CY7C1334F-133AC [CYPRESS]
ZBT SRAM, 64KX32, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | CY7C1334F-133AC |
| 厂家： | 
CYPRESS |
| 描述： | ZBT SRAM, 64KX32, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1334F
2-Mbit (64K x 32) Pipelined SRAM
with NoBL™ Architecture
Functional Description[1]
Features
• Pin compatible and functionally equivalent to ZBT™
The CY7C1334F is a 3.3V, 64K x 32 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1334F is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consec-
utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device)
Write operations are controlled by the four Byte Write Select
(BW[A:D]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 64K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable (OE)
• JEDEC-standard 100-pin TQFP package
• Burst Capability—linear or interleaved burst order
• “ZZ” Sleep mode option
• Available in 100-pin TQFP package
.
Logic Block Diagram
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
Q1
A0'
Q0
D1
D0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
WRITE
DRIVERS
BW
A
B
A
M
P
BW
BW
C
D
S
T
E
R
S
F
BW
E
R
S
S
WE
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05436 Rev. *A
Revised April 9, 2004
CY7C1334F
.
Selection Guide
166MHz
3.5
133 MHz
4.0
Unit
ns
Maximum Access Time (tCO
)
Maximum Operating Current (IDD
Maximum CMOS Standby Current
)
240
40
225
40
mA
mA
Shaded area contains advance information. Please contact your local Cypress sales representative for availability of this part.
Pin Configuration
100-Pin TQFP
1
2
3
4
5
6
7
8
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ
DQ
B
DQ
DQ
C
C
B
V
V
V
DDQ
DDQ
V
SSQ
SSQ
DQ
DQ
DQ
DQ
DQ
C
C
C
C
BYTE B
B
B
B
B
BYTE C
DQ
DQ
DQ
V
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
SSQ
SSQ
DDQ
V
DDQ
DQ
DQ
DQ
C
B
B
CY7C1334F
DQ
C
NC
V
SS
V
NC
DD
NC
V
DD
ZZ
V
SS
DQ
DQ
DQ
V
D
A
A
DQ
D
V
V
DDQ
DDQ
SSQ
V
SSQ
DQ
DQ
DQ
DQ
DQ
V
D
D
D
D
A
A
A
A
DQ
DQ
DQ
BYTE A
BYTE D
V
V
SSQ
SSQ
DDQ
V
DDQ
DQ
DQ
DQ
NC
D
A
A
DQ
D
NC
Document #: 38-05436 Rev. *A
Page 2 of 14
CY7C1334F
Pin Definitions
Name
TQFP
I/O
Description
A0, A1, A
37,36,32,
33,34,35,
44,45,46,
47,48,49,
81,82,
Input-
Address Inputs used to select one of the 64K address locations.
Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst
counter.
Synchronous
99,100
Input-
Byte Write Inputs, active LOW. Qualified with WE to conduct writes
93,94,
95,96
88
BW[A:D]
WE
Synchronous
to the SRAM. Sampled on the rising edge of CLK.
Input-
Write Enable Input, active LOW. Sampled on the rising edge of CLK
if CEN is active LOW. This signal must be asserted LOW to initiate a
Write sequence.
Synchronous
ADV/LD
Input-
Advance/Load Input. Used to advance the on-chip address counter
or load a new address. When HIGH (and CEN is asserted LOW) the
internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
85
Synchronous
CLK
CE1
CE2
CE3
OE
89
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device.
CLK is qualified with CEN. CLK is only recognized if CEN is active
LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of
CLK. Used in conjunction with CE2 and CE3 to select/deselect the
device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of
CLK. Used in conjunction with CE1 and CE3 to select/deselect the
device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of
CLK. Used in conjunction with CE1 and CE2 to select/deselect the
device.
Output Enable, asynchronous input, active LOW. Combined with
the synchronous logic block inside the device to control the direction
of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as
input data pins. OE is masked during the data portion of a write se-
quence, during the first clock when emerging from a deselected state,
when the device has been deselected.
Input-
98
97
Synchronous
Input-
Synchronous
Input-
92
86
Synchronous
Input-
Asynchronous
CEN
Input-
Clock Enable Input, active LOW. When asserted LOW the Clock
signal is recognized by the SRAM. When deasserted HIGH the Clock
signal is masked. Since deasserting CEN does not deselect the de-
vice, CEN can be used to extend the previous cycle when required.
ZZ “sleep” Input. This active HIGH input places the device in a
non-time critical “sleep” condition with data integrity preserved. During
normal operation, this pin can be connected to VSS or left floating.
87
64
Synchronous
ZZ
Input-
Asynchronous
DQs
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,
7,8,9,12,
13,18,19,
22,23,24,
25,28,29
I/O-
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, they
deliver the data contained in the memory location specified by A[16:0]
during the clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted
LOW, the pins can behave as outputs. When HIGH, DQs are placed
in a three-state condition. The outputs are automatically three-stated
during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
Synchronous
MODE
31
Input
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence.
Strap pin
Document #: 38-05436 Rev. *A
Page 3 of 14
CY7C1334F
Pin Definitions (continued)
Name
TQFP
I/O
Description
VDD
15,16,41,65,
Power Supply
Power supply inputs to the core of the device.
66,91
VDDQ
4,11,14,20,
27,54,61,70
17,40,67,90
I/O Power
Supply
Ground
Power supply for the I/O circuitry.
Ground for the device.
VSS
VSSQ
5,10,21,26,
55,60,71,76
I/O Ground
Ground for the I/O circuitry. Should be connected to the ground of
the system
NC
1,30,38,39,
42,43,50,51,
80,83,84
No Connects. Not internally connected to the die.
Document #: 38-05436 Rev. *A
Page 4 of 14
CY7C1334F
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of Chip Enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Functional Overview
The CY7C1334F is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.5 ns (166-MHz
device).
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address inputs
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and
DQP[A:D]. In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BW[A:D] can be used to
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
On the next clock rise the data presented to DQs (or a subset
for Byte Write operations, see Write Cycle Description table for
details) inputs is latched into the device and the write is
complete.
The data written during the Write operation is controlled by
BW[A:D] signals. The CY7C1334F provides Byte Write
capability that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW[A:D]) input will selectively write to only the
desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the Write
operations. Byte write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple Byte Write operations.
Because the CY7C1334F is a common I/O device, data should
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before
presenting data to the DQs. Doing so will three-state the output
drivers. As a safety precaution, DQs are automatically
three-stated during the data portion of a Write cycle,
regardless of the state of OE.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus, provided OE
is active LOW. After the first clock of the read access the output
buffers are controlled by OE and the internal control logic. OE
must be driven LOW in order for the device to drive out the
requested data. During the second clock, a subsequent
operation (Read/Write/Deselect) can be initiated. Deselecting
the device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output will three-state following the next clock rise.
Burst Write Accesses
The CY7C1334F has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BW[A:D] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Burst Read Accesses
The CY7C1334F has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
Document #: 38-05436 Rev. *A
Page 5 of 14
CY7C1334F
Sleep Mode
Linear Burst Address Table
(MODE = GND)
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
First
Second
Address
A1, A0
Third
Fourth
Address
A1, A0
Address
A1, A0
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Cycle Description Truth Table[2, 3, 4, 5, 6, 7, 8]
Address
Operation
Deselect Cycle
Used
CE
H
X
ZZ
L
L
ADV/LD
WE
X
X
BWx
X
X
OE
CEN
CLK
L-H
L-H
DQ
Three-State
Three-State
None
None
L
H
X
X
L
L
Continue
Deselect Cycle
Read Cycle
External
Next
L
X
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
X
H
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
Data Out (Q)
Data Out (Q)
Three-State
Three-State
Data In (D)
Data In (D)
Three-State
Three-State
-
(Begin Burst)
Read Cycle
L
(Continue Burst)
NOP/Dummy Read
(Begin Burst)
External
Next
H
H
X
X
X
X
X
X
Dummy Read
X
L
H
L
(Continue Burst)
Write Cycle
External
Next
(Begin Burst)
Write Cycle
X
L
H
L
X
L
L
(Continue Burst)
NOP/WRITE ABORT
(Begin Burst)
WRITE ABORT
(Continue Burst)
IGNORE CLOCK EDGE Current
(Stall)
SNOOZE MODE
None
H
H
X
X
Next
X
X
X
H
X
X
X
X
X
None
Three-State
Notes:
2. X = “Don't Care.” H = HIGH, L = LOW. CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies
that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
3. Write is defined by BW
, and WE. See Write Cycle Descriptions table.
[A:D]
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
OE is inactive or when the device is deselected, and DQs = data when OE is active.
= Three-state when
[A:D]
Document #: 38-05436 Rev. *A
Page 6 of 14
CY7C1334F
Write Cycle Description[2, 3]
Function
Read
Write − No bytes written
Write Byte A − (DQA)
Write Byte B − (DQB)
Write Bytes A, B
Write Byte C − (DQC)
Write Bytes C,A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D − (DQD)
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BWD
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
BWC
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
BWB
BWA
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ inactive to exit snooze current
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
40
2tCYC
Unit
mA
ns
ns
ns
ns
2tCYC
0
2tCYC
tRZZI
Document #: 38-05436 Rev. *A
Page 7 of 14
CY7C1334F
Current into Outputs (LOW)......................................... 20 mA
Maximum Rating
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Operating Range
Power Applied.................................................. −55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Range Temperature (TA)
VDD
VDDQ
DC Voltage Applied to Outputs
Com’l
0°C to +70°C
3.3V - 5%/+10% 3.3V - 5%
to VDD
in Three-State ..........................................−0.5V to VDDQ + 0.5V
DC Input Voltage ....................................... −0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range[9, 10]
Parameter
VDD
VDDQ
VOH
VOL
VIH
Description
Test Conditions
Min.
3.135
3.135
2.4
Max.
3.6
VDD
Unit
V
V
V
V
V
V
µA
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
0.4
VDD + 0.3V
Input HIGH Voltage[9] VDDQ = 3.3V
2.0
–0.3
−5
VIL
IX
Input LOW Voltage[9]
VDDQ = 3.3V
GND ≤ VI ≤ VDDQ
0.8
5
Input Load Current
except ZZ and MODE
Input Current of MODE Input = VSS
Input = VDD
−30
−5
µA
µA
µA
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
30
5
IOZ
IDD
Output Leakage
Current
GND ≤ VI ≤ VDDQ, Output Disabled
−5
VDD Operating Supply VDD = Max., IOUT = 0 mA,
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
240
225
100
90
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
Automatic CE
VDD = Max, Device Deselected,
Power-Down
VIN ≥ VIH or VIN ≤ VIL
Current—TTL Inputs
f = fMAX = 1/tCYC
Automatic CE
VDD = Max, Device Deselected,
All speeds
40
mA
Power-Down
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V, f
Current—CMOS Inputs = 0
Automatic CE
VDD = Max, Device Deselected, or 6-ns cycle, 166 MHz
85
75
mA
mA
Power-Down
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V
7.5-ns cycle, 133 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
ISB4
Automatic CE
VDD = Max, Device Deselected,
All Speeds
45
mA
Power-Down
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Notes:
9. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
.
10. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
DDQ DD
Power-up
DD
IH
DD
Document #: 38-05436 Rev. *A
Page 8 of 14
CY7C1334F
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
]
Thermal Resistance[11
TQFP
Parameter
Description
Test Conditions
Package.
Units
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51
41.83
9.99
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
°C/W
Capacitance[11]
Parameter
CIN
Description
Test Conditions
Max.
Unit
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 3.3V,
5
pF
pF
pF
CCLK
Clock Input Capacitance
Input/Output Capacitance
5
5
V
DDQ = 3.3V
CI/O
Note:
11. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05436 Rev. *A
Page 9 of 14
CY7C1334F
Switching Characteristics Over the Operating Range[12]
166 MHz
133 MHz
Parameter
tPOWER
Description
Min.
1
Max.
Min.
1
Max.
Unit
ms
VDD (typical) to the First Access[13]
Clock
tCYC
tCH
Clock Cycle Time
Clock HIGH
Clock LOW
6.0
2.5
2.5
7.5
3.0
3.0
ns
ns
ns
tCL
Output Times
tCO
tDOH
tCLZ
tCHZ
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z[14, 15, 16]
3.5
4.0
ns
ns
ns
ns
ns
ns
ns
2.0
0
2.0
0
Clock to High-Z[14, 15, 16]
3.5
3.5
4.0
4.5
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Set-up Times
tAS
tALS
tWES
tCENS
tDS
tCES
OE LOW to Output Low-Z[14, 15, 16]
OE HIGH to Output High-Z[14, 15, 16]
0
0
3.5
4.0
Address Set-up before CLK Rise
ADV/LD Set-up before CLK Rise
GW, BW[A:D] Set-up before CLK Rise
CEN Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Hold Times
tAH
tALH
tWEH
tCENH
tDH
Address Hold after CLK Rise
ADV/LD Hold after CLK Rise
GW, BW[A:D] Hold after CLK Rise
CEN Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tCEH
Notes:
12. Test conditions shown in (a), (b) and (c) of AC Test Loads.
13. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V minimum initially before a Read or Write operation
DD
POWER
14. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
15. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions
16. This parameter is sampled and not 100% tested.
Document #: 38-05436 Rev. *A
Page 10 of 14
CY7C1334F
Switching Waveforms
Read/Write Timing[17, 18, 19]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
CEN
t
t
t
CENS CENH
CL
CH
t
t
CES
CEH
CE
ADV/LD
WE
BW[A:D]
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
For this waveform ZZ is tied LOW.
17.
18. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
19. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05436 Rev. *A
Page 11 of 14
CY7C1334F
Switching Waveforms (continued)
NOP, STALL, and Deselect Cycles[17, 18, 20]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW[A:D]
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
ZZ Mode Timing[21, 22]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
20. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
21. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
22. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05436 Rev. *A
Page 12 of 14
CY7C1334F
Ordering Information
Speed
Package
Name
A101
Operating
Range
Commercial
(MHz)
Ordering Code
CY7C1334F-133AC
Package Type
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
133
Shaded area contains advance information. Please contact your local Cypress sales representative for availability of this part.
Please contact your local Cypress sales representative for availability of 166-MHz speed grade option
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
SEE DETAIL
A
(ꢀX)
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
0°-7°
0.60 0.ꢁ5
ꢁ.00 REF.
0.20 MIN.
51-85050-*A
DETAIL
A
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05436 Rev. *A
Page 13 of 14
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1334F
Document History Page
Document Title: CY7C1334F 2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05436
Orig. of
REV.
**
*A
ECN NO. Issue Date Change
Description of Change
New Data Sheet
200903
See ECN
NJY
VBL
213342
See ENC
Update Ordering Info section: shade part number, add explanation
Shade Selection Guide and Characteristics table
Document #: 38-05436 Rev. *A
Page 14 of 14
相关型号：
CY7C1335-100AC
Cache SRAM, 32KX32, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
CY7C1335L-133AC
Cache SRAM, 32KX32, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
©2020 ICPDF网 联系我们和版权申明