CY7C1339B-100BGCT_技术文档

CY7C1339B

128K x 32 Synchronous Pipelined Cache RAM

The CY7C1339B I/O pins can operate at either the 2.5V or the

3.3V level; the I/O pins are 3.3V-tolerant when V_DDQ= 2.5V.

Features

• Supports 100-MHz bus for Pentium and PowerPC

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise is 3.5 ns (166-MHz

device).

operations with zero wait states

• Fully registered inputs and outputs for pipelined

operation

• 128K × 32 common I/O architecture

• 3.3V core power supply

• 2.5V / 3.3V I/O operation

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

The CY7C1339B supports either the interleaved burst

sequence used by the Intel Pentium processor or a linear burst

sequence used by processors such as the PowerPC. The

burst sequence is selected through the MODE pin. Accesses

can be initiated by asserting either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC) at

clock rise. Address advancement through the burst sequence

is controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

— 4.0 ns (for 133-MHz device)

— 5.5 ns (for 100-MHz device)

• User-selectable burst counter supporting Intel

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Offered in JEDEC-standard 100-pin TQFP and 119-ball

BGA packages

• “ZZ” Sleep Mode and Stop Clock options

Byte Write operations are qualified with the four Byte Write

Select (BW_[3:0]) inputs. A Global Write Enable (GW) overrides

all Byte Write inputs and writes data to all four bytes. All Writes

are conducted with on-chip synchronous self-timed Write

circuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to provide

proper data during depth expansion, OE is masked during the

first clock of a Read cycle when emerging from a deselected

state.

Functional Description

The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined

cache SRAM designed to support zero wait state secondary

cache with minimal glue logic.

MODE

Logic Block Diagram

2

(A_[1;0]

)

Q

CLK

ADV

ADSC

0

BURST

COUNTER

CE

CLR

1

ADSP

Q

15

17

ADDRESS

REGISTER

CE

D

128K × 32

MEMORY

ARRAY

A_[16:0]

GW

17

15

Q

DQ[31:24]

D

BYTEWRITE

REGISTERS

BWE

BW

3

D

DQ[23:16]

BYTEWRITE

REGISTERS

BW

2

DQ[15:8]

BYTEWRITE

REGISTERS

BW

1

DQ[7:0]

BYTEWRITE

REGISTERS

BW

0

32

CE

1

2

CE

D

ENABLE

CE REGISTER

CLK

Q

CE

3

D

Q

OUTPUT

INPUT

ENABLE DELAY

REGISTER

CLK

REGISTERS

CLK

OE

ZZ

SLEEP

CONTROL

DQ_[31:0]

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05141 Rev. *A

Revised March 27, 2002

CY7C1339B

Selection Guide

7C1339B-166

7C1339B-133

7C1339B-100

Unit

ns

Maximum Access Time

3.5

420

10

4.0

375

10

5.5

325

10

Maximum Operating Current

Maximum CMOS Standby Current

mA

Pin Configurations

NC

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQ

16

17

DQ

V

15

14

V

DDQ

SSQ

V

DQ

18

19

DQ

V

13

12

11

10

BYTE2

BYTE1

20

21

9

V

SSQ

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

SSQ

DDQ

V

DQ

22

23

DQ

V

9

8

NC

100-pin TQFP

CY7C1339B

SS

V

DD

NC

V

DD

V

SS

ZZ

DQ

24

25

7

6

V

DDQ

V

DDQ

SSQ

DQ

26

27

DQ

V

5

4

3

2

BYTE3

BYTE0

28

29

V

SSQ

DDQ

V

DDQ

DQ

30

31

DQ

NC

1

0

NC

Document #: 38-05141 Rev. *A

Page 2 of 17

CY7C1339B

Pin Configurations (continued)

119-ball BGA

CY7C1339B (128K × 32)

1

2

A

3

A

4

5

A

6

A

7

A

V_DDQ

NC

ADSP

ADSC

V_DD

V_DDQ

NC

B

C

CE₂

A

NC

A

NC

D

E

F

DQ_c

NC

V_SS

BW_c

V_SS

NC

CE₁

OE

V_SS

BW_b

V_SS

NC

DQ_b

V_DDQ

DQ_b

V_DDQ

DQ_a

DQ_c

V_DD

DQ_d

DQ_b

V_DD

DQ_a

V_DDQ

DQ_c

G

H

J

ADV

GW

V_DD

CLK

DQ_c

V_DDQ

DQ_d

K

V_SS

L

M

N

DQ_d

V_DDQ

DQ_d

BW_d

V_SS

NC

BWE

A1

BW_a

V_SS

DQ_a

V_DDQ

DQ_a

P

R

T

DQ_d

NC

A

V_SS

MODE

A

A0

V_DD

A

V_SS

V_DD

A

NC

A

DQ_a

NC

DNU

NC

ZZ

U

V_DDQ

DNU

V_DDQ

Document #: 38-05141 Rev. *A

Page 3 of 17

CY7C1339B

Pin Definitions

Pin Name

I/O

Input-

Pin Description

Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the

A_[16:0]

Synchronous CLK if ADSP or ADSC is active LOW, and CE₁, CE₂, and CE₃are sampled active. A_[1:0]feed the

two-bit counter.

BW_[3:0]

GW

Input-

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.

Synchronous Sampled on the rising edge of CLK.

Input-

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global

Synchronous Write is conducted (ALL bytes are written, regardless of the values on BW_[3:0]and BWE).

BWE

CLK

CE₁

CE₂

CE₃

OE

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be

Synchronous asserted LOW to conduct a Byte Write.

Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst

counter when ADV is asserted LOW, during a burst operation.

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

Synchronous CE₂and CE₃to select/deselect the device. ADSP is ignored if CE₁is HIGH.

Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

Synchronous CE₁and CE₃to select/deselect the device.

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

Synchronous CE₁and CE₂to select/deselect the device.

Input-

Output Enable, AsynchronousInput, activeLOW. Controls the direction of theI/O pins. WhenLOW,

Asynchronous the I/O pins behave as outputs. When deserted HIGH, I/O pins are three-stated, and act as input

data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected

state.

ADV

Input-

Advance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically incre-

Synchronous ments the address in a burst cycle.

ADSP

Input-

Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A_[16:0]

Synchronous is captured in the address registers. A_[1:0]are also loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE₁is deserted HIGH.

ADSC

ZZ

Input-

Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A_[16:0]

Synchronous is captured in the address registers. A_[1:0]are also loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized.

Input-

ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition

Asynchronous with data integrity preserved. Leaving ZZ floating or NC will default the device into an active state.

ZZ has an internal pull down.

DQ_[31:0]

I/O-

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by

Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified

by A_[16:0]during the previous clock rise of the Read cycle. The direction of the pins is controlled

by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ_[31:0]are placed

in a three-state condition.

V_DD

Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply.

V_SS

Ground

Ground for the core of the device. Should be connected to ground of the system.

Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.

V_DDQ

I/O Power

Supply

V_SSQ

I/O Ground Ground for the I/O circuitry. Should be connected to ground of the system.

MODE

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V_DDQor left

floating selects interleaved burst sequence. This is a strap pin and should remain static during

device operation. When left floating or NC, defaults to interleaved burst order. Mode pin has an

internal pull up.

NC

–

No Connects.

DNU

-

Do Not Use pins. These pins could be left floating or tied to GND.

Document #: 38-05141 Rev. *A

Page 4 of 17

CY7C1339B

data presented to the DQ_[31:0]inputs is written into the corre-

sponding address location in the RAM core. If GW is HIGH,

then the Write operation is controlled by BWE and BW_[3:0]

signals. The CY7C1339B provides Byte Write capability that

is described in the Write Cycle Descriptions table. Asserting

the Byte Write Enable input (BWE) with the selected Byte

Write (BW_[3:0]) input will selectively write to only the desired

bytes. Bytes not selected during a Byte Write operation will

remain unaltered. A synchronous self-timed Write mechanism

has been provided to simplify the Write operations.

Introduction

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise (t_CO) is 3.5 ns

(166-MHz device).

The CY7C1339B supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Because the CY7C1339B is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

to the DQ_[31:0]inputs. Doing so will three-state the output

drivers. As a safety precaution, DQ_[31:0]are automatically

three-stated whenever a Write cycle is detected, regardless of

the state of OE.

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deserted HIGH, (3) CE₁, CE₂, CE₃are all asserted active, and

(4) the appropriate combination of the Write inputs (GW, BWE,

and BW_[3:0]) are asserted active to conduct a Write to the

desired byte(s). ADSC-triggered Write accesses require a

single clock cycle to complete. The address presented to

A_[16:0]is loaded into the address register and the address

advancement logic while being delivered to the RAM core. The

ADV input is ignored during this cycle. If a global Write is

conducted, the data presented to the DQ_[31:0]is written into the

corresponding address location in the RAM core. If a Byte

Write is conducted, only the selected bytes are written. Bytes

not selected during a Byte Write operation will remain

unaltered. A synchronous self-timed Write mechanism has

been provided to simplify the Write operations.

Byte Write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW_[3:0]) inputs. A Global Write

Enable (GW) overrides all Byte Write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. ADSP is ignored if

CE₁is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

CE₁, CE₂, CE₃are all asserted active, and (3) the Write

signals (GW, BWE) are all deserted HIGH. ADSP is ignored if

CE₁is HIGH. The address presented to the address inputs

(A_[16:0]) is stored into the address advancement logic and the

Address Register while being presented to the memory core.

The corresponding data is allowed to propagate to the input of

the Output Registers. At the rising edge of the next clock the

data is allowed to propagate through the output register and

onto the data bus within 3.5 ns (166-MHz device) if OE is

active LOW. The only exception occurs when the SRAM is

emerging from a deselected state to a selected state, its

outputs are always three-stated during the first cycle of the

access. After the first cycle of the access, the outputs are

controlled by the OE signal. Consecutive single Read cycles

are supported. Once the SRAM is deselected at clock rise by

the chip select and either ADSP or ADSC signals, its output

will three-state immediately.

Because the CY7C1339B is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

to the DQ_[31:0]inputs. Doing so will three-state the output

drivers. As a safety precaution, DQ_[31:0]are automatically

three-stated whenever a Write cycle is detected, regardless of

the state of OE.

Burst Sequences

The CY7C1339B provides a two-bit wraparound counter, fed

by A_[1:0], that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed specif-

ically to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a

linear burst sequence. The burst sequence is user selectable

through the MODE input.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both Read and Write burst operations are supported.

Interleaved Burst Sequence

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE₁, CE₂, CE₃are all asserted active. The address

presented to A_[16:0]is loaded into the address register and the

address advancement logic while being delivered to the RAM

core. The Write signals (GW, BWE, and BW_[3:0]) and ADV

inputs are ignored during this first cycle.

First

Address

Second

Address

Third

Address

Fourth

Address

A_[1:0]

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

ADSP-triggered Write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

Document #: 38-05141 Rev. *A

Page 5 of 17

CY7C1339B

Sleep Mode

Linear Burst Sequence

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE₁, CE₂, CE₃, ADSP, and ADSC must

remain inactive for the duration of t_ZZRECafter the ZZ input

returns LOW.

First

Second

Third

Fourth

Address

A_[1:0]

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

I_DDZZ

Description

Snooze mode standby current

Device operation to ZZ

ZZ recovery time

Test Conditions

ZZ > V_DD– 0.2V

ZZ < 0.2V

Min.

Max.

3

Unit

mA

ns

t_ZZS

2t_CYC

t_ZZREC

2t_CYC

ns

Cycle Descriptions^{[1, 2, 3]}

Next Cycle

Unselected

Add. Used

None

ZZ

L

H

CE₃

X

1

CE₂

X

0

CE₁

1

ADSP

X

0

ADSC

ADV

OE

X

1

DQ

Hi-Z

Write

X

0

X

0

X

0

1

0

1

X

0

1

X

0

1

X

Unselected

None

0

Hi-Z

DQ

X

Unselected

None

X

1

0

X

Unselected

None

X

0

1

X

Unselected

None

X

0

1

X

Begin Read

External

0

X

Begin Read

0

1

0

1

Read

Write

X

Continue Read

Suspend Read

Begin Write

X

0

X

1

X

1

0

X

1

Hi-Z

DQ

0

Current

External

X

1

Hi-Z

DQ

1

0

X

1

Hi-Z

DQ

1

0

X

1

X

Hi-Z

Begin Write

X

1

Begin Write

0

Continue Write

Suspend Write

X

1

Current

None

X

1

X

ZZ “Sleep”

X

Notes:

1. X = “Don't Care,” 1 = HIGH, 0 = LOW.

2. Write is defined by BWE, BW_[3:0], and GW. See Write Cycle Descriptions table.

3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

Document #: 38-05141 Rev. *A

Page 6 of 17

CY7C1339B

Write Cycle Descriptions^{[4, 5, 6]}

Function

GW

1

BWE

1

BW₃

X

1

BW₂

X

1

BW₁

BW₀

X

1

Read

X

1

0

1

0

1

0

1

0

X

Read

1

0

Write Byte 0 – DQ_[7:0]

Write Byte 1 – DQ_[15:8]

Write Bytes 1, 0

Write Byte 2 – DQ_[23:16]

Write Bytes 2, 0

Write Bytes 2, 1

Write Bytes 2, 1, 0

Write Byte 3 – DQ_[31:24]

Write Bytes 3, 0

Write Bytes 3, 1

Write Bytes 3, 1, 0

Write Bytes 3, 2

Write Bytes 3, 2, 0

Write Bytes 3, 2, 1

Write All Bytes

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Write All Bytes

0

X

Notes:

4. X = “don't care,” 1 = Logic HIGH, 0 = Logic LOW.

5. The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW_[3:0].Writes may occur only on subsequent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE

is a don't care for the remainder of the Write cycle.

6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ = High-Z when OE is inactive

or when the device is deselected, and DQ = data when OE is active.

Document #: 38-05141 Rev. *A

Page 7 of 17

CY7C1339B

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Static Discharge Voltage .......................................... >2001V

(per MIL-STD-883, Method 3015)

Storage Temperature ..................................... −65°C to +150°C

Latch-Up Current.................................................... >200 mA

Ambient Temperature with

Power Applied.................................................. −55°C to +125°C

Operating Range

Supply Voltage on V_DDRelative to GND.........−0.5V to +4.6V

Ambient

Range

Commercial

Industrial

Temperature^[8]

0°C to +70°C

V_DD

V_DDQ

DC Voltage Applied to Outputs

in High Z State^[7]....................................... −0.5V to V_DD+ 0.5V

3.3V

2.5V −5%

−5%/+10% 3.3V /+10%

DC Input Voltage^[7].................................... −0.5V to V_DD+ 0.5V

–40°C to +85°C

Current into Outputs (LOW).........................................20 mA

Electrical Characteristics Over the Operating Range

Parameter

V_DD

Description

Test Conditions

Min.

3.135

2.375

2.4

Max.

3.6

Unit

V

Power Supply Voltage 3.3V −5%/+10%

V_DDQ

I/O Supply Voltage

2.5V −5% to 3.3V +10%

3.6

V

V_OH

Output HIGH Voltage

V_DDQ= 3.3V, V_DD= Min., I_OH= –4.0 mA

V_DDQ= 2.5V, V_DD= Min., I_OH= –2.0 mA

V_DDQ= 3.3V, V_DD= Min., I_OL= 8.0 mA

V

2.0

V

V_OL

V_IH

V_IL

I_X

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage^[7]

0.4

0.7

V

_DDQ= 2.5V, V_DD= Min., I_OL= 2.0 mA

V

V_DDQ= 3.3V

V_DDQ= 2.5V

V_DDQ= 3.3V

V_DDQ= 2.5V

GND ≤ V_I≤ V_DDQ

2.0

1.7

V_DD+ 0.3V

0.8

V

–0.3

−5

V

0.7

V

Input Load Current

except ZZ and MODE

5

µA

Input Current of MODE Input = V_SS

Input = V_DDQ

−30

−5

µA

5

Input Current of ZZ

Input = V_SS

Input = V_DDQ

30

5

I_OZ

I_DD

Output Leakage

Current

GND ≤ V_I≤ V_DDQ,Output Disabled

−5

V_DDOperating Supply V_DD= Max., I_OUT= 0 mA,

6-ns cycle, 166 MHz

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

6-ns cycle, 166 MHz

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

All speeds

420

375

325

150

125

115

10

mA

Current

f = f_MAX= 1/t_CYC

I_SB1

Automatic CS

Power-Down

Current—TTL Inputs

Max. V_DD, Device Deselected,

V_IN≥ V_IHor V_IN≤ V_IL

f = f_MAX= 1/t_CYC

I_SB2

Automatic CS

Power-Down

Current—CMOS Inputs f = 0

Max. V_DD, Device Deselected,

V_IN≤ 0.3V or V_IN> V_DDQ– 0.3V,

I_SB3

Automatic CS

Power-Down

Current—CMOS Inputs f = f_MAX= 1/t_CYC

Max. V_DD, Device Deselected, or 6-ns cycle, 166 MHz

125

95

mA

V_IN≤ 0.3V or V_IN> V_DDQ– 0.3V

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

85

I_SB4

Automatic CS

Power-Down

Current—TTL Inputs

Max. V_DD, Device Deselected,

V_IN≥ V_IHor V_IN≤ V_IL, f = 0

18

Notes:

7. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.

8. _Ais the case temperature.

T

Document #: 38-05141 Rev. *A

Page 8 of 17

CY7C1339B

Capacitance^[9]

Parameter

Description

Input Capacitance

Test Conditions

TQFP Max.

BGA Max.

Unit

pF

C_IN

T_A= 25°C, f = 1 MHz,

V_DD= 3.3V

V_DDQ= 3.3V

4

6

8

C_CLK

C_I/O

Clock Input Capacitance

Input/Output Capacitance

pF

AC Test Loads and Waveforms

R= 317/1667Ω

[10]

3.3/2.5V

OUTPUT

ALL INPUT PULSES

90%

3.0/2.5V

GND

OUTPUT

R = 50Ω

90%

10%

Z = 50Ω

0

10%

L

5 pF

R= 351/1538Ω

≤ 1V/ns

V = 1.5V for 3.3 V

L

DDQ

1.25V for 2.5V V

DDQ

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

Thermal Resistance^[9]

Description

Test Conditions

Symbol

TQFP Typ.

BGA

Units

Thermal Resistance

(Junction to Ambient)

StillAir, solderedona4×4.5inch,

2-layer printed circuit board

Q_JA

41.83

47.63

°C/W

Thermal Resistance

(Junction to Case)

Q_JC

9.99

11.71

°C/W

Note:

9. Tested initially and after any design or process changes that may affect these parameters.

10. Input waveform should have a slew rate of 1 V/ns.

Document #: 38-05141 Rev. *A

Page 9 of 17

CY7C1339B

Switching Characteristics Over the Operating Range^{[10, 12, 13]}

-166

-133

-100

Parameter

t_CYC

t_CH

Description

Clock Cycle Time

Min.

6.0

1.7

1.5

0.5

Max.

Min.

7.5

1.9

1.5

0.5

Max.

Min.

10

Max.

Unit

ns

Clock HIGH

3.5

1.5

0.5

t_CL

Clock LOW

t_AS

Address Set-Up Before CLK Rise

Address Hold After CLK Rise

Data Output Valid After CLK Rise

Data Output Hold After CLK Rise

ADSP, ADSC Set-up Before CLK Rise

ADSP, ADSC Hold After CLK Rise

BWE, GW, BW[3:0] Set-up Before CLK Rise

BWE, GW, BW[3:0] Hold After CLK Rise

ADV Set-Up Before CLK Rise

ADV Hold After CLK Rise

t_AH

t_CO

3.5

4.0

5.5

t_DOH

t_ADS

t_ADH

t_WES

t_WEH

t_ADVS

t_ADVH

t_DS

1.5

2.0

0.5

2.0

0.5

2.0

0.5

1.5

0.5

2.0

0.5

2.0

2.5

0.5

2.5

0.5

2.5

0.5

1.5

0.5

2.5

0.5

2.0

2.5

0.5

2.5

0.5

2.5

0.5

1.5

0.5

2.5

0.5

Data Input Set-up Before CLK Rise

Data Input Hold After CLK Rise

Chip Select Set-up

t_DH

t_CES

t_CEH

t_CHZ

t_CLZ

Chip Select Hold After CLK Rise

Clock to High-Z^[12]

Clock to Low-Z^[12]

OE HIGH to Output High-Z^{[12, 13]}

OE LOW to Output Low-Z^{[12, 13]}

OE LOW to Output Valid^[12]

3.5

4.0

3.5

5.5

0

t_EOHZ

t_EOLZ

t_EOV

Notes:

11. Unless otherwise noted, test conditions assume signal transition time of 3.0/2.5 ns or less, timing reference levels of 1.5/1.25V, input pulse levels of 0 to

3.0/2.5V for 3.3/2.5V V_DDQrespectively, and output loading of the specified I_OL/I_OHand load capacitance. Shown in (a) and (c) of AC test loads diagram.

12. t_CHZ, t_CLZ, t_EOV, t_EOLZ, and t_EOHZare specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mv from

steady-state voltage.

13. At any given voltage and temperature, t_EOHZis less than t_EOLZand t_CHZis less than t_CLZ

.

Document #: 38-05141 Rev. *A

Page 10 of 17

CY7C1339B

Switching Waveforms

Write Cycle Timing^{[14, 15]}

Single Write

t_CYC

t_ADH

Burst Write

Pipelined Write

t_CH

Unselected

CLK

t_ADS

t_CL

ADSP ignored with CE₁inactive

ADSP

ADSC

ADV

t_ADH

t_ADS

ADSC initiated Write

t_ADVH

t_ADVS

t_AS

ADV Must Be Inactive for ADSP Write

WD3

ADD

GW

WE

WD1

WD2

t_AH

t_WH

t_WS

t_CES

t_CEH

CE₁masks ADSP

CE₁

CE₂

t_CEH

t_CES

Unselected with CE₂

CE₃

t_CES

t_CEH

OE

t_DH

t_DS

High-Z

Data In

3a

2a

1a

2b

2c

2d

= DON’T CARE

= UNDEFINED

Notes:

14. WE is the combination of BWE, BW_[3:0], and GW to define a Write cycle (see Write Cycle Descriptions table).

15. WDx stands for Write Data to Address X.

Document #: 38-05141 Rev. *A

Page 11 of 17

CY7C1339B

Switching Waveforms (continued)

Read Cycle Timing^{[14, 16]}

Burst Read

Single Read

t_CYC

Unselected

t_CH

Pipelined Read

CLK

t_ADH

t_ADS

t_CL

ADSP ignored with CE₁inactive

ADSP

t_ADS

ADSC initiated Read

ADSC

ADV

t_ADVS

t_ADH

Suspend Burst

t_ADVH

t_AS

ADD

GW

RD1

RD3

RD2

t_AH

t_WS

t_WH

WE

t_CES

t_CEH

t_WH

CE₁masks ADSP

CE₁

Unselected with CE₂

CE₂

t_CES

t_CEH

CE₃

OE

t_CES

t_DOE

t_CEH

t_OEHZ

t_DOH

t_CO

Data Out

2c

1a

2d

3a

2a

2b

t_CLZ

t_CHZ

= DON’T CARE

= UNDEFINED

Note:

16. RDx stands for Read Data from Address X.

Document #: 38-05141 Rev. *A

Page 12 of 17

CY7C1339B

Switching Waveforms (continued)

Read/Write Cycle Timing^{[14, 15, 16, 17]}

Single Read

t_CYC

Single Write

t_CH

Unselected

Burst Read

Pipelined Read

CLK

t_ADH

t_ADS

t_CL

ADSP ignored with CE₁inactive

ADSP

ADSC

ADV

t_ADS

t_ADVS

t_ADH

t_AS

t_ADVH

WD2

ADD

GW

RD1

RD3

t_AH

t_WS

t_WH

WE

t_CES

t_CEH

t_WH

CE₁masks ADSP

CE₁

CE₂

t_CES

t_CEH

CE₃

OE

t_CES

t_DOE

t_CEH

t_OEHZ

t_DS

t_DH

t_DOH

See Note 17

2a

t_OELZ

t_CO

3b

Out

3c

Out

3a

Out

3d

Out

Data In/Out

1a

2a

In

Out

t_CHZ

= UNDEFINED

= DON’T CARE

Note:

17. Data bus is driven by SRAM, but data is not guaranteed.

Document #: 38-05141 Rev. *A

Page 13 of 17

CY7C1339B

Switching Waveforms (continued)

ZZ Mode Timing ^{[18, 19]}

CLK

ADSP

HIGH

ADSC

CE₁

LOW

CE₂

HIGH

CE₃

ZZ

t_ZZS

I_DD

I_DD(active)

t_ZZREC

I_DDZZ

I/Os

Three-state

Notes:

18. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

19. I/Os are in three-state when exiting ZZ sleep mode.

Document #: 38-05141 Rev. *A

Page 14 of 17

CY7C1339B

Ordering Information

Speed

Package

Name

Operating

Range

(MHz)

Ordering Code

Package Type

100-lead Thin Quad Flat Pack

119-ball BGA

166

CY7C1339B-166AC

CY7C1339B-166BGC

CY7C1339B-133AC

CY7C1339B-133BGC

CY7C1339B-133AI

CY7C1339B-133BGI

CY7C1339B-100AC

CY7C1339B-100BGC

CY7C1339B-100AI

CY7C1339B-100BGI

A101

BG119

A101

Commercial

Industrial

133

100

100-lead Thin Quad Flat Pack

119-ball BGA

BG119

A101

100-lead Thin Quad Flat Pack

119-ball BGA

BG119

A101

100-lead Thin Quad Flat Pack

119-ball BGA

Commercial

Industrial

BG119

A101

100-lead Thin Quad Flat Pack

119-ball BGA

BG119

Package Diagrams

100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-A

Document #: 38-05141 Rev. *A

Page 15 of 17

CY7C1339B

Package Diagrams (continued)

119-Lead PBGA (14 x 22 x 2.4 mm) BG119

51-85115-*A

i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a registered trademark of

IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.

Document #: 38-05141 Rev. *A

Page 16 of 17

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1339B

Document Title: CY7C1339B 128K x 32 Synchronous Pipelined Cache RAM

Document Number: 38-05141

Issue

Date

Orig. of

Change

REV.

**

ECN NO.

109885

113899

Description of Change

09/15/01

03/29/02

SZV

SKX

Change from Spec number: 38-00936 to 38-05141

*A

Changed the JTAG pins on the BGA package to DNU pins.

Added BGA capacitance.

Added thermal resistance table for both TQFP and BGA.

Document #: 38-05141 Rev. *A

Page 17 of 17


型号：	CY7C1339B-100BGCT
厂家：	CYPRESS
描述：	Cache SRAM, 128KX32, 5.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 静态存储器
文件：	总17页 (文件大小：527K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1339B-100BGCT [CYPRESS]

相关型号：

CY7C1339B-100BGI

CY7C1339B-100BGIT

CY7C1339B-133AC

CY7C1339B-133ACT

CY7C1339B-133AI

CY7C1339B-133AIT

CY7C1339B-133BGC

CY7C1339B-133BGCT

CY7C1339B-133BGI

CY7C1339B-133BGIT

CY7C1339B-166AC

CY7C1339B-166ACT