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CY7C1339F-166AXI [CYPRESS]

Cache SRAM, 128KX32, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
CY7C1339F-166AXI
型号： CY7C1339F-166AXI
厂家： CYPRESS    CYPRESS
描述：

Cache SRAM, 128KX32, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

静态存储器
文件： 总17页 (文件大小：438K)
中文：  中文翻译
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CY7C1339F  
4-Mbit (128K x 32) Pipelined Sync SRAM  
Features  
Functional Description[1]  
• Registered inputs and outputs for pipelined operation  
• 128K × 32 common I/O architecture  
• 3.3V core power supply  
• 2.5V / 3.3V I/O operation  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
— 2.6 ns (for 225-MHz device)  
— 2.8 ns (for 200-MHz device)  
— 3.5 ns (for 166-MHz device)  
The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells  
with advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(
), depth-expansion Chip Enables (CE and  
), Burst  
CE3  
CE1  
2
Control inputs (  
,
,
and  
ADSC ADSP  
), Write Enables  
ADV  
(
, and  
), and Global Write (  
BWE  
). Asynchronous  
GW  
BW[A:D]  
inputs include the Output Enable ( ) and the ZZ pin.  
OE  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (  
) or  
ADSP  
Address Strobe Controller (  
) are active. Subsequent  
ADSC  
— 4.0 ns (for 133-MHz device)  
— 4.5 ns (for 100-MHz device)  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
ADV  
• Provide high-performance 3-1-1-1 access rate  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to four bytes wide as  
• User-selectable burst counter supporting Intel  
Pentiuminterleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
controlled by the byte write control inputs.  
when active  
GW  
causes all bytes to be written.  
LOW  
The CY7C1339F operates from a +3.3V core power supply  
while all outputs may operate with either a +2.5 or +3.3V  
supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
• Offered in JEDEC-standard 100-pin TQFP and 119-ball  
BGA packages  
• “ZZ” Sleep Mode Option  
Logic Block Diagram  
A0, A1,  
A
ADDRESS  
REGISTER  
2
A
[1:0]  
Q1  
MODE  
ADV  
CLK  
BURST  
COUNTER  
CLR AND Q0  
LOGIC  
ADSC  
ADSP  
DQ  
BYTE  
W RITE REGISTER  
D
DQ  
BYTE  
W RITE DRIVER  
D
BW  
D
DQ  
C
DQ  
C
BYTE  
W RITE DRIVER  
BYTE  
W RITE REGISTER  
BW  
C
OUTPUT  
BUFFERS  
OUTPUT  
REGISTERS  
MEMORY  
ARRAY  
SENSE  
AMPS  
D Q s  
DQ  
B
E
DQ  
B
BYTE  
W RITE DRIVER  
BYTE  
W RITE REGISTER  
BW  
BW  
B
DQ  
A
DQ  
A
BYTE  
W RITE DRIVER  
BYTE  
W RITE REGISTER  
A
BW E  
INPUT  
REGISTERS  
GW  
ENABLE  
REGISTER  
PIPELINED  
ENABLE  
CE  
CE  
CE  
1
2
3
OE  
SLEEP  
CONTROL  
ZZ  
1
Note:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05217 Rev. *C  
Revised April 09, 2004  
CY7C1339F  
Selection Guide  
250 MHz  
2.6  
225 MHz  
2.6  
200 MHz  
2.8  
166 MHz  
3.5  
133 MHz  
4.0  
100 MHz  
4.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
325  
40  
290  
40  
265  
40  
240  
40  
225  
40  
205  
40  
mA  
mA  
Shaded areas contain advanced information. Please contact your local Cypress sales representative for availability of these parts.  
Pin Configurations  
NC  
DQC  
DQC  
VDDQ  
VSSQ  
DQC  
DQC  
DQC  
DQC  
VSSQ  
VDDQ  
DQC  
DQC  
NC  
NC  
1
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQB  
DQB  
VDDQ  
VSSQ  
DQB  
DQB  
DQB  
DQB  
VSSQ  
VDDQ  
DQB  
DQB  
VSS  
2
3
4
5
6
BYTE C  
BYTE B  
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
100-pin TQFP  
CY7C1339F  
VDD  
NC  
NC  
VDD  
VSS  
ZZ  
DQD  
DQD  
VDDQ  
VSSQ  
DQD  
DQD  
DQD  
DQD  
VSSQ  
VDDQ  
DQD  
DQD  
NC  
DQA  
DQA  
VDDQ  
VSSQ  
DQA  
DQA  
DQA  
DQA  
VSSQ  
VDDQ  
DQA  
DQA  
NC  
BYTE D  
BYTE A  
Document #: 38-05217 Rev. *C  
Page 2 of 17  
CY7C1339F  
Pin Configurations (continued)  
119-ball BGA  
CY7C1339F (128K × 32)  
1
2
A
CE2  
A
3
A
A
A
4
5
A
A
A
6
A
NC  
A
7
A
B
C
VDDQ  
NC  
NC  
VDDQ  
NC  
NC  
ADSP  
ADSC  
VDD  
DQC  
DQC  
VDDQ  
DQC  
DQC  
VDDQ  
DQD  
NC  
VSS  
VSS  
VSS  
BWc  
VSS  
NC  
NC  
CE1  
OE  
ADV  
GW  
VDD  
CLK  
VSS  
VSS  
VSS  
BWB  
VSS  
NC  
NC  
DQB  
DQB  
VDDQ  
DQB  
DQB  
VDDQ  
DQA  
D
E
F
G
H
J
DQC  
DQC  
DQC  
DQC  
VDD  
DQD  
DQB  
DQB  
DQB  
DQB  
VDD  
DQA  
K
VSS  
VSS  
L
M
N
DQD  
VDDQ  
DQD  
DQD  
DQD  
DQD  
BWD  
VSS  
VSS  
NC  
BWE  
A1  
BWA  
VSS  
VSS  
DQA  
DQA  
DQA  
DQA  
VDDQ  
DQA  
P
R
T
DQD  
NC  
NC  
NC  
A
NC  
VSS  
MODE  
A
A0  
VDD  
A
VSS  
NC  
A
NC  
A
NC  
DQA  
NC  
ZZ  
VDDQ  
NC  
NC  
NC  
NC  
NC  
VDDQ  
U
Pin Definitions  
Name  
A0, A1, A  
BGA  
P4,N4,  
TQFP  
37,36,  
I/O  
Input-  
Description  
Address Inputs used to select one of the 128K address locations.  
A2,C2,R2, 32,33,34, Synchronous Sampled at the rising edge of the CLK if  
or is active LOW,  
ADSP ADSC  
and CE1, CE2, andCE3 are sampled active. A1, A0 are fed to the two-bit  
counter.  
A3,B3,C3, 35,44,45,  
T3,T4,A5, 46,47,48,  
B5,C5,T5, 49,50,81,  
.
A6,C6,R6  
82,99,  
100  
L5,G5,G3, 93,94,95,  
Input-  
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct  
BWA,BWB  
BWC,BWD  
L3  
96  
88  
Synchronous  
.
byte writes to the SRAM. Sampled on the rising edge of CLK  
Input-  
Global Write Enable Input, active LOW. When asserted LOW on the  
H4  
GW  
Synchronous rising edge of CLK, a global write is conducted (ALL bytes are written,  
regardless of the values on BW[A:D] and BWE).  
M4  
K4  
87  
89  
Input-  
Byte Write Enable Input, active LOW. Sampled on the rising edge of  
BWE  
CLK  
Synchronous CLK. This signal must be asserted LOW to conduct a byte write.  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. Also  
used to increment the burst counter when ADV is asserted LOW, during  
a burst operation.  
E4  
B2  
98  
97  
Input-  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.  
CE1  
CE2  
Synchronous Used in conjunction with CE2 and CE3 to select/deselect the device.  
ADSP is ignored if CE1 is HIGH.  
Input-  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.  
Synchronous Used in conjunction with CE1 and CE3 to select/deselect the device.  
Document #: 38-05217 Rev. *C  
Page 3 of 17  
CY7C1339F  
Pin Definitions (continued)  
Name  
BGA  
TQFP  
I/O  
Description  
-
92  
Input-  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.  
CE3  
Synchronous Used in conjunction with CE and CE to select/deselect the device.  
Not  
2
connected for BGA. Where 1referenced, CE3 is assumed active  
throughout this document for BGA.  
F4  
86  
Input-  
Output Enable, asynchronous input, active LOW. Controls the  
OE  
Asynchronous direction of the I/O pins. When LOW, the I/O pins behave as outputs.  
When deasserted HIGH, I/O pins are three-stated, and act as input data  
pins. OE is masked during the first clock of a read cycle when emerging  
from a deselected state.  
G4  
A4  
83  
84  
Input-  
Advance Input signal, sampled on the rising edge of CLK, active  
ADV  
Synchronous LOW. When asserted, it automatically increments the address in a burst  
cycle.  
Input-  
Address Strobe from Processor, sampled on the rising edge of  
ADSP  
Synchronous CLK, active LOW. When asserted LOW, addresses presented to the  
device are captured in the address registers. A1, A0 are also loaded into  
the burst counter. When ADSP and ADSC are both asserted, only ADSP  
is recognized. ASDP is ignored when CE1 is deasserted HIGH.  
85  
64  
Input-  
Address Strobe from Controller, sampled on the rising edge of  
B4  
T7  
ADSC  
Synchronous CLK, active LOW. When asserted LOW, addresses presented to the  
device are captured in the address registers. A1, A0 are also loaded into  
the burst counter. When ADSP and ADSC are both asserted, only ADSP  
is recognized.  
ZZ  
Input-  
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device  
Asynchronous in a non-time-critical “sleep” condition with data integrity preserved. For  
normal operation, this pin has to be LOW or left floating. ZZ pin has an  
internal pull-down.  
K6,L6,M6, 52,53,56,  
I/O-  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data  
DQs  
N6,K7,L7, 57,58,59, Synchronous register that is triggered by the rising edge of CLK. As outputs, they  
N7,P7,E6, 62,63,68,  
F6,G6,H6, 69,72,73,  
D7,E7,G7, 74,75,78,  
H7,D1,E1, 79,2,3,6,  
G1,H1,E2, 7,8,9,12,  
F2,G2,H2, 13,18,19,  
K1,L1,N1, 22,23,24,  
P1,K2,L2, 25,28,29  
M2,N2  
deliver the data contained in the memory location specified by the  
addresses presented during the previous  
clock rise of the read cycle.  
The direction of the pins is controlled by OE. When OE is asserted LOW,  
the pins behave as outputs. When HIGH, DQs are placed in a three-state  
condition.  
VDD  
VSS  
J2,J4,R4 15,41,65, Power Supply Power supply inputs to the core of the device.  
91  
D3,E3,F3, 17,40,67,  
Ground  
Ground for the core of the device.  
K3,M3,N3,  
P3,D5,E5,  
F5,H5,K5,  
M5,N5,P5  
90  
VDDQ  
A1,F1,J1,  
4,11,20,  
I/O Power  
Supply  
Power supply for the I/O circuitry.  
Ground for the I/O circuitry.  
M1,U1,A7, 27,54,61,  
F7,J7,M7,  
70,77  
U7  
VSSQ  
-
5,10,21,  
26,55,60,  
71,76  
I/O Ground  
MODE  
R3  
31  
Input-  
Static  
Selects Burst Order. When tied to GND selects linear burst sequence.  
When tied to VDD or left floating selects interleaved burst sequence. This  
is a strap pin and should remain static during device operation. Mode  
Pin has an internal pull-up.  
Document #: 38-05217 Rev. *C  
Page 4 of 17  
CY7C1339F  
Pin Definitions (continued)  
Name  
BGA  
TQFP  
I/O  
Description  
NC  
B1,C1,R1, 1,14,16,  
T1,D2,P2, 30,38,39,  
T2,U2,J3, 42,43,51,  
No Connects. Not internally connected to the die  
U3,D4,L4,  
U4,J5,U5,  
B6,D6,P6,  
T6,U6,B7,  
C7,R5,R7  
66,80  
Single Write Accesses Initiated by ADSP  
Functional Overview  
This access is initiated when both of the following conditions  
are satisfied at clock rise: (1) ADSP is asserted LOW, and  
(2) CE1, CE2, CE3 are all asserted active. The address  
presented to A is loaded into the address register and the  
address advancement logic while being delivered to the  
memory array. The Write signals (GW, BWE, and BW[A:D]) and  
ADV inputs are ignored during this first cycle.  
ADSP-triggered Write accesses require two clock cycles to  
complete. If GW is asserted LOW on the second clock rise, the  
data presented to the DQs inputs is written into the corre-  
sponding address location in the memory array. If GW is HIGH,  
then the Write operation is controlled by BWE and BW[A:D]  
signals. The CY7C1339F provides Byte Write capability that is  
described in the Write Cycle Descriptions table. Asserting the  
Byte Write Enable input (BWE) with the selected Byte Write  
(BW[A:D]) input, will selectively write to only the desired bytes.  
Bytes not selected during a Byte Write operation will remain  
unaltered. A synchronous self-timed Write mechanism has  
been provided to simplify the Write operations.  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock.  
Maximum access delay from the clock rise (tCO) is 3.5 ns  
(166-MHz device).  
The CY7C1339F supports secondary cache in systems  
utilizing either a linear or interleaved burst sequence. The  
interleaved burst order supports Pentium and i486  
processors. The linear burst sequence is suited for processors  
that utilize a linear burst sequence. The burst order is user  
selectable, and is determined by sampling the MODE input.  
Accesses can be initiated with either the Processor Address  
Strobe (ADSP) or the Controller Address Strobe (ADSC).  
Address advancement through the burst sequence is  
controlled by the ADV input. A two-bit on-chip wraparound  
burst counter captures the first address in a burst sequence  
and automatically increments the address for the rest of the  
burst access.  
Byte Write operations are qualified with the Byte Write Enable  
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write  
Enable (GW) overrides all Byte Write inputs and writes data to  
all four bytes. All writes are simplified with on-chip  
synchronous self-timed Write circuitry.  
Three synchronous Chip Selects (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output three-state control. ADSP is ignored if  
CE1 is HIGH.  
Because the CY7C1339F is a common I/O device, the Output  
Enable (OE) must be deserted HIGH before presenting data  
to the DQs inputs. Doing so will three-state the output drivers.  
As a safety precaution, DQs are automatically three-stated  
whenever a Write cycle is detected, regardless of the state of  
OE.  
Single Write Accesses Initiated by ADSC  
ADSC Write accesses are initiated when the following condi-  
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is  
deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and  
(4) the appropriate combination of the Write inputs (GW, BWE,  
and BW[A:D]) are asserted active to conduct a Write to the  
desired byte(s). ADSC-triggered Write accesses require a  
single clock cycle to complete. The address presented to A is  
loaded into the address register and the address  
advancement logic while being delivered to the memory array.  
The ADV input is ignored during this cycle. If a global Write is  
conducted, the data presented to the DQs is written into the  
corresponding address location in the memory core. If a Byte  
Write is conducted, only the selected bytes are written. Bytes  
not selected during a Byte Write operation will remain  
unaltered. A synchronous self-timed Write mechanism has  
been provided to simplify the Write operations.  
Single Read Accesses  
This access is initiated when the following conditions are  
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)  
CE1, CE2, CE3 are all asserted active, and (3) the Write  
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if  
CE1 is HIGH. The address presented to the address inputs (A)  
is stored into the address advancement logic and the Address  
Register while being presented to the memory array. The  
corresponding data is allowed to propagate to the input of the  
Output Registers. At the rising edge of the next clock the data  
is allowed to propagate through the output register and onto  
the data bus within 3.5 ns (166-MHz device) if OE is active  
LOW. The only exception occurs when the SRAM is emerging  
from a deselected state to a selected state, its outputs are  
always three-stated during the first cycle of the access. After  
the first cycle of the access, the outputs are controlled by the  
OE signal. Consecutive single Read cycles are supported.  
Once the SRAM is deselected at clock rise by the chip select  
and either ADSP or ADSC signals, its output will three-state  
immediately.  
Because the CY7C1339F is a common I/O device, the Output  
Enable (OE) must be deserted HIGH before presenting data  
to the DQs inputs. Doing so will three-state the output drivers.  
As a safety precaution, DQs are automatically three-stated  
whenever a Write cycle is detected, regardless of the state of  
OE.  
Document #: 38-05217 Rev. *C  
Page 5 of 17  
CY7C1339F  
Burst Sequences  
Interleaved Burst Address Table  
(MODE = Floating or VDD  
The CY7C1339F provides a two-bit wraparound counter, fed  
by A1, A0, that implements either an interleaved or linear burst  
sequence. The interleaved burst sequence is designed specif-  
ically to support Intel Pentium applications. The linear burst  
sequence is designed to support processors that follow a  
linear burst sequence. The burst sequence is user selectable  
through the MODE input.  
Asserting ADV LOW at clock rise will automatically increment  
the burst counter to the next address in the burst sequence.  
Both Read and Write burst operations are supported.  
)
First  
Second  
Address  
A1, A0  
Third  
Fourth  
Address  
A1, A0  
Address  
A1, A0  
Address  
A1, A0  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Sleep Mode  
Linear Burst Address Table (MODE = GND)  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
First  
Second  
Address  
A1, A0  
Third  
Address  
A1, A0  
Fourth  
Address  
A1, A0  
Address  
A1, A0  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
t
he “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must  
remain inactive for the duration of tZZREC after the ZZ input  
returns LOW.  
ZZ Mode Electrical Characteristics  
Parameter  
IDDZZ  
tZZS  
Description  
Snooze mode standby current  
Device operation to ZZ  
Test Conditions  
ZZ > VDD – 0.2V  
ZZ > VDD – 0.2V  
Min.  
Max.  
40  
2tCYC  
Unit  
mA  
ns  
tZZREC  
tZZI  
tRZZI  
ZZ recovery time  
ZZ active to snooze current  
ZZ Inactive to exit snooze current  
ZZ < 0.2V  
This parameter is sampled  
This parameter is sampled  
2tCYC  
0
ns  
ns  
ns  
2tCYC  
Truth Table[ 2, 3, 4, 5, 6, 7]  
Operation  
Add. Used  
None  
CE2  
X
L
X
L
CLK  
DQ  
CE3  
X
X
H
X
H
X
L
L
L
L
L
WRITE  
CE1  
ZZ  
ADSP ADSC ADV  
OE  
Deselect Cycle, Power-down  
Deselect Cycle, Power-down  
Deselect Cycle, Power-down  
Deselect Cycle, Power-down  
Deselect Cycle, Power-down  
Snooze Mode, Power-down  
READ Cycle, Begin Burst  
READ Cycle, Begin Burst  
WRITE Cycle, Begin Burst  
READ Cycle, Begin Burst  
READ Cycle, Begin Burst  
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
L-H three-state  
L-H three-state  
L-H three-state  
L-H three-state  
L-H three-state  
None  
None  
None  
None  
L
L
L
L
X
L
L
L
L
L
X
L
L
L
L
H
L
L
L
L
L
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
H
X
L
L
H
H
X
L
X
X
L
None  
X
X
X
L
L
L
X
L-H  
three-state  
Q
External  
External  
External  
External  
External  
Next  
H
H
H
H
H
X
L
L-H three-state  
L-H  
L-H  
L-H three-state  
L-H  
H
H
H
H
D
Q
H
H
H
H
L
READ Cycle, Continue Burst  
X
H
Q
Notes:  
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.  
3. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW ) and BWE = L or GW= L. WRITE = H when all Byte write enable signals  
A
B
C
D
(BW , BW , BW , BW ), BWE, GW = H.  
A
B
C
D
4. The DQ pins are controlled by the current cycle and the  
signal.  
is asynchronous and is not sampled with the clock.  
OE  
OE  
5. CE , CE , and CE are available only in the TQFP package. BGA package has only 2 chip selects CE and CE .  
1
2
3
1
2
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW  
. Writes may occur only on subsequent clocks  
[A: D]  
after the  
or with the assertion of  
. As a result,  
must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state.  
OE  
is  
ADSC  
a don't care for the remainder of the write cycle  
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when  
OE  
ADSP  
7.  
OE  
is  
OE  
.
is active (LOW)  
inactive or when the device is deselected, and all data bits behave as output when  
OE  
Document #: 38-05217 Rev. *C  
Page 6 of 17  
CY7C1339F  
Truth Table[ 2, 3, 4, 5, 6, 7]  
Operation  
Add. Used  
Next  
CE2  
X
X
X
X
X
X
X
X
CLK  
DQ  
L-H three-state  
L-H  
L-H three-state  
CE3  
X
X
X
X
X
X
X
X
WRITE  
CE1  
ZZ  
ADSP ADSC ADV  
OE  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
WRITE Cycle, Continue Burst  
WRITE Cycle, Continue Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
WRITE Cycle, Suspend Burst  
WRITE Cycle, Suspend Burst  
X
L
H
X
X
H
X
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
Next  
Next  
Next  
Next  
Current  
Current  
Current  
Current  
Current  
Current  
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
X
X
L
H
L
H
X
X
Q
L
L
L
H
H
H
H
H
H
L-H  
L-H  
L-H  
D
D
Q
L
H
H
H
H
L
L-H three-state  
L-H  
L-H three-state  
L-H  
L-H  
Q
X
X
X
X
X
X
D
D
L
Partial Truth Table for Read/Write[2, 8]  
Function  
BWD  
BWC  
BWB  
BWA  
GW  
BWE  
Read  
Read  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
X
H
H
L
X
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Write Byte A – DQA  
Write Byte B – DQB  
Write Bytes B, A  
Write Byte C– DQC  
Write Bytes C, A  
Write Bytes C, B  
Write Bytes C, B, A  
Write Byte D– DQD  
Write Bytes D, A  
Write Bytes D, B  
Write Bytes D, B, A  
Write Bytes D, C  
Write Bytes D, C, A  
Write Bytes D, C, B  
Write All Bytes  
L
H
H
L
L
H
H
L
L
H
H
L
L
X
L
L
L
X
Write All Bytes  
X
Notes:  
8. Table only lists a partial listing of the byte write combinations. Any combination of BW  
is valid. Appropriate write will be done based on which byte write is active.  
[A:D]  
Document #: 38-05217 Rev. *C  
Page 7 of 17  
CY7C1339F  
Current into Outputs (LOW)......................................... 20 mA  
Maximum Ratings  
Static Discharge Voltage........................................... >2001V  
(Above which the useful life may be impaired. For user guide-  
(per MIL-STD-883, Method 3015)  
lines, not tested.)  
Latch-up Current..................................................... >200 mA  
Storage Temperature .................................–65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Ambient  
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V  
Range  
Temperature  
VDD  
VDDQ  
DC Voltage Applied to Outputs  
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V –5%  
in three-state....................................... –0.5V to VDDQ + 0.5V  
to VDD  
Industrial  
–40°C to +85°C  
DC Input Voltage....................................–0.5V to VDD + 0.5V  
[9, 10]  
Electrical Characteristics Over the Operating Range  
Parameter  
VDD  
VDDQ  
VOH  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Output HIGH Voltage  
Test Conditions  
Min.  
3.135  
2.375  
2.4  
Max.  
3.6  
VDD  
Unit  
V
V
V
V
V
V
V
V
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA  
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA  
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA  
DDQ = 2.5V, VDD = Min., IOL = 1.0 mA  
VDDQ = 3.3V  
DDQ = 2.5V  
2.0  
VOL  
VIH  
VIL  
IX  
Output LOW Voltage  
Input HIGH Voltage[9]  
Input LOW Voltage[9]  
0.4  
0.4  
VDD + 0.3V  
VDD + 0.3V  
0.8  
V
2.0  
1.7  
–0.3  
–0.3  
–5  
V
VDDQ = 3.3V  
VDDQ = 2.5V  
GND ≤ VI ≤ VDDQ  
V
V
µA  
0.7  
5
Input Load Current  
except ZZ and MODE  
Input Current of MODE Input = VSS  
Input = VDD  
–30  
–5  
µA  
µA  
µA  
µA  
µA  
5
Input Current of ZZ  
Input = VSS  
Input = VDD  
30  
5
IOZ  
IDD  
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled  
–5  
VDD Operating Supply VDD = Max., IOUT = 0 mA,  
4-ns cycle, 250 MHz  
4.4-ns cycle, 225 MHz  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
7.5-ns cycle, 133 MHz  
10-ns cycle, 100 MHz  
4-ns cycle, 250 MHz  
4.4-ns cycle, 225 MHz  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
7.5-ns cycle, 133 MHz  
10-ns cycle, 100 MHz  
All speeds  
325  
290  
265  
240  
225  
205  
120  
115  
110  
100  
90  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Current  
f = fMAX = 1/tCYC  
ISB1  
Automatic CE  
VDD = Max, Device Deselected,  
Power-down  
VIN ≥ VIH or VIN ≤ VIL  
Current—TTL Inputs  
f = fMAX = 1/tCYC  
80  
40  
ISB2  
Automatic CE  
Power-down  
VDD = Max, Device Deselected,  
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V,  
Current—CMOS Inputs f = 0  
Shaded area contains advanced information.  
Notes:  
9. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC) > -2V (Pulse width less than t  
/2).  
IH  
DD  
CYC  
IL  
CYC  
10. TPower-up: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V  
< V  
.
DD  
DD  
IH  
DD  
DDQ  
Document #: 38-05217 Rev. *C  
Page 8 of 17  
CY7C1339F  
Electrical Characteristics Over the Operating Range (continued)[9, 10]  
Parameter  
ISB3  
Description  
Automatic CE  
Power-down  
Test Conditions  
VDD = Max, Device Deselected, or 4-ns cycle, 250 MHz  
Min.  
Max.  
105  
100  
95  
85  
75  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V  
4.4-ns cycle, 225 MHz  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
7.5-ns cycle, 133 MHz  
10-ns cycle, 100 MHz  
All Speeds  
Current—CMOS Inputs f = fMAX = 1/tCYC  
65  
45  
ISB4  
Automatic CE  
V
DD = Max, Device Deselected,  
Power-down  
V
IN ≥ VIH or VIN ≤ VIL, f = 0  
Current—TTL Inputs  
Shaded areas contain advance information.  
Thermal Resistance[11]  
TQFP  
BGA  
Parameter  
Description  
Test Conditions  
Package  
Package  
Unit  
ΘJA  
Thermal Resistance  
Test conditions follow standard test  
41.83  
47.63  
°C/W  
(Junction to Ambient)  
methods and procedures for  
measuring thermal impedance, per  
EIA / JESD51.  
ΘJC  
Thermal Resistance  
(Junction to Case)  
9.99  
11.71  
°C/W  
Capacitance[11]  
TQFP  
BGA  
Parameter  
Description  
Test Conditions  
Package Package Unit  
CIN  
CCLK  
CI/O  
Input Capacitance  
Clock Input Capacitance  
Input/Output Capacitance  
TA = 25°C, f = 1 MHz,  
5
5
5
5
5
7
pF  
pF  
pF  
V
DD = 3.3V.  
DDQ = 3.3V  
V
AC Test Loads and Waveforms  
3.3V I/O Test Load  
R = 317Ω  
3.3V  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
OUTPUT  
90%  
10%  
Z = 50Ω  
0
10%  
R = 50Ω  
L
5 pF  
R = 351Ω  
≤ 1ns  
≤ 1ns  
INCLUDING  
JIG AND  
SCOPE  
V = 1.5V  
T
(c)  
(a)  
(b)  
2.5V I/O Test Load  
OUTPUT  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R =1538Ω  
≤ 1ns  
≤ 1ns  
V = 1.25V  
T
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
Note:  
11. Tested initially and after any design or process change that may affect these parameters  
Document #: 38-05217 Rev. *C  
Page 9 of 17  
CY7C1339F  
Switching Characteristics Over the Operating Range[16, 17]  
250 MHz 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz  
Parameter  
tPOWER  
Clock  
tCYC  
tCH  
tCL  
Description  
Min. Max Min. Max Min. Max Min. Max Min. Max Min. Max Unit  
VDD(Typical) to the first Access[12]  
1
1
1
1
1
1
ms  
Clock Cycle Time  
Clock HIGH  
Clock LOW  
4.0  
1.7  
1.7  
4.4  
2.0  
2.0  
5.0  
2.0  
2.0  
6.0  
2.5  
2.5  
7.5  
3.0  
3.0  
10  
3.5  
3.5  
ns  
ns  
ns  
Output Times  
tCO  
tDOH  
tCLZ  
tCHZ  
tOEV  
tOELZ  
tOEHZ  
Data Output Valid After CLK Rise  
2.6  
2.6  
2.8  
3.5  
4.0  
4.5 ns  
ns  
Data Output Hold After CLK Rise  
1.0  
0
1.0  
0
1.0  
0
2.0  
0
2.0  
0
2.0  
0
Clock to Low-Z[13, 14, 15]  
ns  
Clock to High-Z[13, 14, 15]  
2.6  
2.6  
2.6  
2.6  
2.8  
2.8  
3.5  
3.5  
4.0  
4.5  
4.5 ns  
4.5 ns  
ns  
OE LOW to Output Valid  
LOW to Output Low-Z[13, 14, 15]  
OE  
0
0
0
0
0
0
OE HIGH to Output High-Z[13, 14, 15]  
2.6  
2.6  
2.8  
3.5  
4.0  
4.5 ns  
Set-up Times  
tAS  
tADS  
Address Set-up Before CLK Rise  
0.8  
0.8  
1.2  
1.2  
1.2  
1.2  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
,
ADSC ADSP Set-up Before CLK  
Rise  
tADVS  
tWES  
0.8  
1.2  
1.2  
1.2  
1.2  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ADV Set-up Before CLK Rise  
Set-up Before 0.8  
GW, BWE, BW[A:D]  
CLK Rise  
tDS  
tCES  
Data Input Set-up Before CLK Rise 0.8  
1.2  
1.2  
1.2  
1.2  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
Chip Enable Set-Up Before CLK  
0.8  
Rise  
Hold Times  
tAH  
tADH  
tADVH  
tWEH  
Address Hold After CLK Rise  
0.4  
0.4  
0.4  
0.4  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
,
Hold After CLK Rise  
ADSP ADSC  
ADV Hold After CLK Rise  
,
,
GW BWE BW[A:D] Hold After CLK  
Rise  
tDH  
tCEH  
Data Input Hold After CLK Rise  
Chip Enable Hold After CLK Rise  
0.4  
0.4  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
Shaded areas contain advance information.  
Notes:  
12. This part has a voltage regulator internally; t  
can be initiated.  
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation  
DD  
POWER  
13. t  
, t  
,t  
, and t  
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
CHZ CLZ OELZ  
OEHZ  
14. At any given voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
OEHZ  
OELZ  
CHZ  
CLZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z prior to Low-Z under the same system conditions  
15. This parameter is sampled and not 100% tested.  
16. Timing reference level is 1.5V when V  
= 3.3V and is 1.25V when V  
= 2.5V.  
DDQ  
DDQ  
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
Document #: 38-05217 Rev. *C  
Page 10 of 17  
CY7C1339F  
Switching Waveforms  
Read Cycle Timing[18]  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
ADH  
ADS  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Burst continued with  
new base address  
t
t
WEH  
WES  
GW, BWE,  
BW[A:D]  
Deselect  
cycle  
t
t
CEH  
CES  
CE  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV  
suspends  
burst.  
t
t
OEV  
CO  
t
t
OEHZ  
t
OELZ  
t
CHZ  
DOH  
t
CLZ  
t
Q(A2)  
Q(A2 + 1)  
Q(A2 + 2)  
Q(A2 + 3)  
Q(A2)  
Q(A2 + 1)  
Q(A1)  
Data Out (Q)  
High-Z  
CO  
Burst wraps around  
to its initial state  
Single READ  
BURST READ  
DON’T CARE  
UNDEFINED  
Notes:  
18. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
19.  
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW  
LOW.  
[A:D]  
Document #: 38-05217 Rev. *C  
Page 11 of 17  
CY7C1339F  
Switching Waveforms (continued)  
Write Cycle Timing[18, 19]  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC extends burst  
t
t
ADH  
ADS  
t
t
ADH  
ADS  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Byte write signals are  
ignored for first cycle when  
ADSP initiates burst  
t
t
WEH  
WES  
BWE,  
BW[A :D]  
t
t
WEH  
WES  
GW  
CE  
t
t
CEH  
CES  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV suspends burst  
t
t
DH  
DS  
Data In (D)  
D(A2)  
D(A2 + 1)  
D(A2 + 1)  
D(A2 + 2)  
D(A2 + 3)  
D(A3)  
D(A3 + 1)  
D(A3 + 2)  
D(A1)  
High-Z  
t
OEHZ  
Data Out (Q)  
BURST READ  
Single WRITE  
BURST WRITE  
Extended BURST WRITE  
DON’T CARE  
UNDEFINED  
Document #: 38-05217 Rev. *C  
Page 12 of 17  
CY7C1339F  
Switching Waveforms (continued)  
Read/Write Cycle Timing[18, 20, 21]  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
A4  
A5  
A6  
ADDRESS  
t
t
WEH  
WES  
BWE,  
BW[A:D]  
t
t
CEH  
CES  
CE  
ADV  
OE  
t
t
DH  
t
CO  
DS  
t
OELZ  
Data In (D)  
High-Z  
High-Z  
D(A3)  
D(A5)  
D(A6)  
t
t
OEHZ  
CLZ  
Data Out (Q)  
Q(A1)  
Q(A2)  
Q(A4)  
Q(A4+1)  
Q(A4+2)  
Q(A4+3)  
Back-to-Back READs  
Single WRITE  
BURST READ  
Back-to-Back  
WRITEs  
DON’T CARE  
UNDEFINED  
Note:  
20.  
21.  
.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by  
GW is HIGH.  
ADSP or ADSC  
Document #: 38-05217 Rev. *C  
Page 13 of 17  
CY7C1339F  
Switching Waveforms (continued)  
ZZ Mode Timing [22, 23]  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(MHz)  
Ordering Code  
Package Type  
250  
CY7C1339F-250AC  
CY7C1339F-250BGC  
CY7C1339F-250AI  
CY7C1339F-250BGI  
CY7C1339F-225AC  
CY7C1339F-225BGC  
CY7C1339F-225AI  
CY7C1339F-225BGI  
CY7C1339F-200AC  
CY7C1339F-200BGC  
CY7C1339F-200AI  
CY7C1339F-200BGI  
CY7C1339F-166AC  
CY7C1339F-166BGC  
CY7C1339F-166AI  
CY7C1339F-166BGI  
CY7C1339F-133AC  
CY7C1339F-133BGC  
CY7C1339F-133AI  
CY7C1339F-133BGI  
A101  
BG119  
A101  
BG119  
A101  
BG119  
A101  
BG119  
A101  
BG119  
A101  
BG119  
A101  
BG119  
A101  
BG119  
A101  
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial  
119-ball BGA (14 x 22 x 2.4mm)  
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)  
119-ball BGA (14 x 22 x 2.4mm)  
Industrial  
225  
200  
166  
133  
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial  
119-ball BGA(14 x 22 x 2.4mm)  
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)  
119-ball BGA(14 x 22 x 2.4mm)  
Industrial  
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial  
119-ball BGA(14 x 22 x 2.4mm)  
100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm)  
119-ball BGA(14 x 22 x 2.4mm)  
100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm)  
119-ball BGA(14 x 22 x 2.4mm)  
100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm)  
119-ball BGA(14 x 22 x 2.4mm)  
Industrial  
Commercial  
Industrial  
100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm)  
119-ball BGA(14 x 22 x 2.4mm)  
100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm)  
119-ball BGA(14 x 22 x 2.4mm)  
Commercial  
Industrial  
BG119  
A101  
BG119  
Notes:  
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.  
23. DQs are in high-Z when exiting ZZ sleep mode  
Document #: 38-05217 Rev. *C  
Page 14 of 17  
CY7C1339F  
Ordering Information (continued)  
Speed  
Package  
Name  
A101  
BG119  
A101  
Operating  
Range  
Commercial  
(MHz)  
Ordering Code  
CY7C1339F-100AC  
CY7C1339F-100BGC  
CY7C1339F-100AI  
CY7C1339F-100BGI  
Package Type  
100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm)  
119-ball BGA(14 x 22 x 2.4mm)  
100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm)  
119-ball BGA(14 x 22 x 2.4mm)  
100  
Industrial  
BG119  
Shaded areas contain advanced information.  
Please contact your local Cypress sales representative for availability of these parts.  
Package Diagrams  
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101  
51-85050-*A  
Document #: 38-05217 Rev. *C  
Page 15 of 17  
CY7C1339F  
Package Diagrams (continued)  
51-85115-*B  
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark  
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.  
Document #: 38-05217 Rev. *C  
Page 16 of 17  
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CY7C1339F  
Document History Page  
Document Title: CY7C1339F 4-Mbit (128K x 32) Pipelined Sync SRAM  
Document Number: 38-05217  
Orig. of  
REV.  
**  
*A  
*B  
*C  
ECN NO. Issue Date Change  
Description of Change  
119284  
123850  
200660  
213342  
01/06/03  
01/18/03  
See ECN  
See ECN  
HGK  
AJH  
REF  
VBL  
New Data Sheet  
Added power-up requirements to AC test loads and waveforms information  
Final Data Sheet  
Update Ordering Info section: unshade active parts. -133AI & BGI  
Document #: 38-05217 Rev. *C  
Page 17 of 17  

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