CY7C1339G-200AXCT [CYPRESS]
Cache SRAM, 128KX32, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100;型号: | CY7C1339G-200AXCT |
厂家: | CYPRESS |
描述: | Cache SRAM, 128KX32, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100 静态存储器 |
文件: | 总17页 (文件大小:340K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C1339G
PRELIMINARY
4-Mbit (128K x 32) Pipelined Sync SRAM
Features
Functional Description[1]
• Registered inputs and outputs for pipelined operation
• 128K × 32 common I/O architecture
• 3.3V core power supply
The CY7C1339G SRAM integrates 131,072 x 32 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
(
), depth-expansion Chip Enables (CE and
), Burst
CE3
CE1
2
— 2.6 ns (for 250-MHz device)
Control inputs (
,
,
and
ADSC ADSP
), Write Enables
). Asynchronous
GW
ADV
), and Global Write (
BWE
(
, and
BW[A:D]
— 2.8 ns (for 200-MHz device)
inputs include the Output Enable ( ) and the ZZ pin.
OE
— 3.5 ns (for 166-MHz device)
Addresses and chip enables are registered at rising edge of
— 4.0 ns (for 133-MHz device)
clock when either Address Strobe Processor (
) or
ADSP
Address Strobe Controller (
burst addresses can be internally generated as controlled by
the Advance pin ( ).
) are active. Subsequent
ADSC
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
ADV
Pentium® interleaved or linear burst sequences
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
controlled by the byte write control inputs.
when active
GW
• Lead-Free 100-pin TQFP and 119-ball BGA packages
• “ZZ” Sleep Mode Option
causes all bytes to be written.
LOW
The CY7C1339G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0, A1,
A
ADDRESS
REGISTER
2
A
[1:0]
Q1
MODE
ADV
CLK
BURST
COUNTER
CLR AND Q0
LOGIC
ADSC
ADSP
DQ
BYTE
W RITE REGISTER
D
DQ
BYTE
W RITE DRIVER
D
BW
D
DQ
C
DQ
C
BYTE
W RITE DRIVER
BYTE
W RITE REGISTER
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
MEMORY
ARRAY
SENSE
AMPS
D Q s
DQ
B
E
DQ
B
BYTE
W RITE DRIVER
BYTE
W RITE REGISTER
BW
BW
B
DQ
A
DQ
A
BYTE
W RITE DRIVER
BYTE
W RITE REGISTER
A
BW E
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
1
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05520 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 10, 2004
PRELIMINARY
CY7C1339G
Selection Guide
250 MHz
200 MHz
2.8
166 MHz
3.5
133 MHz
Unit
ns
Maximum Access Time
2.6
325
40
4.0
225
40
Maximum Operating Current
Maximum CMOS Standby Current
265
240
mA
mA
40
40
Shaded area contains advanced information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configurations
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
NC
DQB
DQB
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
BYTE C
BYTE B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-pin TQFP
CY7C1339G
VDD
NC
VSS
NC
VDD
ZZ
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
BYTE D
BYTE A
Document #: 38-05520 Rev. *A
Page 2 of 17
PRELIMINARY
CY7C1339G
Pin Configurations (continued)
119-ball BGA
CY7C1339G (128K × 32)
1
2
A
3
A
A
A
4
5
A
A
A
6
A
7
A
VDDQ
NC
VDDQ
NC
ADSP
CE2
A
NC
A
B
C
ADSC
VDD
NC
NC
DQC
DQC
VDDQ
DQC
DQC
VDDQ
DQD
NC
VSS
VSS
VSS
BWc
VSS
NC
NC
CE1
OE
VSS
VSS
VSS
BWB
VSS
NC
NC
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
D
E
F
DQC
DQC
DQC
DQC
VDD
DQD
DQB
DQB
DQB
DQB
VDD
DQA
G
H
J
ADV
GW
VDD
CLK
K
VSS
VSS
L
M
N
DQD
VDDQ
DQD
DQD
DQD
DQD
BWD
VSS
VSS
NC
BWA
VSS
VSS
DQA
DQA
DQA
DQA
VDDQ
DQA
BWE
A1
P
R
T
DQD
NC
NC
A
VSS
MODE
A
A0
VDD
A
VSS
NC
A
NC
A
DQA
NC
NC
NC
NC
NC
NC
ZZ
VDDQ
NC
NC
NC
VDDQ
U
Pin Definitions
Name
I/O
Description
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
or is active LOW, and CE , CE , and CE are sampled active. A1, A0
A0, A1, A
Input-
Synchronous of the CLK if
ADSP ADSC
are fed to the two-bit counter.
1
2
3
.
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK
BWA,BWB
BWC,BWD
.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
GW
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
Input- Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
BWE
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1
CE2
Synchronous CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE
1 is sampled only
when a new external address is loaded.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device.CE
2 is sampled only when a new external address is
loaded.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE3 is sampled only when a new external address is
loaded.Not connected for BGA. Where referenced, CE3 is assumed active throughout this
document for BGA.
CE3
OE
Synchronous CE and CE to select/deselect the device.
1
2
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Document #: 38-05520 Rev. *A
Page 3 of 17
PRELIMINARY
CY7C1339G
Pin Definitions (continued)
Name
ADV
I/O
Description
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
Input-
Synchronous automatically increments the address in a burst cycle.
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
ADSP
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1, A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH.
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
ADSC
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1, A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
I/O-
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
DQs
clock rise of the read cycle. The direction
of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When
HIGH, DQs are placed in a tri-state condition.
VDD
VSS
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the core of the device.
Power supply for the I/O circuitry.
VDDQ
I/O Power
Supply
VSSQ
I/O Ground
Ground for the I/O circuitry.
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
NC
No Connects. Not internally connected to the die
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 2.6 ns
(250-MHz device).
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write
The CY7C1339G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state immedi-
ately.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
Document #: 38-05520 Rev. *A
Page 4 of 17
PRELIMINARY
CY7C1339G
address advancement logic while being delivered to the
Burst Sequences
memory array. The Write signals (GW, BWE, and BW[A:D]) and
ADV inputs are ignored during this first cycle.
The CY7C1339G provides a two-bit wraparound counter, fed
by A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BW[A:D]
signals. The CY7C1339G provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW[A:D]) input, will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
Because the CY7C1339G is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
the
“sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
Single Write Accesses Initiated by ADSC
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and
(4) the appropriate combination of the Write inputs (GW, BWE,
and BW[A:D]) are asserted active to conduct a Write to the
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Because the CY7C1339G is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Snooze mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
Unit
mA
ns
40
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ recovery time
ZZ < 0.2V
2tCYC
0
ns
ZZ active to snooze current
ZZ Inactive to exit snooze current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ns
Document #: 38-05520 Rev. *A
Page 5 of 17
PRELIMINARY
CY7C1339G
Truth Table [ 2, 3, 4, 5, 6, 7]
Operation
Add. Used
None
CE2
X
L
CLK
L-H
L-H
L-H
L-H
L-H
X
DQ
tri-state
tri-state
tri-state
tri-state
tri-state
tri-state
Q
CE3
X
X
H
X
H
X
L
WRITE
CE1
ZZ
ADSP ADSC ADV
OE
X
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Snooze Mode, Power-down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
H
L
X
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
None
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
None
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
External
External
External
External
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
L
L
H
X
L
tri-state
D
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
tri-state
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
tri-state
Q
Next
L
Next
L
H
X
X
L
tri-state
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
tri-state
Q
H
X
X
tri-state
D
WRITE Cycle, Suspend Burst
L
D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW ) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
A
B
C
D
(BW , BW , BW , BW ), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the
signal.
is asynchronous and is not sampled with the clock.
OE
OE
5. CE , CE , and CE are available only in the TQFP package. BGA package has only 2 chip selects CE and CE .
1
2
3
1
2
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A: D]
after the
or with the assertion of
. As a result,
ADSC
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state.
is a
OE
OE
ADSP
don't care for the remainder of the write cycle
7.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when
is
OE
OE
.
is active (LOW)
inactive or when the device is deselected, and all data bits behave as output when
OE
Document #: 38-05520 Rev. *A
Page 6 of 17
PRELIMINARY
CY7C1339G
Partial Truth Table for Read/Write [2, 8]
Function
Read
BWD
BWC
BWB
BWA
GW
BWE
H
H
X
X
X
X
Read
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
L
H
L
Write Byte A – DQA
Write Byte B – DQB
Write Bytes B, A
Write Byte C– DQC
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D– DQD
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
H
L
L
H
H
L
H
L
L
L
H
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
H
L
L
L
L
H
H
L
H
L
L
L
L
L
H
L
L
L
L
Write All Bytes
X
X
X
X
Note:
8.Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05520 Rev. *A
Page 7 of 17
PRELIMINARY
CY7C1339G
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Range
Temperature
VDD
VDDQ
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to VDDQ + 0.5V
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V –5%
to VDD
Industrial
–40°C to +85°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
[9, 10]
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Test Conditions
Min.
3.135
2.375
2.4
Max.
3.6
Unit
V
VDDQ
VDD
V
VOH
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
V
2.0
V
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH Voltage[9]
Input LOW Voltage[9]
0.4
0.4
V
V
DDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
DDQ = 2.5V
V
2.0
1.7
VDD + 0.3V
VDD + 0.3V
0.8
V
V
V
VDDQ = 3.3V
–0.3
–0.3
–5
V
VDDQ = 2.5V
0.7
V
Input Load Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
5
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
µA
30
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
µA
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
All speeds
325
265
240
225
120
110
100
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
ISB2
Automatic CE
Power-down
Current—CMOS Inputs f = 0
V
DD = Max, Device Deselected,
40
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
ISB3
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX = 1/tCYC
V
DD = Max, Device Deselected, or 4-ns cycle, 250 MHz
105
95
mA
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
All Speeds
85
75
ISB4
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
45
Document #: 38-05520 Rev. *A
Page 8 of 17
PRELIMINARY
CY7C1339G
Electrical Characteristics Over the Operating Range (continued)[9, 10]
Parameter
Description
Test Conditions
Min.
Max.
Unit
Shaded area contains advanced information.
Notes:
9. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > -2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
10. TPower-up: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
Thermal Resistance[11]
TQFP
Package
BGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA / JESD51.
TBD
TBD
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
TBD
TBD
°C/W
Capacitance[11]
TQFP
BGA
Parameter
Description
Test Conditions
Package Package Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
5
5
5
5
5
7
pF
pF
pF
V
DD = 3.3V.
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
VDDQ = 3.3V
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
INCLUDING
JIG AND
SCOPE
V = 1.5V
T
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R =1538Ω
≤ 1ns
≤ 1ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
11. Tested initially and after any design or process change that may affect these parameters
Document #: 38-05520 Rev. *A
Page 9 of 17
PRELIMINARY
CY7C1339G
Switching Characteristics Over the Operating Range[12, 13, 14, 15, 16, 17]
250 MHz
200 MHz
166 MHz
133 MHz
Parameter
tPOWER
Clock
tCYC
Description
VDD(Typical) to the first Access[12]
Min. Max Min. Max Min. Max Min. Max Unit
1
1
1
1
ms
Clock Cycle Time
Clock HIGH
4.0
1.7
1.7
5.0
2.0
2.0
6.0
2.5
2.5
7.5
3.0
3.0
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCO
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[13, 14, 15]
2.6
2.8
3.5
4.0
ns
ns
ns
ns
ns
ns
ns
tDOH
1.0
0
1.0
0
1.5
0
1.5
0
tCLZ
tCHZ
Clock to High-Z[13, 14, 15]
2.6
2.6
2.8
2.8
3.5
3.5
4.0
4.0
tOEV
OE LOW to Output Valid
LOW to Output Low-Z[13, 14, 15]
OE HIGH to Output High-Z[13, 14, 15]
tOELZ
tOEHZ
Set-up Times
tAS
0
0
0
0
OE
2.6
2.8
3.5
4.0
Address Set-up Before CLK Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tADS
,
ADSC ADSP Set-up Before CLK Rise
tADVS
tWES
ADV Set-up Before CLK Rise
Set-up Before CLK Rise
GW, BWE, BWX
tDS
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
tCES
Hold Times
tAH
Address Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
,
Hold After CLK Rise
ADSP ADSC
tADVH
tWEH
ADV Hold After CLK Rise
,
,
GW BWE BWX Hold After CLK Rise
Data Input Hold After CLK Rise
tDH
tCEH
Chip Enable Hold After CLK Rise
Shaded areas contain advance information.
Notes:
12. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a read or write
DD
POWER
operation can be initiated.
13. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state
CHZ CLZ OELZ
OEHZ
voltage.
14. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the
CLZ
OEHZ
OELZ
CHZ
same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is
designed to achieve High-Z prior to Low-Z under the same system conditions
15. This parameter is sampled and not 100% tested.
16. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05520 Rev. *A
Page 10 of 17
PRELIMINARY
CY7C1339G
Switching Waveforms
Read Cycle Timing[18]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BW[A:D]
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
OELZ
t
CHZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Notes:
18. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
19.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW.
[A:D]
Document #: 38-05520 Rev. *A
Page 11 of 17
PRELIMINARY
CY7C1339G
Switching Waveforms (continued)
Write Cycle Timing[18, 19]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A :D]
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Document #: 38-05520 Rev. *A
Page 12 of 17
PRELIMINARY
CY7C1339G
Switching Waveforms (continued)
Read/Write Cycle Timing[18, 20, 21]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE,
BW[A:D]
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Note:
20.
21.
.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
GW is HIGH.
ADSP or ADSC
Document #: 38-05520 Rev. *A
Page 13 of 17
PRELIMINARY
CY7C1339G
Switching Waveforms (continued)
ZZ Mode Timing [22, 23]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
250
CY7C1339G-250AXC
CY7C1339G-250BGC
CY7C1339G-250BGXC
CY7C1339G-250AXI
CY7C1339G-250BGI
CY7C1339G-250BGXI
CY7C1339G-200AXC
CY7C1339G-200BGC
CY7C1339G-200BGXC
CY7C1339G-200AXI
CY7C1339G-200BGI
CY7C1339G-200BGXI
CY7C1339G-166AXC
CY7C1339G-166BGC
CY7C1339G-166BGXC
CY7C1339G-166AXI
CY7C1339G-166BGI
CY7C1339G-166BGXI
CY7C1339G-133AXC
CY7C1339G-133BGC
CY7C1339G-133BGXC
CY7C1339G-133AXI
CY7C1339G-133BGI
CY7C1339G-133BGXI
A101
BG119
BG119
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
119-ball BGA (14 x 22 x 2.4mm)
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-ball BGA (14 x 22 x 2.4mm)
Industrial
BG119
BG119
A101
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
200
166
133
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
119-ball BGA (14 x 22 x 2.4mm)
BG119
BG119
A101
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-ball BGA (14 x 22 x 2.4mm)
Industrial
BG119
BG119
A101
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
119-ball BGA (14 x 22 x 2.4mm)
BG119
BG119
A101
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-ball BGA (14 x 22 x 2.4mm)
Industrial
BG119
BG119
A101
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
119-ball BGA (14 x 22 x 2.4mm)
BG119
BG119
A101
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-ball BGA (14 x 22 x 2.4mm)
Industrial
BG119
BG119
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
Shaded areas contain advanced information. Please contact your local Cypress sales representative for availability of these parts.
Notes:
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
23. DQs are in high-Z when exiting ZZ sleep mode
Document #: 38-05520 Rev. *A
Page 14 of 17
PRELIMINARY
CY7C1339G
Ordering Information (continued)
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
Notes:
24. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
25. DQs are in high-Z when exiting ZZ sleep mode
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05520 Rev. *A
Page 15 of 17
PRELIMINARY
CY7C1339G
Package Diagrams (continued)
51-85115-*B
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05520 Rev. *A
Page 16 of 17
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY7C1339G
Document History Page
Document Title: CY7C1339G 4-Mbit (128K x 32) Pipelined Sync SRAM
Document Number: 38-05520
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
224368
288909
See ECN
See ECN
RKF
VBL
New data sheet
*A
In Ordering Info section, Changed TQFP to PB-free TQFP
Added PB-free BG package
Document #: 38-05520 Rev. *A
Page 17 of 17
相关型号:
CY7C1339G-250AXCT
Cache SRAM, 128KX32, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
CYPRESS
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