CY7C1345F-133AI [CYPRESS]
4-Mb (128K x 36) Flow-Through Sync SRAM; 4 -MB ( 128K ×36 )流通型同步SRAM型号: | CY7C1345F-133AI |
厂家: | CYPRESS |
描述: | 4-Mb (128K x 36) Flow-Through Sync SRAM |
文件: | 总17页 (文件大小:422K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C1345F
4-Mb (128K x 36) Flow-Through Sync SRAM
Features
Functional Description[1]
The CY7C1345F is a 131,072 x 36 synchronous cache RAM
designed to interface with high-speed microprocessors with
• 128K × 36 common I/O
• 3.3V –5% and +10% core power supply (VDD
)
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
• 2.5V or 3.3V I/O supply (VDDQ
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
— 8.0 ns (100-MHz version)
— 11.0 ns (66-MHz version)
)
(
), depth-expansion Chip Enables (CE and
), Burst
CE3
CE1
2
Control inputs (
,
,
), Write Enables
). Asynchronous
GW
and
ADV
ADSC ADSP
(
,
and
), and Global Write (
BW[A:D]
BWE
• Provide high-performance 2-1-1-1 access rate
(
)
and the ZZ pin
.
nputs include the Output Enable
OE
i
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
The CY7C1345F allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs.
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP and 119-ball
Addresses and chip enables are registered at rising edge of
BGA packages
• “ZZ” Sleep Mode option
clock when either Address Strobe Processor (
) or
ADSP
Address Strobe Controller (
) are active. Subsequent
ADSC
burst addresses can be internally generated as controlled by
the Advance pin ( ).
ADV
The CY7C1345F operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
ADDRESS
REGISTER
A0, A1, A
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQPD
DQ
BYTE
WRITE REGISTER
D, DQPD
BW
D
DQ
BYTE
WRITE REGISTER
C, DQPC
DQ
BYTE
WRITE REGISTER
C, DQPC
BW
C
OUTPUT
BUFFERS
DQs
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQPB
B
C
DQ
BYTE
WRITE REGISTER
B, DQPB
BW
B
DQPD
DQ
BYTE
WRITE REGISTER
A, DQPA
DQ
A, DQPA
BW
A
BYTE
BWE
WRITE REGISTER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05214 Rev. *C
Revised September 24,
CY7C1345F
Selection Guide
133 MHz
6.5
117 MHz
7.5
100 MHz
8.0
66 MHz
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
11.0
195
40
225
220
205
40
40
40
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configurations
100-Pin TQFP
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
1
2
3
4
5
6
7
8
DQPB
DQB
DQB
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
BYTE C
BYTE B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1345F
VDD
NC
VSS
NC
VDD
ZZ
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
BYTE D
BYTE A
Document #: 38-05214 Rev. *C
Page 2 of 17
CY7C1345F
Pin Configurations (continued)
119-Ball BGA
2
A
1
3
A
4
5
A
6
A
7
VDDQ
VDDQ
A
B
C
D
E
F
G
H
J
ADSP
NC
NC
CE2
A
A
A
A
A
NC
NC
ADSC
VDD
NC
CE1
OE
ADV
GW
VDD
CLK
NC
BWE
A1
CE3
A
DQC
DQC
VDDQ
DQC
DQC
VDDQ
DQD
DQD
VDDQ
DQD
DQPC
DQC
DQC
DQC
DQC
VDD
DQD
DQD
DQD
DQD
VSS
VSS
VSS
BWC
VSS
NC
VSS
VSS
VSS
BWB
VSS
NC
DQPB
DQB
DQB
DQB
DQB
VDD
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
K
VSS
VSS
DQA
L
M
N
BWD
VSS
VSS
BWA
VSS
VSS
DQA
DQA
DQA
P
R
T
DQD
NC
NC
DQPD
A
NC
VSS
MODE
A
A0
VDD
A
VSS
NC
A
DQPA
A
NC
DQA
NC
ZZ
VDDQ
NC
NC
NC
NC
NC
VDDQ
U
Pin Descriptions
Name
A0, A1, A
TQFP
BGA
P4,N4,A2,A3,
I/O
Input-
Description
37,36,32,
Address Inputs used to select one of the 128K address
33,34,35,
A5,A6,B3,B5, Synchronous locations. Sampled at the rising edge of the CLK if ADSP or ADSC
44,45,46, C2,C3,C5,C6,
is active LOW, and CE1,CE2, andCE3 are sampled active. A[1:0] feed
the 2-bit counter.
47,48,49,
50,81,82,
99,100
R2,R6,T3,T4,
T5
BWA,BWB
BWC,BWD
GW
93,94,
L5,G5,
G3,L3
H4
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to
95,96
Synchronous conduct byte writes to the SRAM. Sampled on the rising edge of CLK.
88
Input-
Global Write Enable Input, active LOW. When asserted LOW on
Synchronous the rising edge of CLK, a global write is conducted (ALL bytes are
written, regardless of the values on BW[A:D] and BWE).
87
89
M4
K4
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge
BWE
CLK
Synchronous of CLK. This signal must be asserted LOW to conduct a byte write.
Input-Clock Clock Input. Used to capture all synchronous inputs to the device.
Also used to increment the burst counter when ADV is asserted
LOW, during a burst operation.
98
97
92
E4
B2
B6
Input-
Synchronous CLK. Used in conjunction with CE2 and CE3 to select/deselect the
device. ADSP is ignored
Chip Enable 1 Input, active LOW. Sampled on the rising edge of
CE1
CE2
if CE1 is HIGH.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of
Synchronous CLK. Used in conjunction with CE1 and CE3 to select/deselect the
device.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.
CE3
Synchronous Used in conjunction with CE1 and CE2 to select/deselect the device.
Document #: 38-05214 Rev. *C
Page 3 of 17
CY7C1345F
Pin Descriptions (continued)
Name
TQFP
BGA
I/O
Description
86
F4
Input-
Output Enable, asynchronous input, active LOW. Controls the
OE
Asynchronous direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a read cycle when
emerging from a deselected state.
83
84
G4
A4
Input-
Advance Input signal, sampled on the rising edge of CLK. When
ADV
Synchronous asserted, it automatically increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of
ADSP
Synchronous CLK, active LOW. When asserted LOW, addresses presented to the
device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized. ASDP is ignored when
HIGH
CE1 is deasserted
85
64
B4
T7
Input-
Address Strobe from Controller, sampled on the rising edge of
ADSC
ZZ
Synchronous CLK, active LOW. When asserted LOW, addresses presented to the
device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP
only ADSP is recognized
ZZ “sleep” Input, active HIGH. When asserted HIGH places the
and ADSC are both asserted,
.
Input-
Asynchronous device in a non-time-critical “sleep” condition with data integrity
preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
DQs
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,
7,8,9,12,
13,18,19,
22,23,24,
25,28,29,
K6,K7,L6,
L7,M6,N6,
N7,P7,D7,
E6,E7,F6,
G6,G7,H6,
H7,D1,E1,
E2,F2,G1,
G2,H1,H2,
K1,K2,L1,
L2,M2,N1
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip
DQPA,
DQPB
DQPC,
DQPD
Synchronous data register that is triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory location specified by
the addresses presented during the previous clock rise of the read
cycle. The direction of the pins is controlled by
. When
OE
is
OE
asserted LOW, the pins behave as outputs. When HIGH, DQs and
DQP[A:D] are placed in a three-state condition.
51,80,1,30 N2,P1,P6,D6,
D2,P2
VDD
VSS
15,41,
65, 91
C4,J2,J4,
R4,J6
D3,D5,E3,E5,
F3,F5,H3,H5,
K3,K5,M3,M5,
N3,N5,P3,P5
Power Supply Power supply inputs to the core of the device.
17,40,
Ground
Ground for the core of the device.
67,90
VDDQ
4,11,20,
27,54,61,
70,77
A1,A7,F1,F7,
J1,J7,M1,M7,
U1,U7
I/O Power Power supply for the I/O circuitry.
Supply
VSSQ
5,10,21,
26,55,60,
71,76
–
I/O Ground Ground for the I/O circuitry.
MODE
31
R3
Input-
Static
Selects Burst Order. When tied to GND selects linear burst
sequence. When tied to VDD or left floating selects interleaved burst
sequence. This is a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.
NC
14,16,38,
39,42,43,
66,
B1,B7,C1,C7,
D4,J3,J5,L4,
R1,R5,R7,T1,
T2,T6,U2,U3,
U4,U5,U6
No Connects. Not Internally connected to the die.
Document #: 38-05214 Rev. *C
Page 4 of 17
CY7C1345F
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tC0) is 6.5 ns (133-MHz device).
The CY7C1345F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium® and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
HIGH, and (4) the write input signals (GW, BWE, and BW[A:D]
)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[D:A] will be
written into the specified address location. Byte writes are
allowed. During byte writes, BWA controls DQA, BWB controls
DQB, BWC controls DQC, and BWD controls DQD. All I/Os are
three-stated when a write is detected, even a byte write. Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be three-stated prior to
the presentation of data to DQs. As a safety precaution, the
data lines are three-stated once a write cycle is detected,
regardless
of the state of OE.
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Burst Sequences
The CY7C1345F provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
leaved burst sequence.
Byte write operations are qualified with the Byte Write Enable
[A:D]
(BWE) and Byte Write Select (BW
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
Interleaved Burst Address Table (MODE =
Floating or VDD
)
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
rise. ADSP is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
First
Address
A1,A0
Second
Address
A1,A0
Third
Address
A1,A0
Fourth
Address
A1,A0
This access is initiated when the following conditions are
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
satisfied at clock rise: (1)
CE1, CE2, CE3 are all asserted
ADSP is asserted LOW. The addresses
active, and (2)
presented are loaded into the address register and the burst
inputs (
GW, BWE, and BW[A:D] )are ignored during this first
clock cycle. If the write inputs are asserted active ( see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise,the appropriate data will be latched
and written into the device.Byte writes are allowed. During
Sleep Mode
B, BWC
BW controls DQ and BW controls DQ
byte writes,
A
controls DQ , and BW controAls DQ .
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
D AllBI/Os are three-stated
during a byCte write.SiDnce this is a common I/O device, the
asynchronous
OE input signal must be deasserted and the
I/Os must be three-stated prior to the presentation of data to
DQs. As a safety precaution, the data lines are three-stated
once a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
the “sleep” mode. CEs, ADSP, and ADSC must remain
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Document #: 38-05214 Rev. *C
Page 5 of 17
CY7C1345F
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
Description
Snooze mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
Min.
Max.
40
2tCYC
Unit
mA
ns
tZZREC
tZZI
tRZZI
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
2tCYC
0
ns
ns
ns
2tCYC
Truth Table[2, 3, 4, 5, 6]
Address
Used
Cycle Description
CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle,
None
None
None
None
None
H
L
L
L
X
X
X
X
H
X
X
L
L
L
L
L
X
L
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H three-state
L-H three-state
L-H three-state
L-H three-state
L-H three-state
Power-down
Deselected Cycle,
Power-down
L
L
Deselected Cycle,
X
L
L
Power-down
Deselected Cycle,
Power-down
H
H
Deselected Cycle,
X
Power-down
Snooze Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
External
External
External
External
External
Next
Next
Next
Next
Next
X
L
L
L
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
L
X
X
X
L
H
H
H
H
H
H
L
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
X
L-H
three-state
Q
L-H three-state
L-H
L-H
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
D
Q
L
L
L-H three-state
L-H
L-H three-state
L-H
L-H three-state
L-H
L-H
L-H
L-H three-state
L-H
L-H three-state
L-H
L-H
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
Q
Q
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
D
D
Write Cycle, Suspend Burst
L
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW ) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
A
B
C
D
(BW , BW , BW , BW ), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the
signal.
is asynchronous and is not sampled with the clock.
OE
OE
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A: D]
after the
or with the assertion of
. As a result,
must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state.
OE
is
ADSC
OE
ADSP
a don't care for the remainder of the write cycle.
6.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when
OE
is
OE
inactive or when the device is deselected, and all data bits behave as output when
is active (LOW).
OE
Document #: 38-05214 Rev. *C
Page 6 of 17
CY7C1345F
Partial Truth Table for Read/Write[2, 7]
Function
Read
Read
Write Byte (A, DQPA)
Write Byte (B, DQPB)
BWD
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BWC
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BWB
BWA
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
GW
H
BWE
H
X
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
Write Bytes (B, A, DQPA, DQPB)
Write Byte (C, DQPC)
Write Bytes (C, A, DQPC, DQPA)
Write Bytes (C, B, DQPC, DQPB)
Write Bytes (C, B, A, DQPC, DQPB, DQPA)
Write Byte (D, DQPD)
Write Bytes (D, A, DQPD, DQPA)
Write Bytes (D, B, DQPD, DQPA)
Write Bytes (D, B, A, DQPD, DQPB, DQPA)
Write Bytes (D, B, DQPD, DQPB)
Write Bytes (D, B, A, DQPD, DQPC, DQPA)
Write Bytes (D, C, A, DQPD, DQPB, DQPA)
Write All Bytes
L
H
H
L
L
H
H
L
L
H
H
L
L
X
Write All Bytes
X
Note:
7. Table only lists a partial listing of the byte write combinations. Any combination of BW
is valid. Appropriate write will be done based on which byte write is active.
[A:D]
Document #: 38-05214 Rev. *C
Page 7 of 17
CY7C1345F
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Range
Temperature]
VDD
VDDQ
DC Voltage Applied to Outputs
Commercial 0°C to +70°C 3.3V −5%/+10% 2.5V –5%
in three-state....................................... –0.5V to VDDQ + 0.5V
to VDD
Industrial
–40°C to +85°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
[8, 9]
Electrical Characteristics Over the Operating Range
CY7C1345F
Parameter
VDD
VDDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
Max.
3.6
VDD
Unit
V
V
V
V
3.135
2.375
2.4
VOH
Output HIGH Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
DDQ = 2.5V, VDD = Min., IOH = –1.0 mA
V
2.0
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[8]
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
0.4
0.4
V
V
V
V
V
V
µA
2.0 VDD + 0.3V
1.7 VDD + 0.3V
V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
–0.3
–0.3
−5
0.8
0.7
5
V
Input Load Current
GND ≤ VI ≤ VDDQ
(except ZZ and MODE)
Input Current of MODE
Input = VSS
Input = VDD
Input = VSS
–30
–5
µA
µA
µA
5
Input Current of ZZ
Input = VDD
GND ≤ VI ≤ VDD, Output Disabled
VDD = Max., VOUT = GND
30
5
µA
µA
µA
IOZ
IOS
IDD
Output Leakage Current
Output Short Circuit Current
VDD Operating Supply Current
–5
–300
225
220
205
195
90
85
80
60
40
VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
8.0-ns cycle, 117 MHz
10-ns cycle, 100 MHz
15-ns cycle, 66 MHz
7.5-ns cycle, 133 MHz
8.0-ns cycle, 117 MHz
10-ns cycle, 100 MHz
15-ns cycle, 66 MHz
All speeds
mA
mA
mA
mA
mA
mA
mA
mA
mA
f = fMAX= 1/tCYC
ISB1
Automatic CE Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
V
IN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
ISB2
Automatic CE Power-down
Current—CMOS Inputs
Max. VDD, Device Deselected,
V
IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
Shaded areas contain advance information.
Notes:
8. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > -2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
9. T
: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V
< V
DDQ DD.
Power-up
DD
IH
DD
Document #: 38-05214 Rev. *C
Page 8 of 17
CY7C1345F
Electrical Characteristics Over the Operating Range (continued) [8, 9]
CY7C1345F
Parameter
ISB3
Description
Test Conditions
Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz
IN ≥VDDQ – 0.3V or VIN ≤ 0.3V,
Min.
Max.
75
70
65
45
Unit
mA
mA
mA
mA
mA
Automatic CE Power-down
Current—CMOS Inputs
V
8.0-ns cycle, 117 MHz
10-ns cycle, 100 MHz
15-ns cycle, 66 MHz
f = fMAX, inputs switching
ISB4
Automatic CE Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, All speeds
IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
45
V
Thermal Resistance[10]
TQFP
BGA
Parameter
ΘJA
Description
Test Conditions
Package
Package
Unit
°C/W
Thermal Resistance
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA / JESD51.
41.83
47.63
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
9.99
11.71
°C/W
Capacitance[10]
TQFP
BGA
Parameter
Description
Input Capacitance
Clock Input Capacitance
Test Conditions
Package
Package
Unit
CIN
CCLK
CI/O
TA = 25°C, f = 1 MHz,
5
5
5
5
5
7
pF
pF
pF
V
DD = 3.3V.
VDDQ = 3.3V
Input/Output Capacitance
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDD
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDD
90%
10%
Z = 50Ω
0
10%
L
GND
≤ 1ns
5 pF
R =1538Ω
≤ 1ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
10. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05214 Rev. *C
Page 9 of 17
CY7C1345F
Switching Characteristics Over the Operating Range [15, 16]
133 MHz
117 MHz
100 MHz
66 MHz
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VDD(Typical) to the first Access[11]
1
1
1
1
ms
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
8.5
3.0
3.0
10
4.0
4.0
15
5.0
5.0
ns
ns
ns
Clock LOW
Output Times
tCDV
tDOH
tCLZ
tCHZ
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[12, 13, 14]
6.5
7.5
8.0
11.0
ns
ns
ns
ns
ns
ns
ns
2.0
0
2.0
0
2.0
0
2.0
0
Clock to High-Z[12, 13, 14]
3.5
3.5
3.5
3.5
3.5
3.5
5.0
6.0
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Setup Times
tAS
tADS
tADVS
tWES
OE LOW to Output Low-Z[12, 13, 14]
OE HIGH to Output High-Z[12, 13, 14]
0
0
0
0
3.5
3.5
3.5
6.0
Address Set-up Before CLK Rise
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
Set-up Before CLK Rise
GW, BWE, BW[A:D]
tDS
tCES
Data Input Set-up Before CLK Rise
Chip Enable Set-up
Hold Times
tAH
tADH
tWEH
tADVH
tDH
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
,
,
GW BWE BW[A:D] Hold After CLK Rise
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Shaded areas contain advance information.
Notes:
11. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation
DD
POWER
12. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
13. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
15. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05214 Rev. *C
Page 10 of 17
CY7C1345F
Timing Diagrams
Read Cycle Timing[17]
t
CYC
t
CLK
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
[A:D]
CE
Deselect Cycle
t
t
CES
CEH
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst.
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
17. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05214 Rev. *C
Page 11 of 17
CY7C1345F
Timing Diagrams (continued)
Write Cycle Timing[17, 18]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW
X
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
Note:
18.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW.
[A:D]
Document #: 38-05214 Rev. *C
Page 12 of 17
CY7C1345F
Timing Diagrams (continued)
Read/Write Timing[17, 19, 20]
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
Notes:
19.
20.
.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
GW is HIGH.
ADSP or ADSC
Document #: 38-05214 Rev. *C
Page 13 of 17
CY7C1345F
Timing Diagrams (continued)
ZZ Mode Timing[21, 22]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
Package
Name
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
Operating
Range
Commercial
(MHz)
Ordering Code
CY7C1345F-133AC
CY7C1345F-133BGC
CY7C1345F-133AI
CY7C1345F-133BGI
CY7C1345F-117AC
CY7C1345F-117BGC
CY7C1345F-117AI
CY7C1345F-117BGI
CY7C1345F-100AC
CY7C1345F-100BGC
CY7C1345F-100AI
CY7C1345F-100BGI
CY7C1345F-66AC
CY7C1345F-66BGC
CY7C1345F-66AI
Package Type
100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-Ball PBGA (14 x 22 x 2.4mm)
100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-Ball PBGA (14 x 22 x 2.4mm)
100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-Ball PBGA (14 x 22 x 2.4mm)
100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-Ball PBGA (14 x 22 x 2.4mm)
100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-Ball PBGA (14 x 22 x 2.4mm)
100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-Ball PBGA (14 x 22 x 2.4mm)
133
Industrial
117
100
66
Commercial
Industrial
Commercial
Industrial
100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-Ball PBGA (14 x 22 x 2.4mm)
100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-Ball PBGA (14 x 22 x 2.4mm)
Commercial
Industrial
CY7C1345F-66BGI
BG119
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Notes:
21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
22. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05214 Rev. *C
Page 14 of 17
CY7C1345F
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05214 Rev. *C
Page 15 of 17
CY7C1345F
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
may be the trademarks of their respective holders.
Document #: 38-05214 Rev. *C
Page 16 of 17
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1345F
Document History Page
Document Title: CY7C1345F 4-Mb (128K x 36) Flow-Through Sync SRAM
Document Number: 38-05214
Orig. of
REV.
**
*A
*B
*C
ECN NO. Issue Date Change
Description of Change
119831
123118
200663
280230
12/11/02
01/18/03
12/19/03
See ECN
HGK
RBI
REF
NJY
New data sheet
Added power-up requirements to AC test loads and waveforms information
Final data sheet
Corrected the timing diagrams for Write Cycle and Read/Write Cycle Timing
on page 12 and 13 of the data sheet
Corrected typo in the part number in the Document Title on page 17 from
CY7C1345B to CY7C1345F
Document #: 38-05214 Rev. *C
Page 17 of 17
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