CY7C1347F [CYPRESS]
4-Mbit (128K x 36) Pipelined Sync SRAM; 4兆位（ 128K ×36 ）流水线同步SRAM
| 型号： | CY7C1347F |
| 厂家： | 
CYPRESS |
| 描述： | 4-Mbit (128K x 36) Pipelined Sync SRAM |
| 文件： | 总19页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1347F
4-Mbit (128K x 36) Pipelined Sync SRAM
Features
Functional Description[1]
The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic.
• Fully registered inputs and outputs for pipelined oper-
ation
• 128K by 36 common I/O architecture
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V
level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 2.6 ns (250-MHz
device)
CY7C1347F supports either the interleaved burst sequence
used by the Intel Pentium processor or a linear burst sequence
used by processors such as the PowerPC®. The burst
sequence is selected through the MODE pin. Accesses can be
initiated by asserting either the Address Strobe from
Processor (ADSP) or the Address Strobe from Controller
(ADSC) at clock rise. Address advancement through the burst
sequence is controlled by the ADV input. A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-pin TQFP, 119-pin BGA and
165-pin fBGA packages
Byte write operations are qualified with the four Byte Write
Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write
circuitry.
• “ZZ” Sleep Mode option and Stop Clock option
• Available in Industrial and Commercial temperature
ranges
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
proper data during depth expansion, OE is masked during the
first clock of a read cycle when emerging from a deselected
state.
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND
CLR
Q0
LOGIC
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D ,DQPD
DQ
BYTE
WRITE DRIVER
D ,DQPD
BWD
DQC ,DQP
BYTE
WRITE DRIVER
C
DQC ,DQP
BYTE
WRITE REGISTER
C
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
MEMORY
ARRAY
DQ s
SENSE
AMPS
DQP
DQP
DQP
A
DQB ,DQP
BYTE
WRITE DRIVER
B
E
DQB ,DQP
BYTE
WRITE REGISTER
B
B
C
BW
B
DQPD
DQ
BYTE
WRITE DRIVER
A ,DQPA
DQ
BYTE
WRITE REGISTER
A ,DQPA
BWA
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05213 Rev. *D
Revised April 9, 2004
CY7C1347F
Selection Guide
-250
2.6
-225
2.6
-200
2.8
-166
3.5
-133
4.0
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
325
40
290
40
265
40
240
40
225
40
mA
mA
Shaded areas contain advance information. Please contact your local Cypress Sales representative for availability of these parts.
Pin Configurations
100-Pin TQFP
DQPC
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
2
3
4
5
6
BYTE C
BYTE B
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
NC
VDD
VSS
ZZ
CY7C1347F
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
BYTE D
BYTE A
Document #: 38-05213 Rev. *D
Page 2 of 19
CY7C1347F
Pin Configurations (continued)
119-Ball BGA
2
A
CE2
A
1
3
A
A
4
5
A
A
6
A
CE3
A
7
VDDQ
NC
NC
ADSP
ADSC
VDD
VDDQ
NC
NC
A
B
C
D
E
F
G
H
J
A
A
DQC
DQC
VDDQ
DQC
DQC
VDDQ
DQD
DQPC
DQC
DQC
DQC
DQC
VDD
DQD
VSS
VSS
VSS
NC
CE1
VSS
VSS
VSS
BWB
VSS
NC
DQPB
DQB
DQB
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
OE
ADV
GW
VDD
BWC
VSS
NC
K
VSS
CLK
VSS
L
M
N
DQD
VDDQ
DQD
DQD
DQD
DQD
BWD
VSS
VSS
NC
BWE
A1
BWA
VSS
VSS
DQA
DQA
DQA
DQA
VDDQ
DQA
P
R
T
DQD
NC
NC
DQPD
A
NC
VSS
MODE
A
A0
VDD
A
VSS
NC
A
DQPA
A
NC
DQA
NC
ZZ
VDDQ
NC
NC
NC
NC
NC
VDDQ
U
165-Ball fBGA
1
2
A
A
NC
DQC
DQC
DQC
DQC
VSS
3
4
5
6
7
8
9
10
11
NC
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
NC
CE1
CE2
BWC
BWB
CE3
BWE
GW
VSS
VSS
VSS
ADSC
ADV
A
A
B
C
D
E
F
G
H
J
K
L
NC
DQPC
DQC
BWD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
DQB
DQB
DQB
DQB
NC
DQA
DQA
DQA
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
DQC
DQC
DQC
NC
DQD
DQD
DQD
VSS
VSS
VSS
VSS
VSS
VSS
DQD
DQD
DQD
DQD
DQPD
NC
DQD
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
NC
VSS
NC
A1
VSS
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
NC
M
N
P
A0
MODE
NC
A
A
NC
NC
A
A
A
A
R
Document #: 38-05213 Rev. *D
Page 3 of 19
CY7C1347F
Pin Definitions
Name
(1N00aTmQFeP)
I/O
Description
(BGA,FBGA)
A0,A1,A
A[16:0]
Input-
Address Inputs used to select one of the 128K address locations. Sampled at
Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
are sampled active. A[1:0] feeds the 2-bit counter.
BWA,BWB,
BWC,BWD
GW
BW[A:D]
GW
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
Synchronous to the SRAM. Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
Synchronous of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW[A:D] and BWE).
BWE
CLK
CE1
BWE
CLK
CE1
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
Synchronous signal must be asserted LOW to conduct a byte write.
Input-Clock
Input-
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH.
CE2
CE3
OE
CE2
CE3
OE
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3 to select/deselect the device.
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the
Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.
ADV
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK. When
Synchronous asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted
HIGH.
ADSC
ZZ
ADSC
ZZ
Input-
Address Strobe from Controller, sampled on the rising edge of CLK. When
Synchronous asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has
to be LOW or left floating. ZZ pin has an internal pull-down.
DQA, DQB
DQs
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
DQC, DQD
DQPs
Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are
placed in a three-state condition.
DQPA, DQPB,
DQPC, DQPD
VDD
VSS
VDDQ
VDD
VSS
VDDQ
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the core of the device.
Power supply for the I/O circuitry.
I/O Power
Supply
VSSQ
VSSQ
I/O Ground
Ground for the I/O circuitry.
MODE
MODE
Input-
Selects Burst Order. When tied to GND selects linear burst sequence. When tied
to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
Static
NC
NC
No Connects.
Document #: 38-05213 Rev. *D
Page 4 of 19
CY7C1347F
BW[A:D] signals. The CY7C1347F provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BW[A:D]) input will selectively write to only the
desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so will three-state the
output drivers. As a safety precaution, DQs and DQPs are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (TCO) is 2.6 ns
(250-MHz device).
The CY7C1347F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Address Strobe from Processor
(ADSP) or the Address Strobe from Controller (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW[A:D]) are asserted active to conduct a write to
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A[16:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQs and DQPs is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
Because the CY7C1347F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so will three-state the
output drivers. As a safety precaution, DQs and DQPs are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
is HIGH. The address presented to the address inputs (A[16:0]
)
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the Output Register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Burst Sequences
The CY7C1347F provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user-selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asserted active. The address presented
to A[16:0] is loaded into the Address Register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW[A:D]) and ADV inputs are
ignored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs and DQPs inputs is written into the
corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Document #: 38-05213 Rev. *D
Page 5 of 19
CY7C1347F
Linear Burst Sequence
Interleaved Burst Sequence
First
Second
Third
Address
Fourth
First
Second
Third
Fourth
Address
Address
Address
Address
Address
Address
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current This parameter is sampled
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
Min.
Max.
40
2tCYC
Unit
mA
ns
ns
ns
IDDZZ
tZZS
tZZREC
tZZI
2tCYC
0
This parameter is sampled
2tCYC
tRZZI
ns
Truth Table[2, 3, 4, 5, 6]
Add.
Next Cycle
Used
CE2
X
L
X
L
WRITE
DQ
CE1
CE3
ZZ
ADSP ADSC ADV
OE CLK
Deselect Cycle, Power-down None
Deselect Cycle, Power-down None
Deselect Cycle, Power-down None
Deselect Cycle, Power-down None
Deselect Cycle, Power-down None
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
X
X
X
X
X
X
L
L-H three-state
L-H three-state
L-H three-state
L-H three-state
L-H three-state
three-state
Q
L-H three-state
L
L
L
L
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
L
Snooze Mode, Power-down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
None
External
External
External
External
External
Next
Next
Next
Next
Next
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
X
L-H
L
H
X
L
H
H
H
H
H
X
X
H
X
H
H
X
X
L-H
L-H
D
Q
H
L
H
L
L-H three-state
L-H
L-H three-state
L-H
L-H three-state
Q
L
L
L
L
Q
H
X
X
L
L-H
L-H
L-H
D
D
Q
Next
L
L
READ Cycle, Suspend Burst Current
READ Cycle, Suspend Burst Current
READ Cycle, Suspend Burst Current
H
H
H
H
H
H
H
H
H
L
H
L-H three-state
L-H
L-H three-state
Q
READ Cycle, Suspend Burst Current
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW ) and BWE = L or GW = L. WRITE = H when all Byte write enable signals
A
B
C
D
(BW , BW , BW , BW ), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the
signal.
is asynchronous and is not sampled with the clock.
OE
OE
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A:D]
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when
OE
OE
is
.
is active (LOW)
inactive or when the device is deselected, and all data bits behave as output when
OE
Document #: 38-05213 Rev. *D
Page 6 of 19
CY7C1347F
Truth Table[2, 3, 4, 5, 6]
Add.
Next Cycle
Used
CE2
X
X
WRITE
DQ
D
D
CE1
CE3
ZZ
ADSP ADSC ADV
OE CLK
WRITE Cycle, Suspend Burst Current
WRITE Cycle, Suspend Burst Current
X
X
L
H
X
H
H
H
H
L
L
X
X
L-H
L-H
H
X
L
Partial Truth Table for Read/write[2, 7]
Function
BWD
BWC
BWB
BWA
GW
BWE
Read
Read
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
H
H
L
X
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Write Byte A – DQA
Write Byte B – DQB
Write Bytes B, A
Write Byte C– DQC
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D– DQD
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
H
H
L
L
H
H
L
L
H
H
L
L
X
L
L
L
X
Write All Bytes
X
Notes:
7. Table only lists a partial listing of the byte write combinations. Any combination of BW
is valid. Appropriate write will be done based on which byte write is active.
[A:D]
Document #: 38-05213 Rev. *D
Page 7 of 19
CY7C1347F
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature ..................................... −65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Range Temperature
VDD
VDDQ
DC Voltage Applied to Outputs
Com’l
Ind’l
0°C to +70°C
–40°C to +85°C
3.3V −5%/+10%
2.5V −5%
in High-Z State........................................... −0.5V to VDD + 0.5V
to VDD
DC Input Voltage ....................................... −0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range [8, 9]
Parameter
VDD
VDDQ
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Test Conditions
Min.
3.135
2.375
2.4
Max.
3.6
VDD
Unit
V
V
V
V
V
V
V
V
V
V
µA
VOH
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
DDQ = 2.5V, VDD = Min., IOL = 2.0 mA
VDDQ = 3.3V
DDQ = 2.5V
2.0
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH Voltage[8]
Input LOW Voltage[8]
0.4
0.7
VDD + 0.3V
V
2.0
1.7
–0.3
–0.3
−5
V
VDD + 0.3V
VDDQ = 3.3V
VDDQ = 2.5V
0.8
0.7
5
Input Load Current ex- GND ≤ VI ≤ VDDQ
cept ZZ and MODE
Input Current of MODE Input = VSS
Input = VDDQ
−30
−5
µA
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDDQ
30
5
µA
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
−5
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
4-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
All speeds
325
290
265
240
225
120
115
110
100
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
Automatic CE
Max. VDD, Device Deselected,
Power-down
VIN ≥ VIH or VIN ≤ VIL
Current—TTL Inputs
f = fMAX = 1/tCYC
ISB2
Automatic CE
Power-down
Max. VDD, Device Deselected,
40
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V, f
Current—CMOS Inputs = 0
Notes:
8. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > -2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
9. T
: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V
< V
DDQ DD
Power-up
DD
IH
DD
Document #: 38-05213 Rev. *D
Page 8 of 19
CY7C1347F
Electrical Characteristics Over the Operating Range (continued)[8, 9]
Parameter
ISB3
Description
Automatic CE
Power-down
Test Conditions
Min.
Max.
105
100
95
85
75
Unit
mA
mA
mA
mA
mA
mA
Max. VDD, Device Deselected, or 4-ns cycle, 250 MHz
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
ISB4
Automatic CE
Max. VDD, Device Deselected,
45
Power-down
V
IN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Shaded areas contain advance information.
Capacitance[10]
BGA
fBGA
TQFP
Parameter
CIN
Description
Input Capacitance
Test Conditions
Package
Package
Package
Unit
TA = 25°C, f = 1
5
5
5
5
5
7
5
5
7
pF
pF
pF
MHz,
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
VDD = 3.3V.
V
DDQ = 3.3V
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
10%
L
GND
≤ 1ns
5 pF
R = 351Ω
≤ 1ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R =1538Ω
≤ 1ns
≤ 1ns
INCLUDING
JIG AND
SCOPE
V = 1.25V
L
(c)
(a)
(b)
Thermal Resistance[10]
TQFP
BGA
fBGA
Parameter
Description
Test Conditions
Package
Package
Package
Unit
QJA
Thermal Resistance
Test conditions follow standard
41.83
47.63
20.3
°C/W
(Junction to Ambient) testmethodsandproceduresfor
measuring thermal impedance,
Thermal Resistance
QJC
9.99
11.71
4.6
°C/W
per EIA / JESD51.
(Junction to Case)
Note:
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05213 Rev. *D
Page 9 of 19
CY7C1347F
Switching Characteristics Over the Operating Range[15, 16]
-250
-225
-200
-166
-133
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPOWER
VDD(min.) to the first access
1
1
1
1
1
ms
read or write [11]
tCYC
tCH
tCL
Clock Cycle Time
Clock HIGH
Clock LOW
4.0
1.7
1.7
0.8
4.4
2.0
2.0
1.2
5.0
2.0
2.0
1.2
6.0
2.5
2.5
1.5
7.5
3.0
3.0
1.5
ns
ns
ns
ns
tAS
Address Set-up Before CLK
Rise
tAH
tCO
Address Hold After CLK Rise
0.4
0.5
0.5
0.5
0.5
ns
ns
Data Output Valid After CLK
2.6
2.6
2.8
3.5
4.0
Rise
tDOH
tWES
tWEH
tALS
Data Output Hold After CLK
Rise
1.0
0.8
0.4
0.8
0.4
1.0
1.2
0.5
1.2
1.0
1.2
0.5
1.2
2.0
1.5
0.5
1.5
2.0
1.5
0.5
1.5
ns
ns
ns
ns
GW, BWS[3:0] Set-up Before
CLK Rise
GW, BWS[3:0] Hold After CLK
Rise
ADV/LD Set-up Before CLK
Rise
tALH
tDS
ADV/LD Hold after CLK Rise
0.5
1.2
0.5
1.2
0.5
1.5
0.5
1.5
ns
ns
Data Input Set-up Before CLK 0.8
Rise
tDH
Data Input Hold After CLK
Rise
0.4
0.8
0.4
0.5
1.2
0.5
0.5
1.2
0.5
0.5
1.5
0.5
0.5
1.5
0.5
ns
ns
ns
tCES
tCEH
Chip Enable Set-up Before
CLK Rise
Chip Enable Hold After CLK
Rise
tCHZ
tCLZ
tEOHZ
Clock to High-Z[12, 13, 14]
2.6
2.6
2.6
2.6
2.8
2.8
3.5
3.5
4.0
4.0
ns
ns
ns
Clock to Low-Z[12, 13, 14]
0
0
0
0
0
0
0
0
0
0
OE HIGH to Output
High-Z[12, 13, 14]
tEOLZ
OE LOW to Output
ns
ns
Low-Z[12, 13, 14]
tEOV
OE LOW to Output Valid
2.6
2.6
2.8
3.5
4.5
Notes:
11. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation
DD
POWER
12. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
13. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
15. Timing references level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V on all data sheets.
DDQ
DDQ
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05213 Rev. *D
Page 10 of 19
CY7C1347F
Switching Waveforms
Read Cycle Timing[17]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BW[A:D]
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
OELZ
t
CHZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Notes:
17. On this diagram when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH,CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
18. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW and BW
LOW.
[A:D]
Document #: 38-05213 Rev. *D
Page 11 of 19
CY7C1347F
Switching Waveforms (continued)
Write Cycle Timing[17, 18]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE,
BW[A:D]
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Document #: 38-05213 Rev. *D
Page 12 of 19
CY7C1347F
Switching Waveforms (continued)
Read/Write Cycle Timing[17, 19, 20]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE,
BW[A:D]
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Note:
19. The data bus (Q)remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
20. GW is HIGH
Document #: 38-05213 Rev. *D
Page 13 of 19
CY7C1347F
Switching Waveforms (continued)
ZZ Mode Timing [21, 22]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
22. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05213 Rev. *D
Page 14 of 19
CY7C1347F
Ordering Information
Speed
Package
Name
A101
BG119
A101
BG119
A101
BG119
BB165C
A101
BG119
A101
BG119
BB165C
A101
BG119
A101
BG119
BB165C
A101
Operating
Range
(MHz)
Ordering Code
Package Type
100-Lead Thin Quad Flat Pack
119-Ball BGA
100-Lead Thin Quad Flat Pack
119-Ball BGA
100-Lead Thin Quad Flat Pack
119-Ball BGA
165-Ball FBGA
100-Lead Thin Quad Flat Pack
119-Ball BGA
100-Lead Thin Quad Flat Pack
119-Ball BGA
165-Ball FBGA
100-Lead Thin Quad Flat Pack
119-Ball BGA
250
CY7C1347F-250AC
CY7C1347F-250BGC
CY7C1347F-225AC
CY7C1347F-225BGC
CY7C1347F-200AC
CY7C1347F-200BGC
CY7C1347F-200BZC
CY7C1347F-200AI
CY7C1347F-200BGI
CY7C1347F-166AC
CY7C1347F-166BGC
CY7C1347F-166BZC
CY7C1347F-166AI
CY7C1347F-166BGI
CY7C1347F-133AC
CY7C1347F-133BGC
CY7C1347F-133BZC
CY7C1347F-133AI
CY7C1347F-133BGI
Commercial
Commercial
Commercial
225
200
Industrial
166
133
Commercial
Industrial
100-Lead Thin Quad Flat Pack
119-Ball BGA
165-Ball FBGA
100-Lead Thin Quad Flat Pack
119-Ball BGA
Commercial
Industrial
BG119
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05213 Rev. *D
Page 15 of 19
CY7C1347F
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05213 Rev. *D
Page 16 of 19
CY7C1347F
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05213 Rev. *D
Page 17 of 19
CY7C1347F
Package Diagrams (continued)
165-Ball FBGA (15 x 17 x 1.20 mm) BB165C
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45 0.05ꢀ1ꢁ5ꢂX
1
2
3
4
5
ꢁ
7
8
9
10
11
11 10
9
8
7
ꢁ
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15ꢀ4ꢂX
SEATING PLANE
C
51-85165-*A
Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a registered trademark of International Business
Machines, Inc. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05213 Rev. *D
Page 18 of 19
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1347F
Document History Page
Document Title: CY7C1347F 4-Mbit (128K x 36) Pipelined Sync SRAM
Document Number: 38-05213
Orig. of
REV.
**
*A
*B
*C
ECN NO. Issue Date Change Description of Change
119829
123117
127632
200660
12/16/02
01/18/03
06/13/03
See ECN
HGK
RBI
DPM
SWI
New Data Sheet
Added power-up requirements to AC test loads and waveforms information
Final Data Sheet
Improvements:
Updated thermal resistance and capacitance
Updated R5 pin of 119-Ball BGA from VDD to NC
Updated all switching waveforms
Clarifications:
Updated footnotes
Updated ZZ mode electrical characteristics
*D
213342
See ECN
VBL
Update Ordering Info section: Delete -100, shade -250, -225
Delete -100, Shade -250, -225 data from selection guide and characteristics
Document #: 38-05213 Rev. *D
Page 19 of 19
相关型号：
CY7C1347F-133ACT
Cache SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
©2020 ICPDF网 联系我们和版权申明