CY7C1351B-117BGC [CYPRESS]
ZBT SRAM, 128KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119;
| 型号： | CY7C1351B-117BGC |
| 厂家： | 
CYPRESS |
| 描述： | ZBT SRAM, 128KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 静态存储器 |
| 文件： | 总16页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
351B
PRELIMINARY
CY7C1351B
128Kx36 Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
• Pincompatible andfunctionallyequivalenttoZBT™ de-
The CY7C1351B is a 3.3V, 128K by 36 Synchronous
Flow-Through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1351B is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to en-
able consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data through the SRAM, especially in sys-
tems that require frequent Write/Read transitions. The
CY7C1351B is pin/functionally compatible to ZBT SRAMs
IDT71V547, MT55L128L36F, and MCM63Z737.
vices IDT71V547, MT55L128L36F, and MCM63Z737
• Supports 66-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for Flow-Through operation
• Byte Write capability
• 128K x 36 common I/O architecture
• Single 3.3V power supply
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock Enable (CEN) signal, which, when deasserted, sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 7.5 ns (117-MHz
device).
• Fast clock-to-output times
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
— 11.0 ns (for 66-MHz device)
— 12.0 ns (for 50-MHz device)
Write operations are controlled by the four Byte Write Select
(BWS[3:0]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
— 14.0 ns (for 40-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Standard 100 TQFP and 119 BGA packages
• Burst Capability—linear or interleaved burst order
Low standby power
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
36
D
CLK
Data-In REG.
CE
Q
36
ADV/LD
17
A
[16:0]
CEN
CONTROL
and WRITE
LOGIC
36
128KX36
CE
1
CE
2
MEMORY
DQ
ARRAY
[31:0]
CE
3
17
DP
WE
[3:0]
BWS
[3:0]
Mode
OE
.
Selection Guide
7C1351B-117 7C1351B-100 7C1351B-66 7C1351B-50 7C1351B-40
Maximum Access Time (ns)
7.5
8.5
11.0
12.0
14.0
Maximum Operating Current
(mA)
Commercial
Commercial
375 mA
350 mA
250 mA
200 mA
175 mA
Maximum CMOS Standby
Current (mA)
5 mA
5 mA
5 mA
5 mA
5 mA
Cypress Semiconductor Corporation
Document #: 38-05208 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 19, 2002
PRELIMINARY
CY7C1351B
Pin Configuration
100-Pin TQFP
DP
DP
2
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
DQ
DQ
16
2
15
DQ
17
3
DQ
14
V
DDQ
4
V
DDQ
V
SS
5
V
SS
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
V
18
19
20
21
6
13
12
11
10
7
8
9
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
V
V
DDQ
DDQ
CY7C1351B
DQ
DQ
DQ
DQ
V
22
23
9
8
V
V
SS
SS
SS
DD
V
V
DD
DD
V
V
V
SS
SS
DQ
DQ
V
DQ
DQ
V
24
25
7
6
DDQ
DDQ
SS
V
V
SS
DQ
DQ
DQ
DQ
DQ
V
26
27
28
29
5
4
3
2
DQ
DQ
DQ
V
SS
SS
V
V
DDQ
DDQ
DQ
DQ
DQ
DQ
DP
30
31
1
0
DP
3
0
Document #: 38-05208 Rev. *A
Page 2 of 16
PRELIMINARY
CY7C1351B
Pin Configuration
119-Ball Bump BGA
CY7C1351B (128K x 36) - 7 x 17 BGA
1
2
3
4
5
6
7
V
A
A
16M
A
A
V
DDQ
A
B
C
D
E
F
DDQ
NC
NC
DQ
CE
A
A
A
ADV/LD
A
A
CE
A
NC
NC
DQ
2
3
b
V
DD
DP
V
NC
V
DP
c
c
SS
SS
SS
SS
SS
SS
b
DQ
DQ
DQ
V
V
CE
V
V
DQ
DQ
DQ
b
c
c
c
1
b
b
V
OE
V
DDQ
DDQ
DQ
DQ
DQ
V
BWS
8M
BWS
DQ
DQ
V
DQ
G
H
J
c
c
c
c
c
b
b
b
b
b
DQ
V
WE
V
DQ
SS
SS
V
V
V
V
V
DDQ
DDQ
DD
SS(1)
DD
SS(1)
DD
DQ
DQ
V
CLK
NC
V
DQ
DQ
K
d
d
d
SS
SS
a
a
DQ
DQ
DQ
BWS
BWS
DQ
DQ
DQ
DP
DQ
L
M
N
P
d
d
a
a
a
a
a
V
V
V
V
DDQ
CEN
A1
DDQ
d
SS
SS
DQ
DQ
V
V
DQ
d
d
d
SS
SS
a
a
DQ
DP
A
V
A0
V
DQ
d
SS
SS
a
NC
NC
MODE
A
V
V
A
NC
NC
R
T
DD
SS
64M
TMS
A
A
32M
V
TDI
TCK
TDO
DNU
V
DDQ
U
DDQ
Document #: 38-05208 Rev. *A
Page 3 of 16
PRELIMINARY
CY7C1351B
Pin Definitions
Name
I/O
Description
A[16:0]
Input-
Synchronous
Address Inputs used to select one of the 133,072 address locations. Sampled at the rising
edge of the CLK.
BWS[3:0]
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWS0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8]
and DP1, BWS2 controls DQ[23:16] and DP2, BWS3 controls DQ[31:24] and DP3.
WE
Input-
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
Synchronous
This signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load input used to advance the on-chip address counter or load a new ad-
dress. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an access. After being deselected,
ADV/LD should be driven LOW in order to load a new address.
CLK
CE1
CE2
CE3
OE
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.
Input-
Asynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the first clock when emerging from a
deselected state and when the device has been deselected.
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQ[31:0]
I/O-
Synchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQ[31:0] are placed in a three-state condition. The outputs are auto-
matically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state
of OE.
DP[3:0]
MODE
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ[31:0]. Dur-
ing write sequences, DP0 is controlled by BWS0, DP1 is controlled by BWS1, DP2 is controlled
by BWS2, and DP3 is controlled by BWS3.
Input
Strap pin
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst
order. Pulled LOW selects the linear burst order. MODE should not change states during
operation. When left floating MODE will default HIGH, to an interleaved burst order.
VDD
Power Supply
Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
VDDQ
I/O Power
Supply
VSS
NC
Ground
-
Ground for the device. Should be connected to ground of the system.
No Connects. Reserved for address inputs for depth expansion. Pins 83 and 84 will be used
for 256K and 512K depths respectively.
DNU
-
Do Not Use pins. These pins should be left floating or tied to VSS.
Document #: 38-05208 Rev. *A
Page 4 of 16
PRELIMINARY
CY7C1351B
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Introduction
Functional Overview
The CY7C1351B is a Synchronous Flow-Through Burst
SRAM designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (tCDV) is 7.5 ns (117-MHz device).
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to A0–A16 is loaded
into the Address Register. The write signals are latched into
the Control Logic block. The data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ[31:0] and
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The ac-
cess can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BWS[3:0] can be used to
conduct byte write operations.
DP[3:0]
.
On the next clock rise the data presented to DQ[31:0] and
DP[3:0] (or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device
and the write is complete. Additional accesses
(Read/Write/Deselect) can be initiated on this cycle.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.
The data written during the Write operation is controlled by
BWS[3:0] signals. The CY7C1351B provides byte write capa-
bility that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BWS[3:0]) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-
ple byte write operations.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs (A0–A16
)
is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the output buffers. The data is available
within 7.5 ns (117-MHz device) provided OE is active LOW.
After the first clock of the read access the output buffers are
controlled by OE and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. On the subsequent clock, another operation
(Read/Write/Deselect) can be initiated. When the SRAM is de-
selected at clock rise by one of the chip enable signals, its
output will three-stated immediately.
Because the CY7C1351B is a common I/O device, Data
should not be driven into the device while the outputs are ac-
tive. The Output Enable (OE) can be deasserted HIGH before
presenting data to the DQ[31:0] and DP[3:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[31:0]
and DP[3:0].are automatically three-stated during the data por-
tion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1351B has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial ad-
dress, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise,
the chip enables (CE1, CE2, and CE3) and WE inputs are ig-
nored and the burst counter is incremented. The correct
BWS[3:0] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Burst Read Accesses
The CY7C1351B has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
Document #: 38-05208 Rev. *A
Page 5 of 16
PRELIMINARY
CY7C1351B
.
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
ADV/L
D
Address
Operation
Used
CE
CEN
WE
BWSx
CLK
L-H
Comments
Deselected
External
1
0
L
X
X
I/Os three-state following next
recognized clock.
Suspend
-
X
1
X
X
X
L-H
Clock ignored, all operations
suspended.
Begin Read
Begin Write
External
External
0
0
0
0
0
0
1
0
X
L-H
Address latched.
Valid L-H
L-H
Address latched, data presented two
valid clocks later.
Burst Read
Operation
Internal
X
0
1
X
X
Burst Read operation. Previous ac-
cess was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of MODE.
Burst Write
Operation
Internal
X
0
1
X
Valid L-H
Burst Write operation. Previous ac-
cess was a Write operation. Address-
es incremented internally in conjunc-
tion with the state of MODE. Bytes
written are determined by BWS[3:0]
.
Notes:
1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWS = 0 signifies at least one Byte Write Select is active, BWS
x
x
= Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS
. See Write Cycle Description table for details.
[3:0]
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN=1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
Document #: 38-05208 Rev. *A
Page 6 of 16
PRELIMINARY
CY7C1351B
Interleaved Burst Sequence
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
First
Address
Second
Address
Third
Address
Fourth
Address
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Write Cycle Description[1, 2]
Function
WE
1
BWS3
BWS2
BWS1
BWS0
Read
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Write − No bytes written
Write Byte 0 − (DQ[7:0] and DP0)
Write Byte 1 – (DQ[15:8] and DP1)
Write Bytes 1, 0
0
0
0
0
Write Byte 2 − (DQ[23:16] and DP2)
Write Bytes 2, 0
0
0
Write Bytes 2, 1
0
Write Bytes 2, 1, 0
0
Write Byte 3 − (DQ[31:24] and DP3)
Write Bytes 3, 0
0
0
Write Bytes 3, 1
0
Write Bytes 3, 1, 0
0
Write Bytes 3, 2
0
Write Bytes 3, 2, 0
0
Write Bytes 3, 2, 1
0
Write All Bytes
0
Document #: 38-05208 Rev. *A
Page 7 of 16
PRELIMINARY
CY7C1351B
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Ambient
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Range
Com’l
Temperature[8]
VDD/VDDQ
DC Voltage Applied to Outputs
in High Z State[7]......................................−0.5V to VDDQ + 0.5V
0°C to +70°C
3.3V ± 5%
DC Input Voltage[7]..................................−0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Test Conditions
Min.
Max.
3.465
3.465
Unit
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
3.135
3.135
2.4
V
V
V
V
V
VDDQ
VOH
VDD = Min., IOH = –4.0 mA[9]
VDD = Min., IOL = 8.0 mA[9]
VOL
0.4
VIH
2.0
VDD +
0.3V
0.8
5
VIL
IX
Input LOW Voltage[7]
Input Load Current
–0.3
–5
V
GND ≤ VI ≤ VDDQ
mA
mA
mA
Input Current of MODE
–30
–5
30
5
IOZ
ICC
Output Leakage
Current
GND ≤ VI ≤ VDDQ, Output Disabled
VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
15-ns cycle, 66 MHz
20-ns cycle, 50 MHz
25-ns cycle, 40 MHz
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
15-ns cycle, 66 MHz
20-ns cycle, 50 MHz
25-ns cycle, 40 MHz
All speed grades
375
350
250
200
175
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
80
60
40
35
ISB2
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. VDD, Device Deselected,
5
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f =0
ISB3
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. VDD, Device Deselected, or 8.5-ns cycle, 117 MHz
80
70
50
40
35
mA
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ –0.3V
10-ns cycle, 100 MHz
15-ns cycle, 66 MHz
20-ns cycle, 50 MHz
25-ns cycle, 40 MHz
f = fMAX = 1/tCYC
Notes:
7. Minimum voltage equals –2.0V for pulse duration less than 20 ns.
8. A is the case temperature.
T
9. The load used for VOH and VOL testing is shown in figure (b) of the AC Test Loads.
Document #: 38-05208 Rev. *A
Page 8 of 16
PRELIMINARY
CY7C1351B
Capacitance[10]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ = 3.3V
4
4
4
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
AC Test Loads and Waveforms
R = 317Ω
3.3V
OUTPUT
OUTPUT
ALL INPUT PULSES
Z = 50Ω
0
3.0V
R = 50Ω
L
5 pF
R = 351Ω
GND
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(a)
(b)
Thermal Resistance
Description
Test Conditions
Symbol
TQFP Typ.
Units
Notes
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board
ΘJA
28
°C/W
10
Thermal Resistance
(Junction to Case)
ΘJC
4
°C/W
10
Note:
10. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05208 Rev. *A
Page 9 of 16
PRELIMINARY
CY7C1351B
Switching Characteristics Over the Operating Range[11, 12, 13]
-117
-100
-66
-50
-40
Parameter
Clock
tCYC
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Clock Cycle Time
8.5
10.0
15
20
ns
MHz
ns
FMAX
Maximum Operating Frequency
Clock HIGH
117
100
66
50
40
tCH
1.9
1.9
1.9
1.9
5.0
5.0
6.0
6.0
7.0
7.0
tCL
Clock LOW
ns
Output Times
tCDV
Data Output Valid After CLK
Rise
7.5
4.2
8.5
5.0
11.0
6.0
12.0
7.0
14.0
8.0
ns
tEOV
tDOH
OE LOW to Output Valid[10,11]
ns
ns
Data Output Hold After CLK
Rise
1.5
1.5
1.5
3.0
0
1.5
3.0
0
1.5
3.0
tCHZ
tCLZ
Clock to High-Z[10,11,12,13]
Clock to Low-Z[10,11,12,13]
1.5
3
4.2
4.2
1.5
3
5.0
5.0
5.0
6.0
5.0
7.0
5.0
8.0
ns
ns
ns
tEOHZ
OE HIGH to Output
High-Z[10,11,12,13]
tEOLZ
OE LOW to Output
Low-Z[10,11,12,13]
0
0
ns
Set-up Times
tAS
Address Set-up Before CLK
Rise
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.5
ns
ns
tDS
Data Input Set-up Before CLK
Rise
tCENS
tWES
CEN Set-up Before CLK Rise
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.5
2.5
ns
ns
WE, BWSx Set-up Before CLK
Rise
tALS
ADV/LD Set-up Before CLK
Rise
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.5
2.5
ns
ns
tCES
Chip Select Set-up
Hold Times
tAH
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
WE, BWSx Hold After CLK Rise 0.5
ADV/LD Hold After CLK Rise 0.5
Chip Select Hold After CLK Rise 0.5
tALH
tCEH
Notes:
11. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
12. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. This parameter is sampled and not 100% tested. tCHZ, tCLZ, tOEV, tEOLZ and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads.
Transition is measured +200 mV from steady
Document #: 38-05208 Rev. *A
Page 10 of 16
PRELIMINARY
CY7C1351B
Switching Waveforms
Read/Write/Deselect Sequence
CLK
tCENH
tCENH
tCENS
tCENS
tCL
tCH
tCYC
CEN
tAS
WA2
WA5
RA1
RA3
RA4
RA6
RA7
ADDRESS
tAH
WE
tWS
tWH
tCES
tCEH
CE
tDOH
tCHZ
tDOH
tCLZ
tCHZ
Q6
Out
Q4
Out
D5
In
Data-
In/Out
D2
In
Q7
Out
Q3
Out
Q1
Out
Device
tCDV
originally
deselected
WE is the combination of WE & BWSx to define a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip selects need to be active in order to select
the device. Any chip select can deselect the device. RAx stands for Read Address X, WAx stands for
Write Address X, Dx stands for Data-in X, Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
Document #: 38-05208 Rev. *A
Page 11 of 16
PRELIMINARY
CY7C1351B
Switching Waveforms (continued)
Burst Sequences
CLK
tALH
tALS
tCL
tCH
tCYC
ADV/LD
tAH
tAS
RA1
WA2
ADDRESS
WE
RA3
tWS
tWH
tWS
tWH
BWS[3:0]
tCES
tCEH
CE
tCLZ
tCHZ
tDH
tDOH
tCLZ
Q3
Out
Q1
Q1+2
Out
Q1+3
Out
D2
In
D2+2
In
D2+3
In
Data-
In/Out
Q1+1
Out
D2+1
In
Q3+1
Out
Out
tCDV
tCDV
tDS
Device
originally deselected
The combination of WE & BWS[3:0] defines a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS[3:0] input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
= UNDEFINED
= DON’T CARE
Document #: 38-05208 Rev. *A
Page 12 of 16
PRELIMINARY
CY7C1351B
Switching Waveforms (continued)
OE Timing
OE
tEOV
tEOHZ
Three-state
I/Os
tEOLZ
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
117
100
66
Ordering Code
Package Type
CY7C1351B-117AC
CY7C1351B-100AC
CY7C1351B-66AC
CY7C1351B-50AC
CY7C1351B-40AC
CY7C1351B-117BGC
CY7C1351B-100BGC
CY7C1351B-66BGC
CY7C1351B-50BGC
CY7C1351B-40BGC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead PBGA (14 x 22 x 2.4 mm)
Commercial
50
40
117
100
66
BG119
Commercial
119-Lead PBGA (14 x 22 x 2.4 mm)
119-Lead PBGA (14 x 22 x 2.4 mm)
50
119-Lead PBGA (14 x 22 x 2.4 mm)
40
119-Lead PBGA (14 x 22 x 2.4 mm)
Document #: 38-05208 Rev. *A
Page 13 of 16
PRELIMINARY
CY7C1351B
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05208 Rev. *A
Page 14 of 16
PRELIMINARY
CY7C1351B
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05208 Rev. *A
Page 15 of 16
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY7C1351B
Document History Page
Document Title: CY7C1351B 128K x 36 Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05208
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
115440
Description of Change
Change from Spec number: 38-00691 to 38-05208
Updated package diagram 51-85115 (BG119) to rev. *B
05/06/02
11/21/02
DSG
DSG
*A
121535
Document #: 38-05208 Rev. *A
Page 16 of 16
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