CY7C1351F-133AI [CYPRESS]
4-Mb (128K x 36) Flow-through SRAM with NoBL⑩ Architecture; 4 -MB （ 128K ×36 ）与NoBL⑩架构流通式SRAM
| 型号： | CY7C1351F-133AI |
| 厂家： | 
CYPRESS |
| 描述： | 4-Mb (128K x 36) Flow-through SRAM with NoBL⑩ Architecture |
| 文件： | 总15页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1351F
4-Mb (128K x 36) Flow-through SRAM with
• Burst Capability—linear or interleaved burst order
• Low standby power
Features
• Can support up to 133-MHz bus operations with zero
Functional Description[1]
wait states
— Data is transferred on every clock
The CY7C1351F is a 3.3V, 128K x 36 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1351F is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 128K x 36 common I/O architecture
• 2.5V / 3.3V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
— 8.0 ns (for 100-MHz device)
— 11.0 ns (for 66-MHz device)
Write operations are controlled by the four Byte Write Select
(BW[A:D]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP and 119 BGA packages
Logic Block Diagram
ADDRESS
A0, A1, A
REGISTER
A1
A1'
A0'
D1
A0
Q1
Q0
D0
MODE
BURST
LOGIC
CE
ADV/LD
C
CLK
CEN
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD
A
B
U
F
MEMORY
ARRAY
BWA
BWB
BWC
BWD
WRITE
DRIVERS
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
A
B
C
D
A
M
P
F
E
R
S
S
WE
E
N
G
INPUT
REGISTER
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
Control
ZZ
1
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05210 Rev. *B
Revised January 12, 2004
CY7C1351F
Selection Guide
133 MHz
6.5
117 MHz
7.5
100 MHz
8.0
66 MHz
11.0
195
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
225
40
220
40
205
40
40
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configurations
100-lead TQFP
DQP
DQ
DQ
V
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
DQP
B
C
C
C
DQ
B
DQ
B
V
DDQ
DDQ
V
V
SS
SS
DQ
DQ
C
B
BYTE B
DQ
C
BYTE C
DQ
B
DQ
DQ
C
B
DQ
C
9
DQ
B
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
V
DDQ
DDQ
DQ
DQ
C
B
DQ
C
NC
DQ
B
CY7C1351F
V
SS
V
NC
DD
NC
V
DD
V
ZZ
SS
DQ
DQ
DQ
V
D
A
A
DQ
D
V
DDQ
DDQ
V
V
SS
SS
DQ
DQ
DQ
DQ
DQ
V
D
A
A
A
A
DQ
D
BYTE D
BYTE A
DQ
D
DQ
D
V
SS
SS
V
V
DDQ
DDQ
DQ
DQ
D
A
DQ
D
DQ
A
DQP
DQP
D
A
Document #: 38-05210 Rev. *B
Page 2 of 15
CY7C1351F
Pin Configurations (continued)
119-Ball BGA
2
A
1
3
A
4
NC
5
A
6
A
7
VDDQ
VDDQ
A
B
C
D
E
F
G
H
J
NC
NC
CE2
A
A
A
A
A
NC
NC
ADV/LD
VDD
NC
CE1
OE
NC
WE
VDD
CLK
CE3
A
DQC
DQC
VDDQ
DQC
DQC
VDDQ
DQD
DQPC
DQC
DQC
DQC
DQC
VDD
DQD
VSS
VSS
VSS
BWC
VSS
VSS
VSS
VSS
VSS
VSS
BWB
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
DQB
VDD
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
K
DQA
L
M
N
DQD
VDDQ
DQD
DQD
DQD
DQD
BWD
VSS
VSS
NC
CEN
A1
BWA
VSS
VSS
DQA
DQA
DQA
DQA
VDDQ
DQA
P
R
T
DQD
NC
NC
DQPD
A
NC
VSS
MODE
A
A0
VDD
A
VSS
NC
A
DQPA
A
NC
DQA
NC
ZZ
VDDQ
NC
NC
NC
NC
NC
VDDQ
U
Pin Definitions
Name
A0, A1, A
TQFP
BGA
I/O
Input-
Description
Address Inputs used to select one of the 128K address lo-
37,36,32,33,34, P4,N4,A2,C2,
35,44,45,46,47, R2,A3,B3,C3, Synchronous cations. Sampled at the rising edge of the CLK. A[1:0] are fed
48,49,50,81,82, T3,T4,A5,B5,
to the two-bit burst counter.
99,100
93,94,95,96
88
C5,T5,A6,C6,
R6
L5,G5,G3,L3
Input-
Byte Write Inputs, active LOW. Qualified with WE to conduct
BW[A:D]
WE
Synchronous writes to the SRAM. Sampled on the rising edge of CLK.
H4
Input-
Write Enable Input, active LOW. Sampled on the rising edge
Synchronous of CLK if CEN is active LOW. This signal must be asserted LOW
to initiate a write sequence.
85
B4
Input-
Advance/Load Input. Used to advance the on-chip address
ADV/LD
Synchronous counter or load a new address. When HIGH (and CEN is as-
serted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an ac-
cess. After being deselected, ADV/LD should be driven LOW in
order to load a new address.
CLK
89
98
97
K4
E4
B2
Input-Clock Clock Input. Used to capture all synchronous inputs to the de-
vice. CLK is qualified with CEN. CLK is only recognized if CEN
is active LOW.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge
CE1
CE2
Synchronous of CLK. Used in conjunction with CE2, and CE3 to select/dese-
lect the device.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge
Synchronous ofCLK. Used inconjunction with CE1 andCE3 toselect/deselect
the device.
Document #: 38-05210 Rev. *B
Page 3 of 15
CY7C1351F
Pin Definitions
Name
TQFP
BGA
I/O
Description
92
B6
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge
CE3
Synchronous of CLK. Used in conjunctionwith CE1 andCE2 to select/deselect
the device.
86
F4
Input-
Output Enable, asynchronous input, active LOW. Combined
OE
Asynchronous with the synchronous logic block inside the device to control the
direction of the I/O pins. When LOW, the I/O pins are allowed
to behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when
emerging from a deselected state, when the device has been
deselected.
87
64
M4
T7
Input-
Clock Enable Input, active LOW. When asserted LOW the
CEN
ZZ
Synchronous Clock signal is recognized by the SRAM. When deasserted
HIGH the Clock signal is masked. Since deasserting CEN does
not deselect the device, CEN can be used to extend the previ-
ous cycle when required.
Input-
ZZ “sleep” Input. This active HIGH input places the device in
Asynchronous a non-time critical “sleep” condition with data integrity pre-
served. During normal operation, this pin can be connected to
Vss or left floating.
DQs
52,53,56,57,58, K6,L6,M6,N6,
I/O-
Bidirectional Data I/O Lines. As inputs, they feed into an
59,62,63,68,69, K7,L7,N7,P7, Synchronous on-chip data register that is triggered by the rising edge of CLK.
72,73,74,75,78, E6,F6,G6,H6,
79,2,3,6,7,8,9, D7,E7,G7,H7,
12,13,18,19,22, D1,E1,G1,H1,
23,24,25,28,29 E2,F2,G2,H2,
K1,L1,N1,P1,
As outputs, they deliver the data contained in the memory loca-
tion specified by address during the clock rise of the read cycle.
The direction of the pins is controlled by OE and the internal
control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQs and DQP[A:D] are placed in a
three-state condition. The outputs are automatically three-stat-
ed during the data portion of a write sequence, during the first
clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
K2,L2,M2,N2
DQP[A:D]
MODE
51,80,1,30
31
P6,D6,D2,P2
R3
I/O-
BidirectionalDataParityI/OLines. Functionally, thesesignals
Synchronous are identical to DQs. During write sequences, DQP[A:D] is con-
trolled by BW[A:D] correspondingly.
Input
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence.
Strap Pin
VDD
15,41,65,91
J2,C4,J4,R4, Power Supply Power supply inputs to the core of the device.
J6
VDDQ
4,11,20,27,54, A1,F1,J1,M1, I/O Power Sup- Power supply for the I/O circuitry.
61,70,77
U1,A7,F7,J7,
M7,U7
ply
VSS
NC
5,10,17,21,26, D3,E3,F3,H3,
Ground
Ground for the device.
40,55,60,67,71, J3,K3,M3,N3,
76,90,
P3,D5,E5,F5,
H5,J5,K5,M5,
N5,P5
14,16,38,39,42, B1,C1,R1,T1,
–
No Connects. Not Internally connected to the die.
43,66,83,84
T2,U2,U3,A4,
D4,G4,L4,U4,
U5,T6,U6,B7,
C7,R5,R7,T7
Document #: 38-05210 Rev. *B
Page 4 of 15
CY7C1351F
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Functional Overview
The CY7C1351F is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (tCDV) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW[A:D] can be used to
conduct byte write operations.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically three-stated regardless of the state of the OE
input signal. This allows the external logic to present the data
on DQs and DQP[A:D]
.
On the next clock rise the data presented to DQs and DQP[A:D]
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
The data written during the Write operation is controlled by
BW[A:D] signals. The CY7C1351F provides byte write
capability that is described in the truth table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera-
tions.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Because the CY7C1351F is a common I/O device, data should
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQP[A:D] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs and
DQP[A:D].are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1351F has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BW[A:D] inputs must be driven in each cycle of the burst write,
in order to write the correct bytes of data.
Burst Read Accesses
The CY7C1351F has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enable inputs or WE. WE is latched at the
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for
the duration of tZZREC after the ZZ input returns LOW.
Document #: 38-05210 Rev. *B
Page 5 of 15
CY7C1351F
Interleaved Burst Address Table (MODE =
Linear Burst Address Table (MODE = GND)
Floating or VDD
)
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Address
A1, A0
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
Description
Snooze mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
Min.
Max.
40
2tCYC
Unit
mA
ns
tZZREC
tZZI
tRZZI
ZZ recovery time
ZZ active to snooze current
ZZ inactive to exit snooze current
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
2tCYC
0
ns
ns
ns
2tCYC
Truth Table[2, 3, 4, 5, 6, 7, 8 ]
Address
Operation
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
Used
None
CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
H
X
X
X
L
X
X
L
X
H
X
H
X
X
L
L
L
L
L
L
L
L
L
H
L
X
X
X
X
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L->H Three-state
L->H Three-state
L->H Three-state
L->H Three-state
L->H Data Out (Q)
None
None
None
External
READ Cycle
(Begin Burst)
READ Cycle
Next
External
Next
X
L
X
H
X
H
X
H
X
X
X
X
L
L
L
L
L
L
L
L
L
H
H
L
X
H
X
L
X
X
X
L
L
H
H
X
X
X
X
X
X
L
L
L
L
L
L
L
H
X
L->H Data Out (Q)
L->H Three-state
L->H Three-state
L->H Data In (D)
L->H Data In (D)
L->H Three-state
L->H Three-state
(Continue Burst)
NOP/DUMMY READ
(Begin Burst)
DUMMY READ
(Continue Burst)
X
L
X
L
H
L
WRITE Cycle
External
Next
(Begin Burst)
WRITE Cycle
X
L
X
L
H
L
X
L
L
(Continue Burst)
NOP/WRITE ABORT
None
H
H
X
X
(Begin Burst)
WRITE ABORT
(Continue Burst)
Next
X
X
X
X
X
X
H
X
X
X
X
X
IGNORE CLOCK
Current
None
L->H
X
–
EDGE (Stall)
SNOOZE MODE
Three-state
Notes:
2. X = Don’t Care.” H= Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BW
, and WE. See truth table for Read/Write.
[A:D]
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQs and DQP
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
[A:D]
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
= Three-state when
[A:D]
OE is inactive or when the device is deselected, and DQs and DQP
= data when OE is active.
[A:D]
Document #: 38-05210 Rev. *B
Page 6 of 15
CY7C1351F
Partial Truth Table for Read/Write [2, 3, 9]
Function
Read
BWA
X
BWB
X
BWC
X
BWD
X
WE
H
Read
H
L
L
L
L
L
L
X
H
L
H
H
H
L
X
H
H
L
H
H
L
X
H
H
H
L
X
H
H
H
H
L
Write – No bytes written
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Byte C– (DQC and DQPC)
Write Byte D– (DQD and DQPD)
H
L
Write All Bytes
L
Note:
9. Table only lists a partial listing of the byte write combinatios. Any combination of BW
is valid. Appropriate write will be done based on which byte write is active.
[A:D]
Document #: 38-05210 Rev. *B
Page 7 of 15
CY7C1351F
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND ...... –0.5V to +4.6V
Range Temperature (TA)
VDD
VDDQ
DC Voltage Applied to Outputs
Com’l
Ind’l
0°C to +70°C
−40°C to +85°C
3.3V - 5%/+10% 2.5V - 5% to
in three-state....................................... –0.5V to VDDQ + 0.5V
VDD
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range [10,11]
Parameter
VDD
VDDQ
VOH
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
2.375
2.4
Max.
3.6
VDD
Unit
V
V
V
V
V
V
V
V
Output HIGH Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
DDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
DDQ = 2.5V
2.0
VOL
VIH
VIL
IX
Output LOW Voltage
0.4
0.4
VDD + 0.3V
VDD + 0.3V
0.8
V
Input HIGH Voltage
Input HIGH Voltage
Input LOW Voltage[10]
Input LOW Voltage[10]
2.0
1.7
–0.3
–0.3
−5
V
VDDQ = 3.3V
VDDQ = 2.5V
V
V
µA
0.7
5
Input Load Current (except GND ≤ VI ≤ VDDQ
ZZ and MODE)
Input Current of MODE
Input = VSS
Input = VDD
Input = VSS
–30
–5
µA
µA
µA
5
Input Current of ZZ
Input = VDD
GND ≤ VI ≤ VDD, Output Disabled
30
5
µA
µA
IOZ
IOS
IDD
Output Leakage Current
–5
Output Short Circuit Current VDD = Max., VOUT = GND
VDD Operating Supply Cur- VDD = Max., IOUT = 0 mA,
–300
225
220
205
195
90
85
80
60
40
µA
7.5-ns cycle, 133 MHz
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
15-ns cycle, 66 MHz
mA
mA
mA
mA
mA
mA
mA
mA
mA
rent
f = fMAX= 1/tCYC
ISB1
Automatic CE Power-down VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz
Current—TTL Inputs
V
IN ≥ VIH or VIN ≤ VIL, f = fMAX
,
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
15-ns cycle, 66 MHz
inputs switching
ISB2
Automatic CE Power-down VDD = Max, Device Deselected, All speeds
Current—CMOS Inputs IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
V
Shaded areas contain advance information.
Notes:
10. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2).
11. T
: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
Power-up
Document #: 38-05210 Rev. *B
Page 8 of 15
CY7C1351F
Electrical Characteristics Over the Operating Range (continued)[10,11]
Parameter
ISB3
Description
Test Conditions
Min.
Max.
75
70
65
45
Unit
mA
mA
mA
mA
mA
Automatic CE Power-down VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz
Current—CMOS Inputs
VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
15-ns cycle, 66 MHz
f = fMAX, inputs switching
ISB4
Automatic CE Power-down VDD = Max, Device Deselected, All speeds
Current—TTL Inputs IN ≥ VDD – 0.3V or VIN ≤ 0.3V, f =
0, inputs static
45
V
Thermal Resistance[12]
TQFP
BGA
Parameters
Description
Test Conditions
Package
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard test
41.83
47.63
°C/W
(Junction to Ambient) methods and procedures for measur-
ing thermal impedance, per EIA /
Thermal Resistance
ΘJC
9.99
11.71
°C/W
JESD51.
(Junction to Case)
Capacitance[12]
BGA
TQFP
Parameter
Description
Input Capacitance
Clock Input Capacitance
I/O Capacitance
Test Conditions
Package
Package
Unit
CIN
TA = 25°C, f = 1 MHz,
5
5
5
5
5
7
pF
pF
pF
V
DD = 3.3V
CCLOCK
CI/O
V
DDQ=3.3V
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDD
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDD
90%
10%
Z = 50Ω
0
10%
L
GND
≤ 1ns
5 pF
R =1538Ω
≤ 1ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
12. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05210 Rev. *B
Page 9 of 15
CY7C1351F
Switching Characteristics Over the Operating Range[17, 18]
133 MHz 117 MHz 100 MHz
66 MHz
Parameter
tPOWER
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VDD(Typical) to the first Access[13]
1
1
1
1
ms
Clock
tCYC
tCH
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
2.5
2.5
8.5
3.0
3.0
10
4.0
4.0
15
5.0
5.0
ns
ns
ns
tCL
Output Times
tCDV
tDOH
tCLZ
tCHZ
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[14, 15, 16]
6.5
7.5
8.0
11.0 ns
ns
2.0
0
2.0
0
2.0
0
2.0
0
ns
Clock to High-Z14, 15, 16]
3.5
3.5
3.5
3.5
3.5
3.5
5.0 ns
6.0 ns
ns
tOEV
OE LOW to Output Valid
OE LOW to Output Low-Z[14, 15, 16]
OE HIGH to Output High-Z[14, 15, 16]
tOELZ
tOEHZ
Set-up Times
tAS
tALS
tWES
tCENS
tDS
tCES
0
0
0
0
3.5
3.5
3.5
6.0 ns
Address Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ADV/LD Set-up Before CLK Rise
WE, BW[A:D] Set-Up Before CLK Rise
CEN Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
Hold Times
tAH
tALH
tWEH
tCENH
tDH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ADV/LD Hold after CLK Rise
WE, BW[A:D] Hold After CLK Rise
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
tCEH
Chip Enable Hold After CLK Rise
Shaded areas contain advance information.
Notes:
13. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
14. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
15. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions
16. This parameter is sampled and not 100% tested.
17. Timing reference level is 1.5V when V
=3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
18. Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
Document #: 38-05210 Rev. *B
Page 10 of 15
CY7C1351F
Switching Waveforms
Read/Write Waveforms[19, 20, 21]
t
1
2
3
4
5
6
7
8
9
10
CYC
t
CLK
CEN
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CE
ADV/LD
WE
BW[A:D]
A1
A2
A4
A3
t
A5
A6
A7
ADDRESS
DQ
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
DON’T CARE
4
UNDEFINED
6
NOP, STALL and DESELECT Cycles[19, 20, 22]
1
2
3
5
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW[A:D]
ADDRESS
A1
A2
A3
A4
A5
t
CHZ
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
DOH
DQ
t
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
Document #: 38-05210 Rev. *B
Page 11 of 15
CY7C1351F
Switching Waveforms
ZZ Mode Timing[23,24]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Package Type
133
CY7C1351F-133AC
CY7C1351F-133BGC
CY7C1351F-133AI
CY7C1351F-133BGI
CY7C1351F-117AC
CY7C1351F-117BGC
CY7C1351F-117AI
CY7C1351F-117BGI
CY7C1351F-100AC
CY7C1351F-100BGC
CY7C1351F-100AI
CY7C1351F-100BGI
CY7C1351F-66AC
CY7C1351F-66BGC
CY7C1351F-66AI
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Ball BGA 14 x 22 x 2.4 mm
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Ball BGA 14 x 22 x 2.4 mm
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Ball BGA 14 x 22 x 2.4 mm
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Ball BGA 14 x 22 x 2.4 mm
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Ball BGA 14 x 22 x 2.4 mm
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Ball BGA 14 x 22 x 2.4 mm
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Ball BGA 14 x 22 x 2.4 mm
Commercial
Industrial
117
100
66
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Ball BGA 14 x 22 x 2.4 mm
CY7C1351F-66BGI
Shaded areas contain advance information. Please contain your local sales representative for more information on ordering these parts.
Notes:
For this waveform ZZ is tied low.
19.
20. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
21. Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional.
22. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
23. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
24. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05210 Rev. *B
Page 12 of 15
CY7C1351F
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05210 Rev. *B
Page 13 of 15
CY7C1351F
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Intel and Pentium are registered trademarks of Intel Corporation. ZBT is a trademark of Integrated Device Technology. NoBL and
No Bus Latency are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders. All product and company names mentioned in this document may be the trademarks of
their respective holders.
Document #: 38-05210 Rev. *B
Page 14 of 15
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1351F
Document History Page
Document Title: CY7C1351F 4-Mb (128K x 36) Flow-through SRAM with NoBL™ Architecture
Document Number: 38-05210
Orig. of
REV.
**
*A
ECN NO. Issue Date Change
Description of Change
119833
123846
200664
01/07/03
01/18/03
See ECN
HGK
AJH
SWI
New Data Sheet
Added power-up requirements to AC test loads and waveforms information
Final Data Sheet
*B
Document #: 38-05210 Rev. *B
Page 15 of 15
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