CY7C1354C, CY7C1356C

9-Mbit (256 K × 36/512 K × 18)

Pipelined SRAM with NoBL™ Architecture

9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture

Features

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Functional Description

The CY7C1354C and CY7C1356C

are 3.3 V, 256 K x 36 and

512K x 18 synchronous pipelined burst SRAMs with No Bus

Latency™ (NoBL logic, respectively. They are designed to

support unlimited true back-to-back read/write operations with

no wait states. The CY7C1354C and CY7C1356C are

equipped with the advanced (NoBL) logic required to enable

consecutive read/write operations with data being transferred

on every clock cycle. This feature greatly improves the

throughput of data in systems that require frequent write/read

transitions. The CY7C1354C and CY7C1356C are pin

compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the clock enable (CEN) signal, which

when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the byte write selects

(BW

a

–BW

d

for CY7C1354C and BW

a

–BW

b

for CY7C1356C)

and a write enable (WE) input. All writes are conducted with

on-chip synchronous self-timed write circuitry.

Three synchronous chip enables (CE

1

, CE

2

, CE

3

) and an

asynchronous output enable (OE) provide for easy bank

selection and output tristate control. To avoid bus contention,

the output drivers are synchronously tristated during the data

portion of a write sequence.

Pin-compatible and functionally equivalent to ZBT

Supports 250 MHz bus operations with zero wait states

❐

Available speed grades are 250, 200, and 166 MHz

Internally self-timed output buffer control to eliminate the

need to use asynchronous OE

Fully registered (inputs and outputs) for pipelined

operation

Byte write capability

Single 3.3 V power supply (V

DD

)

3.3 V or 2.5 V I/O power supply (V

DDQ

)

Fast clock-to-output times

❐

2.8 ns (for 250 MHz device)

Clock enable (CEN) pin to suspend operation

Synchronous self-timed writes

Available in Pb-free 100-pin TQFP package, Pb-free, and

non Pb-free 119-ball BGA package and 165-ball FBGA

package

IEEE 1149.1 JTAG-compatible boundary scan

Burst capability – linear or interleaved burst order

“ZZ” sleep mode option and stop clock option

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Logic Block Diagram – CY7C1354C (256 K × 36)

A0, A1, A

MODE

CLK

CEN

ADDRESS

REGISTER 0

A1

A1'

D1

Q1

A0

A0'

BURST

D0

Q0

LOGIC

ADV/LD

C

WRITE ADDRESS

REGISTER 1

WRITE ADDRESS

REGISTER 2

C

ADV/LD

BW

a

BW

b

BW

c

BW

d

WE

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

WRITE

DRIVERS

MEMORY

ARRAY

S

E

N

S

E

A

M

P

S

O

U

T

P

U

T

R

E

G

I

S

T

E

R

S

D

A

T

A

S

T

E

E

R

I

N

G

O

U

T

P

U

T

B

U

F

F

E

R

S

E

DQ s

DQ P

a

DQ P

b

DQ P

c

DQ P

d

E

INPUT

REGISTER 1

E

INPUT

REGISTER 0

E

OE

CE1

CE2

CE3

ZZ

READ LOGIC

SLEEP

CONTROL

Note

1. For best-practices recommendations, refer to the Cypress application note

System Design Guidelines

www.cypress.com.

Cypress Semiconductor Corporation

Document Number: 38-05538 Rev. *K

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Revised March 2, 2011