CY7C1354C-200AXC [CYPRESS]
9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL? Architecture; 9兆位（ 256千×五百十二分之三十六K＆times 18 ）流水线SRAM与NOBL ™架构
| 元器件型号： | CY7C1354C-200AXC |
| 生产厂家： | 
CYPRESS SEMICONDUCTOR
|
| 描述和应用： | 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL? Architecture |
| PDF文件： | 总32页 (文件大小：1078K) |
| 下载文档： | 下载PDF数据表文档文件 |
| 型号参数：CY7C1354C-200AXC参数 | |
| 是否无铅 | 不含铅 |
| 是否Rohs认证 | 符合 |
| 生命周期 | Obsolete |
| IHS 制造商 | CYPRESS SEMICONDUCTOR CORP |
| 零件包装代码 | QFP |
| 包装说明 | LQFP, QFP100,.63X.87 |
| 针数 | 100 |
| Reach Compliance Code | compliant |
| ECCN代码 | 3A991.B.2.A |
| HTS代码 | 8542.32.00.41 |
| Factory Lead Time | 1 week |
| 风险等级 | 5.17 |
| Is Samacsys | N |
| 最长访问时间 | 3.2 ns |
| 其他特性 | PIPELINED ARCHITECTURE |
| 最大时钟频率 (fCLK) | 200 MHz |
| I/O 类型 | COMMON |
| JESD-30 代码 | R-PQFP-G100 |
| JESD-609代码 | e3 |
| 长度 | 20 mm |
| 内存密度 | 9437184 bit |
| 内存集成电路类型 | ZBT SRAM |
| 内存宽度 | 36 |
| 湿度敏感等级 | 3 |
| 功能数量 | 1 |
| 端子数量 | 100 |
| 字数 | 262144 words |
| 字数代码 | 256000 |
| 工作模式 | SYNCHRONOUS |
| 最高工作温度 | 70 °C |
| 最低工作温度 | |
| 组织 | 256KX36 |
| 输出特性 | 3-STATE |
| 封装主体材料 | PLASTIC/EPOXY |
| 封装代码 | LQFP |
| 封装等效代码 | QFP100,.63X.87 |
| 封装形状 | RECTANGULAR |
| 封装形式 | FLATPACK, LOW PROFILE |
| 并行/串行 | PARALLEL |
| 峰值回流温度（摄氏度） | 260 |
| 电源 | 2.5/3.3,3.3 V |
| 认证状态 | Not Qualified |
| 座面最大高度 | 1.6 mm |
| 最大待机电流 | 0.04 A |
| 最小待机电流 | 3.14 V |
| 子类别 | SRAMs |
| 最大压摆率 | 0.22 mA |
| 最大供电电压 (Vsup) | 3.6 V |
| 最小供电电压 (Vsup) | 3.135 V |
| 标称供电电压 (Vsup) | 3.3 V |
| 表面贴装 | YES |
| 技术 | CMOS |
| 温度等级 | COMMERCIAL |
| 端子面层 | Matte Tin (Sn) |
| 端子形式 | GULL WING |
| 端子节距 | 0.65 mm |
| 端子位置 | QUAD |
| 处于峰值回流温度下的最长时间 | 20 |
| 宽度 | 14 mm |
| Base Number Matches | 1 |
MAX34334CSE前5页PDF页面详情预览
CY7C1354C, CY7C1356C
9-Mbit (256 K × 36/512 K × 18)
Pipelined SRAM with NoBL™ Architecture
9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture
Features
■
■
Functional Description
The CY7C1354C and CY7C1356C
[1]
are 3.3 V, 256 K x 36 and
512K x 18 synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL logic, respectively. They are designed to
support unlimited true back-to-back read/write operations with
no wait states. The CY7C1354C and CY7C1356C are
equipped with the advanced (NoBL) logic required to enable
consecutive read/write operations with data being transferred
on every clock cycle. This feature greatly improves the
throughput of data in systems that require frequent write/read
transitions. The CY7C1354C and CY7C1356C are pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the clock enable (CEN) signal, which
when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the byte write selects
(BW
a
–BW
d
for CY7C1354C and BW
a
–BW
b
for CY7C1356C)
and a write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention,
the output drivers are synchronously tristated during the data
portion of a write sequence.
Pin-compatible and functionally equivalent to ZBT
Supports 250 MHz bus operations with zero wait states
❐
Available speed grades are 250, 200, and 166 MHz
Internally self-timed output buffer control to eliminate the
need to use asynchronous OE
Fully registered (inputs and outputs) for pipelined
operation
Byte write capability
Single 3.3 V power supply (V
DD
)
3.3 V or 2.5 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
2.8 ns (for 250 MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in Pb-free 100-pin TQFP package, Pb-free, and
non Pb-free 119-ball BGA package and 165-ball FBGA
package
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
■
■
■
■
■
■
■
■
■
■
■
■
Logic Block Diagram – CY7C1354C (256 K × 36)
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQ s
DQ P
a
DQ P
b
DQ P
c
DQ P
d
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Note
1. For best-practices recommendations, refer to the Cypress application note
System Design Guidelines
on
www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05538 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 2, 2011
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CY7C1354C, CY7C1356C
Logic Block Diagram – CY7C1356C (512 K × 18)
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
a
BW
b
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQ s
DQ P
a
DQ P
b
E
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Document Number: 38-05538 Rev. *K
Page 2 of 32
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CY7C1354C, CY7C1356C
Contents
Selection Guide ................................................................ 4
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Burst Read Accesses .................................................. 8
Single Write Accesses ................................................. 8
Burst Write Accesses .................................................. 9
Sleep Mode ................................................................. 9
Partial Write Cycle Description ..................................... 10
Truth Table ...................................................................... 10
Partial Write Cycle Description ..................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
TAP Controller State Diagram ....................................... 12
Test Access Port (TAP) ............................................. 12
TAP Controller Block Diagram ...................................... 12
PERFORMING A TAP RESET .................................. 12
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 13
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 14
3.3 V TAP AC Test Conditions ....................................... 15
3.3 V TAP AC Output Load Equivalent ......................... 15
2.5 V TAP AC Test Conditions ....................................... 15
2.5 V TAP AC Output Load Equivalent ......................... 15
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 15
Identification Register Definitions ................................ 15
Scan Register Sizes ....................................................... 16
Identification Codes ....................................................... 16
Boundary Scan Exit Order (256 K × 36) ........................ 17
Boundary Scan Exit Order (512 K × 18) ........................ 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Neutron Soft Error Immunity ......................................... 19
Electrical Characteristics ............................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC Solutions ......................................................... 32
Document Number: 38-05538 Rev. *K
Page 3 of 32
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CY7C1354C, CY7C1356C
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
250 MHz
2.8
250
40
200 MHz
3.2
220
40
166 MHz
3.5
180
40
Unit
ns
mA
mA
Pin Configurations
Figure 1. 100-pin TQFP
A
A
CE
1
CE
2
BWd
BWc
BWb
BWa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
NC(18)
A
A
A
CE
1
CE
2
NC
NC
BWb
BWa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
NC(18)
A
NC
DQPb
NC
DQb
NC
DQb
V
DDQ
V
DDQ
V
SS
V
SS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
V
SS
V
SS
V
DDQ
V
DDQ
DQb
DQb
DQb
DQb
NC
V
SS
V
DD
NC
V
DD
NC
V
SS
ZZ
DQb
DQa
DQa
DQb
V
DDQ
V
DDQ
V
SS
V
SS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
V
SS
V
SS
V
DDQ
V
DDQ
NC
DQa
DQa
NC
DQPa
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQPc
DQc
DQc
V
DDQ
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DDQ
DQd
DQd
DQPd
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
CY7C1354C
(256 K × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1356C
(512 K × 18)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC(288)
NC(144)
MODE
A
A
A
A
A
1
A
0
MODE
A
A
A
A
A
1
A
0
NC(36)
NC(288)
NC(144)
NC(72)
NC(72)
NC(36)
V
SS
V
DD
A
A
A
A
A
A
A
Document Number: 38-05538 Rev. *K
V
SS
V
DD
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 4 of 32
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CY7C1354C, CY7C1356C
Figure 2. 119-ball BGA Pinout
CY7C1354C (256 K × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/576M
NC/1G
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC/144M
NC
V
DDQ
2
A
CE
2
A
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
A
NC/72M
TMS
3
A
A
A
V
SS
V
SS
V
SS
BW
c
V
SS
NC
V
SS
BW
d
V
SS
V
SS
V
SS
MODE
A
TDI
4
NC/18M
ADV/LD
V
DD
NC
CE
1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
NC
A
TDO
6
A
CE
3
A
DQP
b
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
DQP
a
A
NC/36M
NC
7
V
DDQ
NC
NC
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC/288M
ZZ
V
DDQ
CY7C1356C (512 K x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/576M
NC/1G
DQ
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC/144M
NC/72M
V
DDQ
2
A
CE
2
A
NC
DQ
b
NC
DQ
b
NC
V
DD
DQ
b
NC
DQ
b
NC
DQP
b
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
TDI
4
NC/18M
ADV/LD
V
DD
NC
CE
1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
NC/36M
TCK
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
NC
A
TDO
6
A
CE
3
A
DQP
a
NC
DQ
a
NC
DQ
a
V
DD
NC
DQ
a
NC
DQ
a
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQ
a
V
DDQ
DQ
a
NC
V
DDQ
DQ
a
NC
V
DDQ
NC
DQ
a
NC/288M
ZZ
V
DDQ
Document Number: 38-05538 Rev. *K
Page 5 of 32
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