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CY7C1354CV25-167AXC 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
Prototype PCB
Part No.:   CY7C1354CV25-167AXC
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Description:   9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
File Size :   338 K    
Page : 25 Pages
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Partial Write Cycle Description
[2, 3, 4, 9]
Function (CY7C1354CV25)
Read
Write –No bytes written
Write Byte a– (DQ
a
and DQP
a)
Write Byte b – (DQ
b
and DQP
b)
Write Bytes b, a
Write Byte c – (DQ
c
and DQP
c)
Write Bytes c, a
Write Bytes c, b
Write Bytes c, b, a
Write Byte d – (DQ
d
and DQP
d)
Write Bytes d, a
Write Bytes d, b
Write Bytes d, b, a
Write Bytes d, c
Write Bytes d, c, a
Write Bytes d, c, b
Write All Bytes
WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BW
d
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
BW
c
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
CY7C1354CV25
CY7C1356CV25
BW
b
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
BW
a
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Partial Write Cycle Description
[2, 3, 4, 9]
Function (CY7C1356CV25)
Read
Write – No Bytes Written
Write Byte a
(DQ
a
and DQP
a)
Write Byte b – (DQ
b
and DQP
b)
Write Both Bytes
WE
H
L
L
L
L
BW
b
x
H
H
L
L
BW
a
x
H
L
H
L
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354CV25/CY7C1356CV25 incorporates a serial
boundary scan test access port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
part operates in accordance with IEEE Standard 1149.1-1900,
but doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V I/O logic levels.
The CY7C1354CV25/CY7C1356CV25 contains a TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(V
SS
) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to V
DD
through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BW
X
is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05537 Rev. *B
Page 9 of 25
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