CY7C1354V25-166BAC [CYPRESS]
ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA119, BGA-119;型号: | CY7C1354V25-166BAC |
厂家: | CYPRESS |
描述: | ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA119, BGA-119 静态存储器 内存集成电路 |
文件: | 总25页 (文件大小:269K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
5
CY7C1354V25
CY7C1356V25
PRELIMINARY
256Kx36/512Kx18 Pipelined SRAM with NoBL™ Architecture
tively designed specifically to support unlimited true
Features
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1354V25/CY7C1356V25 is equipped
with the advanced No Bus Latency™ (NoBL ) logic required
to enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically im-
proves the throughput of data through the SRAM, especially in
systems that require frequent Write/Read transitions.The
CY7C1354V25/CY7C1356V25 is pin compatible and function-
ally equivalent to ZBT devices.
Pin compatible and functionally equivalent to ZBT
• Supports 200-MHz bus operations with zero wait states
— Data is transferred on every clock
•
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully Registered (inputs and outputs) for pipelined op-
eration
• Byte Write capability
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
3.2 ns (200-MHz device).
• Common I/O architecture
• Single 2.5V power supply
• Fast clock-to-output times
— 3.2 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.2 ns (for 133-MHz device)
Write operations are controlled by the Byte Write Selects
(BWSa-BWSd for CY7C1354V25 and BWSa-BWSb for
CY7C1356V25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
— 5.0 ns (for 100-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP & 119 BGA Packages
• Burst Capability—linear or interleaved burst order
Three synchronous Chip Enables (CE , CE , CE ) and an
1
2
3
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Functional Description
The CY7C1354V25 and CY7C1356V25 are 2.5V, 256K by 36
and 512K by 18 Synchronous-Pipelined Burst SRAMs respec-
Logic Block Diagram
D
CLK
Data-In REG.
CE
Q
ADV/LD
Ax
CEN
CE
CONTROL
and WRITE
LOGIC
256KX36/
512KX18
MEMORY
ARRAY
1
CE
2
DQx
DPx
CE
3
WE
CY7C1356
CY7C1354
BWSx
X = 17:0
AX
X = 18:0
Mode
OE
DQX X = a, b, c, d X = a, b
X = a, b, c, d
X = a, b
DPX
X = a, b, c, d X = a, b
BWSX
.
Selection Guide
7C1354V25-200 7C1354V25-166 7C1354V25-133 7C1354V25-100
7C1356V25-200 7C1356V25-166 7C1356V25-133 7C1356V25-100
Maximum Access Time (ns)
3.2
475
10
3.5
450
10
4.0
370
10
5.0
300
10
Maximum Operating Current (mA)
Com’l
Maximum CMOS Standby Current (mA) Com’l
Shaded areas contain advance information.
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 5, 1999
CY7C1354V25
CY7C1356V25
PRELIMINARY
Pin Configurations
100-Pin TQFP Packages
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DPc
DQc
DQc
1
2
3
4
5
6
7
8
DPb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb
DQb
V
V
VDDQ
VSS
NC
DDQ
VDDQ
VSS
V
SS
V
SS
DQc
DQc
NC
NC
DQb
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
DPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
DQc
DQc
DQb
9
9
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
DDQ
DQb
DQb
DQc
DQc
VDD
V
DD
CY7C1354V25
(256K x 36)
V
DD
VDD
VDD
VSS
V
CY7C1356V25
(512K x 18)
DD
Vdd
VDD
VSS
V
DD
V
DD
V
SS
V
SS
DQb
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
DQd
DQa
DQa
DQb
DDQ
DQd
V
V
DDQ
VDDQ
VSS
V
SS
V
SS
DQb
DQb
DPb
NC
DQd
DQd
DQd
DQd
DQa
DQa
DQa
DQa
VSS
NC
V
VSS
VDDQ
NC
NC
NC
V
SS
SS
V
DDQ
NC
NC
NC
V
DDQ
VDDQ
DQd
DQd
DPd
DQa
DQa
DPa
2
CY7C1354V25
CY7C1356V25
PRELIMINARY
Pin Configurations (continued)
119-Ball Bump BGA
CY7C1356 - 7 x 17 BGA
1
3
2
4
5
A
A
A
6
7
A
A
A
A
A
V
DDQ
V
A
NC
DDQ
B
C
D
E
F
CE
A
NC
NC
ADV/LD
NC
NC
CE
A
2
3
V
DD
NC
DQb
NC
NC
DQb
NC
V
SS
V
NC
DQa
NC
SS
V
DQa
V
V
CE1
SS
SS
SS
V
DQa
V
V
OE
A
DDQ
SS
SS
DDQ
DQa
NC
DQb
NC
NC
G
H
J
NC
DQb
BWSb
V
V
DQa
V
V
WE
SS
SS
V
V
V
V
DDQ
V
V
DD
DD
DD
DD
DDQ
DD
V
K
L
M
CLK
NC
NC
V
SS
DQb
NC
NC
DQa
NC
DQa
SS
V
DQb
SS
BWSa
NC
V
V
V
DDQ
V
DQb
NC
SS
CEN
A1
SS
DDQ
V
N
P
R
T
DQb
NC
V
DQa
NC
SS
SS
DPb
A
V
A0
DPa
NC
V
NC
A
SS
SS
NC
NC
MODE
A
V
V
DD
SS
A
A
A
NC
NC
U
V
TMS
NC
V
DDQ
TDI
TCK
TDO
DDQ
CY7C1354 - 7 x 17 BGA
1
3
2
4
5
A
A
A
6
7
A
B
C
D
E
F
A
V
DDQ
A
A
A
V
A
NC
DDQ
CE
NC
NC
ADV/LD
NC
CE
2
3
A
A
V
NC
DD
DPc
DQb
DQb
DQc
DQc
V
SS
V
NC
DPb
DQb
DQb
DQb
DQb
SS
V
V
V
CE1
DQc
DQc
DQc
DQc
SS
SS
SS
V
V
V
OE
A
DDQ
SS
DDQ
DQc
DQc
BWSb
G
H
J
BWSc
V
DQb
DQb
V
WE
SS
SS
DD
V
V
V
V
V
V
V
DD
DD
DD
DDQ
DDQ
DD
DQd
DQd
V
DQa
K
L
CLK
NC
V
DQd
DQd
DQd
DQd
DQa
DQa
SS
SS
BWSd
BWSa
DQa
DQa
DQa
DQa
V
M
N
P
R
T
V
V
V
SS
CEN
A1
SS
DDQ
DDQ
V
DQa
DQd
DQd
NC
V
SS
SS
DPd
A
V
A0
DPa
NC
V
SS
SS
MODE
A
A
V
V
DD
SS
A
NC
A
NC
NC
NC
NC
U
V
TMS
V
TDI
TCK
TDO
DDQ
DDQ
3
CY7C1354V25
CY7C1356V25
PRELIMINARY
Pin Definitions (100-Pin TQFP)
x18 Pin Location x36 Pin Location Name
37, 36, 32–35, 37, 36, 32–35, A0
44–50, 80–83, 99, 44–50, 81-83, 99, A1
I/O Type
Description
Address Inputs used to select one of the 266,144 ad-
Input-
Synchronous dress locations. Sampled at the rising edge of the CLK.
100
100
A
93, 94
93, 94, 95, 96
BWSa
BWSb
BWSc
BWSd
Input- Byte Write Select Inputs, active LOW. Qualified with WE
Synchronous to conduct writes to the SRAM. Sampled on the rising
edge of CLK. BWSa controls DQa and DPa, BWSb con-
trols DQband DPb, BWSc controls DQc and DPc, BWSd
controls DQd and DPd.
88
85
88
85
WE
Input-
Write Enable Input, active LOW. Sampled on the rising
Synchronous edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
ADV/LD Input-
Advance/Load Input used to advance the on-chip ad-
Synchronous dress counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is ad-
vanced. When LOW, a new address can be loaded into
the device foran access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
89
98
97
92
86
89
98
97
92
86
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only rec-
ognized if CEN is active LOW.
CE
CE
CE
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising
1
2
3
Synchronous edge of CLK. Used in conjunction with CE and CE to
2
3
select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising
Synchronous edge of CLK. Used in conjunction with CE and CE to
Input-
1
3
select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising
Synchronous edge of CLK. Used in conjunction with CE and CE to
Input-
1
2
select/deselect the device.
OE
Input-
Output Enable, active LOW. Combined with the synchro-
Asynchronous nous logic block inside the device to control the direction
of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence , during the
first clock when emerging from a deselected state and
when the device has been deselected.
87
87
CEN
Input-
Clock Enable Input, active LOW. When asserted LOW
Synchronous the clock signal is recognized by the SRAM. When deas-
serted HIGH the clock signal is masked. Since deassert-
ing CEN does not deselect the device, CEN can be used
to extend the previous cycle when required.
(a)58, 59, 62, 63,
68, 69, 72–74
(b)8, 9, 12, 13, 18, (b)68, 69, 72–75,
19, 22–24
(a)52, 53, 56–59,
62, 63,
DQa
DQb
DQc
DQd
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an
Synchronous on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
78, 79
memory location specified by A
during the previous
[17:0]
(c)2, 3, 6–9, 12, 13,
(d)18, 19, 22–25,
28, 29
clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE
is asserted LOW, the pins can behave as outputs. When
HIGH, DQa–DQd are placed in a three-state condition.
The outputs are automatically three-stated during the
data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
4
CY7C1354V25
CY7C1356V25
PRELIMINARY
Pin Definitions (100-Pin TQFP) (continued)
x18 Pin Location x36 Pin Location Name
I/O Type
I/O-
Synchronous nals are identical to DQ
Description
Bidirectional Data Parity I/O lines. Functionally, these sig-
. During write sequences,
74, 24
51, 80, 1, 30
DPa
DPb
DPc
DPd
[31:0]
DPa is controlled by BWSa, DPb is controlled by BWSb,
DPc is controlled by BWSc, and DPd is controlled by
BWSd.
31
31
MODE
Input
Strap Pin
Mode Input. Selects the burst order of the device. Tied
HIGH selects the interleaved burst order. Pulled LOW
selects the linear burst order. MODE should not change
states during operation. When left floating MODE will de-
fault HIGH, to an interleaved burst order.
14–16, 41, 65, 66, 14–16, 41, 65, 66,
V
V
V
Power Supply Power supply inputs to the core of the device.
DD
91
91
4, 11, 20, 27, 54,
61, 70, 77
4, 11, 20, 27, 54,
61, 70, 77
I/O Power
Supply
Power supply for the I/O circuitry.
DDQ
SS
5, 10, 17, 21, 26,
5, 10, 17, 21, 26,
Ground
Ground for the device. Should be connected to ground of
the system.
40, 55, 60, 67, 71, 40, 55, 60, 67, 71,
76, 90
76, 90
NC
NC
NC
-
-
No connects. Reserved for address expansion to 512K
depths.
38, 39, 42, 43
38, 39, 42, 43
DNU
Do Not Use pins. These pins should be left floating or tied
to V
.
SS
5
CY7C1354V25
CY7C1356V25
PRELIMINARY
Pin Definitions (119 BGA)
x18 Pin Location
x36 Pin Location
Name
I/O Type
Description
P4, N4, A2, A3, A5, P4, N4, A2, A3, A5, A0
A6, B3, B5, C2, C3, A6, B3, B5, C2, C3, A1
Input-
Synchronous
Address Inputs used to select one of the 266,144
address locations. Sampled at the rising edge of the
CLK.
C5, C6, G4, R2, R6, C5, C6, R2, R6, G4,
A
T2, T3, T5, T6
T3, T4, T5
L5, G3
L5, G5, G3, L3
BWSa
BWSb
BWSc
BWSd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with
WE to conduct writes to the SRAM. Sampled on the
rising edge of CLK. BWSa controls DQa and DPa,
BWSb controls DQb and DPb, BWSc controls DQc
and DPc, BWSd controls DQd and DPd.
H4
B4
H4
B4
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the ris-
ing edge of CLK if CEN is active LOW. This signal
must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load Input used to advance the on-chip ad-
dress counter or load a new address. When HIGH
(and CEN is asserted LOW) the internal burst
counter is advanced. When LOW, a new address can
be loaded into the device for an access. After being
deselected, ADV/LD should be driven LOW in order
to load a new address.
K4
E4
B2
B6
F4
K4
E4
B2
B6
F4
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs
to the device. CLK is qualified with CEN. CLK is only
recognized if CEN is active LOW.
CE
CE
CE
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the
1
2
3
rising edge of CLK. Used in conjunction with CE and
2
CE to select/deselect the device.
3
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE and
1
CE to select/deselect the device.
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE and
1
CE to select/deselect the device.
2
OE
Input-
Asynchronous
Output Enable, active LOW. Combined with the syn-
chronous logic block inside the device to control the
direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data
pins. OE is masked during the data portion of a write
sequence , during the first clock when emerging from
a deselected state and when the device has been
deselected.
M4
M4
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted
LOW the clock signal is recognized by the SRAM.
When deasserted HIGH the clock signal is masked.
Since deassertingCEN doesnotdeselect the device,
CEN can be used to extend the previous cycle when
required.
6
CY7C1354V25
CY7C1356V25
PRELIMINARY
Pin Definitions (119 BGA) (continued)
x18 Pin Location
x36 Pin Location
Name
I/O Type
I/O-
Description
(a)P7, N6, L6, K7, (a)P7, N7, N6, M6, DQa
H6, G7, F6, E7
(b)N1, M2, L1, K2, (b)D7, E7, E6, F6,
H1, G2, E2, D1
Bidirectional Data I/O lines. As inputs, they feed into
an on-chip data register that is triggered by the rising
edge of CLK. As outputs, they deliver the data con-
L7, L6, K7, K6
DQb
DQc
DQd
Synchronous
G7, G6, H7, H6
(c)D1, E1, E2, F2,
G1, G2, H1, H2
(d)P1, N1, N2, M2,
L1, L2, K1, K2
tained in the memory location specified by A
dur-
[17:0]
ing the previous clock rise of the read cycle. The di-
rection of the pins is controlled byOE and the internal
controllogic. When OE is asserted LOW, the pinscan
behave as outputs. When HIGH, DQa–DQd are
placed in a three-state condition. The outputs are au-
tomatically three-stated during the data portion of a
write sequence, during the first clock when emerging
from a deselected state, and when the device is de-
selected, regardless of the state of OE.
D6, P2
R3
P6, D6, D2, P2
DPa
DPb
DPc
DPd
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these
signals are identical to DQ
. During write se-
[31:0]
quences, DPa is controlled by BWSa, DPb is con-
trolled by BWSb, DPc is controlled by BWSc, and
DPd is controlled by BWSd.
R3
MODE
Input
Strap pin
Mode Input. Selects the burst order of the device.
Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not
change states during operation. When left floating
MODE will default HIGH, to an interleaved burst or-
der.
C4, J2, J4, J6, R4
C4, J2, J4, J6, R4
V
V
Power Supply
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
DD
A1, A7, F1, F7, J1, A1, A7, F1, F7, J1,
J7, M1, M7, U1, U7 J7, M1, M7, U1, U7
I/O Power
Supply
DDQ
D3, D5, E3, E5, F3, D3, D5, E3, E5, F3,
F5, H3, H5, K3, K5, F5, H3, H5, K3, K5,
V
Ground
Ground for the device. Should be connected to
ground of the system.
SS
M3, M5, N3, N5,
P3, P5, R5
M3, M5, N3, N5, P3,
P5, R5
T7
T7
ZZ
-
-
-
-
-
-
U5
U5
TDO
TDI
U3
U3
U2
U2
TMS
TCK
U4
U4
A4, T6, T2
A4, T4, T1
NC, 16M,
NC, 32M,
NC, 64M
No connects. Reserved for address expansion to
512K depths.
B1, B7, C1, C7, D2, B7, C7, D4, J3, J5, NC
D4, D7, E1, E6, F2, L4, R1, R7, T1
G1, G5, G6, H2,
-
No connects.
H7, J3, J5, K1, K6,
L2, L3, L4, M6, N2,
N7, P1, P6, R1, R7
7
CY7C1354V25
CY7C1356V25
PRELIMINARY
quence, and will wrap-around when incremented sufficiently.
A HIGH input on ADV/LD will increment the internal burst
counter regardless of the state of chip enables inputs or WE.
WE is latched at the beginning of a burst cycle. Therefore, the
type of access (Read or Write) is maintained throughout the
burst sequence.
Introduction
Functional Overview
The CY7C1354V25/1356V25 are synchronous-pipelined
Burst NoBL SRAMs designed specifically to eliminate wait
states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of
the clock. The clock signal is qualified with the Clock Enable
input signal (CEN). If CEN is HIGH, the clock signal is not
recognized and all internal states are maintained. All synchro-
nous operations are qualified with CEN. All data outputs pass
through output registers controlled by the rising edge of the
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,
1
2
and CE are ALL asserted active, and (3) the write signal WE
3
is asserted LOW. The address presented to A –A is loaded
0
16
into the Address Register. The write signals are latched into
the Control Logic block.
clock. Maximum access delay from the clock rise (t ) is 3.2
ns (200-MHz device).
CO
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
Accesses can be initiated by asserting all three Chip Enables
(CE , CE , CE ) active at the rising edge of the clock. If Clock
1
2
3
Enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access
can either be a read or write operation, depending on the sta-
(DQ
/DP
for CY7C1354V25 and DQ /DP
for
a,b,c,d
a,b
a,b
a,b
CY7C1356V25). In addition, the address for the subsequent
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are assert-
ed).
tus of the Write Enable (WE). BWS
byte write operations.
can be used to conduct
[d:a]
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
On the next clock rise the data presented to DQ and DP
(DQ
/DP
for CY7C1354V25
&
DQ /DP
for
a,b,c,d
a,b
a,b
a,b
CY7C1356V25) (or a subset for byte write operations, see
Write Cycle Description Table for details) inputs is latched into
the device and the write is complete.
Three synchronous Chip Enables (CE , CE , CE ) and an
1
2
3
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.
The data written during the Write operation is controlled by
BWS (BWS
for CY7C1354V25
&
BWS
for
a,b,c,d
a,b
CY7C1356V25) signals. The CY7C1354V25/56V25 provides
byte write capability that is described in the Write Cycle De-
scription table. Asserting the Write Enable input (WE) with the
selected Byte Write Select (BWS) input will selectively write to
only the desired bytes. Bytes not selected during a byte write
operation will remain unaltered. A Synchronous self-timed
write mechanism has been provided to simplify the write oper-
ations. Byte write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple byte write operations.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE
1
2,
and CE are ALL asserted active, (3) the write enable input
3
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read ac-
cess is in progress and allows the requested data to propagate
to the input of the output register. At the rising edge of the next
clock the requested data is allowed to propagate through the
output register and onto the data bus within 3.2 ns (200-MHz
device) provided OE is active LOW. After the first clock of the
read access the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. During the second
clock, a subsequent operation (Read/Write/Deselect) can be
initiated. Deselecting the device is also pipelined. Therefore,
when the SRAM is deselected at clock rise by one of the chip
enable signals, its output will three-state following the next
clock rise.
Because the CY7C1354V25/56V25 is a common I/O device,
data should not be driven into the device while the outputs are
active. The Output Enable (OE) can be deasserted HIGH be-
fore presenting data to the DQ and DP(DQ
/DP
for
a,b,c,d
a,b
CY7C1354V25 & DQ /DP for CY7C1356V25) inputs. Do-
a,b
a,b
ing so will three-state the output drivers. As a safety precau-
tion, DQ and DP(DQ /DP for CY7C1354V25
DQ /DP for CY7C1356V25) are automatically three-stat-
&
a,b,c,d
a,b
a,b
a,b
ed during the data portion of a write cycle, regardless of the
state of OE.
Burst Write Accesses
The CY7C1354V25/56V25 has an on-chip burst counter that
allows the user the ability to supply a single address and con-
duct up to four WRITE operations without reasserting the ad-
dress inputs. ADV/LD must be driven LOW in order to load the
initial address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
Burst Read Accesses
The CY7C1354V25/1356V25 have on-chip burst counter that
allows the user the ability to supply a single address and con-
duct up to four Reads without reasserting the address inputs.
ADV/LD must be driven LOW in order to load a new address
into the SRAM, as described in the Single Read Access sec-
tion above. The sequence of the burst counter is determined
by the MODE input signal. A LOW input on MODE selects a
linear burst mode, a HIGH selects an interleaved burst se-
quence. Both burst counters use A0 and A1 in the burst se-
rise, the chip enables (CE , CE , and CE ) and WE inputs are
1
2
3
ignored and the burst counter is incremented. The correct
BWS (BWS for CY7C1354V25 BWS for
&
a,b,c,d
a,b
CY7C1356V25) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
8
CY7C1354V25
CY7C1356V25
PRELIMINARY
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Address
Used
ADV/
LD/
Operation
CE
CEN
WE
BWS
CLK
L-H
Comments
x
Deselected
External
1
0
L
X
X
I/Os three-state following next
recognized clock.
Suspend
-
X
1
X
X
X
X
L-H
Clock ignored, all operations
suspended.
Begin Read
Begin Write
External
External
0
0
0
0
0
0
1
0
L-H
L-H
Address latched.
Valid
Address latched, data presented
two valid clocks later.
Burst Read
Operation
Internal
X
0
1
X
X
L-H
Burst Read operation. Previous ac-
cess was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of Mode.
Burst Write
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous ac-
cess was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE. Bytes written are deter-
mined by BWS
.
[d:a]
Interleaved Burst Sequence
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Notes:
1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWS = 0 signifies at least one Byte Write Select is active, BWS = Valid
x
x
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS . See Write Cycle Description table for details.
x
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN=1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
9
CY7C1354V25
CY7C1356V25
PRELIMINARY
Write Cycle Description[1]
Function (CY7C1354V25)
WE
1
BWS
X
1
BWS
X
1
BWS
X
1
BWS
X
1
d
c
b
a
Read
Write - No bytes written
Write Byte 0 - (DQa and DPa)
Write Byte 1 - (DQb and DPb)
Write Bytes 1, 0
0
0
1
1
1
0
0
1
1
0
1
0
1
1
0
0
Write Byte 2 - (DQc and DPc)
Write Bytes 2, 0
0
1
0
1
1
0
1
0
1
0
Write Bytes 2, 1
0
1
0
0
1
Write Bytes 2, 1, 0
Write Byte 3 - (DQd and DPd)
Write Bytes 3, 0
0
1
0
0
0
0
0
1
1
1
0
0
1
1
0
Write Bytes 3, 1
0
0
1
0
1
Write Bytes 3, 1, 0
Write Bytes 3, 2
0
0
1
0
0
0
0
0
1
1
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
Function (CY7C1356V25)
WE
1
BWS
BWS
a
b
Read
x
1
1
0
0
x
1
0
1
0
Write - No Bytes Written
0
Write Byte 0 - (DQ and DP )
0
a
a
Write Byte 1 - (DQ and DP )
0
b
b
Write Both Bytes
0
10
CY7C1354V25
CY7C1356V25
PRELIMINARY
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354/56 incorporates a serial boundary scan Test
Access Port (TAP) in the BGA package only. The TQFP pack-
age does not offer this functionality. This port operates in ac-
cordance with IEEE Standard 1149.1-1900, but does not have
the set of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because
their inclusion places an added delay in the critical speed path
of the SRAM. Note that the TAP controller functions in a man-
ner that does not conflict with the operation of other devices
using 1149.1 fully compliant TAPs. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block Dia-
gram. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as de-
scribed in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary "01" pattern to allow
for fault isolation of the board level serial test path.
Disabling the JTAP Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller , TCK must be tied LOW
Bypass Register
(V ) to prevent clocking of the device. TDI and TMS are in-
SS
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
ternally pulled up and may be unconnected. They may alter-
nately be connected to V
through a pull-up resistor. TDO
DD
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the oper-
ation of the device.
Test Access Port (TAP) - Test Clock
Boundary Scan Register
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a xx-bit-long regis-
ter, and the x18 configuration has a yy-bit-long register.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the regis-
ters and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruc-
tion that is loaded into the TAP instruction register. For infor-
mation on loading the instruction register, see the TAP Con-
troller State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Defi-
nitions table.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State Dia-
gram). The output changes on the falling edge of TCK. TDO is
connected to the Least Significant Bit (LSB) of any register.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five ris-
ing edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is oper-
ating. At power-up, the TAP is reset internally to ensure that
TDO comes up in a High-Z state.
Eight different instructions are possible with the three-bit in-
struction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RE-
SERVED and should not be used. The other five instructions
are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller can-
not be used to load address, data, or control signals into the
SRAM and cannot preload the Input or Output buffers. The
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuit-
ry. Only one register can be selected at a time through the
11
CY7C1354V25
CY7C1356V25
PRELIMINARY
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE / PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
When the SAMPLE / PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP control-
ler needs to be moved into the Update-IR state.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible
that during the Capture-DR state, an input or output will under-
go a transition. The TAP may then try to capture a signal while
in transition (metastable state). This will not harm the device,
but there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be ex-
ecuted whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in the TAP controller, and there-
fore this device is not compliant to the 1149.1 standard.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (TCS and TCH). The SRAM clock input might not
be captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the
boundary scan register.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE / PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE / PRELOAD instruction, EX-
TEST places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP con-
troller enters the Shift-DR state. The IDCODE instruction is
loaded into the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the Up-
date-DR state while performing a SAMPLE / PRELOAD in-
struction will have the same effect as the Pause-DR command.
Bypass
When the BYPASS instruction is loaded in the instruction reg-
ister and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The advan-
tage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a
board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE / PRELOAD
Reserved
SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
12
CY7C1354V25
CY7C1356V25
PRELIMINARY
TAP Controller State Diagram
TEST-LOGIC
1
RESET
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
CAPTURE-DR
0
1
1
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
13
CY7C1354V25
CY7C1356V25
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
0
TDO
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
[7, 8]
TAP Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
1.7
Max.
Unit
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
I
I
I
I
= −2.0 mA
= −100 µA
= 2.0 mA
= 100 µA
V
V
OH1
OH
OH
OL
OL
V
2.1
OH2
V
0.7
0.2
V
OL1
V
V
OL2
V
V
1.7
−0.3
−5
V
+0.3
DD
V
IH
IL
0.7
V
I
GND ≤ V ≤ V
DDQ
5
µA
X
I
Notes:
7. All Voltage referenced to Ground
8. Overshoot: VIH(AC)<VDD+1.5V for t<tTCYC/2, Undershoot:VIL(AC)<0.5V for t<tTCYC/2, Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V for t<200 ms.
14
CY7C1354V25
CY7C1356V25
PRELIMINARY
[9, 10]
TAP AC Switching Characteristics Over the Operating Range
Parameter
Description
Min.
Max
Unit
ns
t
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
TCYC
TF
t
t
t
10
MHz
ns
40
40
TH
TCK Clock LOW
ns
TL
Set-up Times
t
t
t
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
TMSS
TDIS
CS
Hold Times
t
t
t
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
TMSH
TDIH
CH
Capture Hold after clock rise
Output Times
t
t
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
TDOV
TDOX
0
Notes:
9. CS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
t
10. Test conditions are specified using the load in TAP AC test conditions. Tr/Tf = 1 ns.
15
CY7C1354V25
CY7C1356V25
PRELIMINARY
TAP Timing and Test Conditions
1.25V
50
Ω
ALL INPUT PULSES
1.25V
TDO
2.5V
Z =50
Ω
0
=20 pF
C
L
0V
GND
(a)
t
TL
t
TH
Test Clock
TCK
t
TCYC
t
TMSS
t
TMSH
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data-In
TDI
Test Data-Out
TDO
t
t
TDOX
TDOV
16
CY7C1354V25
CY7C1356V25
PRELIMINARY
Identification Register Definitions
Instruction Field
Value
Description
Reserved for version number.
Revision Number
(31:28)
TBD
TBD
TBD
TBD
TBD
TBD
Device Depth
(27:23)
Defines depth of SRAM.
Defines with of the SRAM.
Reserved for future use.
Device Width
(22:18)
Cypress Device ID
(17:12)
Cypress JEDEC ID
(11:1)
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
ID Register Presence
(0)
Scan Register sizes
Register Name
Instruction
Bit Size
3
Bypass
1
ID
32
TBD
Boundary Scan
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register be-
tween TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
Captures the Input/Output contents. Places the boundary scan register be-
tween TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction
does not implement 1149.1 preload function and is therefore not 1149.1
compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
17
CY7C1354V25
CY7C1356V25
PRELIMINARY
Boundary Scan Order
Boundary Scan Order
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Bit #
Bit #
36
Bit #
71
Bit #
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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18
CY7C1354V25
CY7C1356V25
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Ambient
Supply Voltage on V Relative to GND.........−0.5V to +3.6V
[11]
DD
Range
Com’l
Temperature
V
/V
DD DDQ
DC Voltage Applied to Outputs
[12]
0°C to +70°C
2.5V ± 5%
in High Z State ....................................−0.5V to V
+ 0.5V
+ 0.5V
DDQ
[12]
DC Input Voltage ................................−0.5V to V
DDQ
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
2.375
2.375
2.0
Max.
2.625
2.625
Unit
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
V
V
V
V
V
DD
V
DDQ
[13]
V
V
V
= Min., I = –1.0 mA
OH
OH
DD
DD
[13]
V
= Min., I = 1.0 mA
0.2
OL
OL
V
1.7
V
+
DD
IH
0.3V
0.7
5
[12]
V
Input LOW Voltage
−0.3
−5
V
IL
I
Input Load Current
GND ≤ V ≤ V
µA
µA
µA
X
I
DDQ
Input Current of MODE
−30
−5
30
5
I
I
Output Leakage
Current
GND ≤ V ≤ V
Output Disabled
OZ
I
DDQ,
V
Operating Supply
V
f = f
= Max., I
= 0 mA,
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
All speed grades
475
450
320
300
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD
DD
DD
OUT
CYC
= 1/t
MAX
I
Automatic CE
Power-Down
Max. V , Device Deselected,
DD
SB1
V
≥ V or V ≤ V
IN
IH
IN
IL
80
Currentëë—TTL Inputs f = f
= 1/t
MAX
CYC
70
65
I
I
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. V , Device Deselected,
10
SB2
DD
V
≤ 0.3V or V > V
− 0.3V,
IN
IN
DDQ
f = 0
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. V , Device Deselected, or 5-ns cycle, 200 MHz
45
40
35
30
25
mA
mA
mA
mA
mA
SB3
DD
V
f = f
≤ 0.3V or V > V
− 0.3V
DDQ
IN
IN
CYC
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
All speed grades
= 1/t
MAX
I
Automatic CE
Max. V , Device Deselected,
DD
SB4
Power-Down
V
≥ V or V ≤ V , f = 0
IN IH IN IL
Current—TTL Inputs
Shaded areas contain advance information.
Notes:
11.
TA is the case temperature.
12. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
13. The load used for VOH and VOL testing is shown in figure (b) of the A/C test conditions.
19
CY7C1354V25
CY7C1356V25
PRELIMINARY
Capacitance[14]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
C
Input Capacitance
4
4
4
IN
A
V
= V
= 2.5V
DD
DDQ
Clock Input Capacitance
Input/Output Capacitance
pF
CLK
I/O
pF
AC Test Loads and Waveforms
R=1667
Ω
2.5V
[15]
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
2.5V
GND
90%
10%
Z =50
Ω
0
10%
R =50
Ω
L
5 pF
R=1538
Ω
< 2.5 ns
< 2.5 ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Thermal Resistance
Description
Test Conditions
Symbol
TQFP Typ.
Units
°C/W
Notes
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board
Q
TBD
14
JA
Thermal Resistance
(Junction to Case)
Q
TBD
°C/W
14
JC
Notes:
14. Tested initially and after any design or process change that may affect these parameters.
15. Input waveform should have a slew rate of 1 V/ns.
20
CY7C1354V25
CY7C1356V25
PRELIMINARY
[16]
Switching Characteristics Over the Operating Range
-200
-166
-133
-100
Parameter
Clock
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
Clock Cycle Time
5
6
7.5
10.0
ns
MHz
ns
CYC
F
Maximum Operating Frequency
Clock HIGH
200
166
133
100
MAX
t
t
1.4
1.4
1.7
1.7
2.0
2.0
4.0
4.0
CH
CL
Clock LOW
ns
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
3.2
3.2
3.5
3.5
4.2
4.2
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
CDV
EOV
DOH
CHZ
CLZ
[14, 17, 19]
OE LOW to Output Valid
Data Output Hold After CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
[14, 16, 17, 18, 19]
Clock to High-Z
3.2
3.0
3.5
3.3
3.5
4.0
3.5
4.8
[14, 16, 17, 18, 19]
Clock to Low-Z
[16, 17, 19]
OE HIGH to Output High-Z
EOHZ
EOLZ
[16, 17, 19]
OE LOW to Output Low-Z
0
0
0
0
Set-Up Times
t
t
t
t
t
t
Address Set-Up Before CLK Rise
Data Input Set-Up Before CLK Rise
CEN Set-Up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
AS
DS
CENS
WES
ALS
CES
WE, BWS Set-Up Before CLK Rise
x
ADV/LD Set-Up Before CLK Rise
Chip Select Set-Up
Hold Times
t
t
t
t
t
t
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
DH
CENH
WEH
ALH
CEH
WE, BW Hold After CLK Rise
x
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
Shaded areas contain advance information.
Notes:
16. AC test conditions assume signal transition time of 2 ns or less, timing reference levels, input pulse levels and output loading shown in part (a) of AC Test Load.
17. CHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
t
18. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
19. This parameter is sampled and not 100% tested.
21
CY7C1354V25
CY7C1356V25
PRELIMINARY
Switching Waveforms
READ/WRITE/DESELECT Sequence
CLK
CEN
t
CENH
t
CENS
t
t
CL
t
CYC
CH
t
t
AH
AS
CEN HIGH blocks
all synchronous inputs
WA2
WA5
RA1
RA3
RA4
RA6
ADDRESS
WE &
RA7
BWS
x
t
t
WS
WH
t
t
CEH
CES
CE
t
t
t
t
DH
DS
CHZ
CHZ
t
DOH
t
t
CLZ
DOH
Q1
Out
D2
In
Data-
In/Out
Q4
Out
D5
In
Q3
Out
Q6
Out
Q7
Out
Device
originally
t
CO
deselected
The combination of WE & BWS (x=a, b, c, d for CY7C1354V25 & x=a, b for CY7C1356V25) define a write cycle
x
(see Write Cycle Definition table) CE is the combination of CE , CE , and CE . All chip enables need to be active
1
2
3
in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW.
OE held LOW.
= UNDEFINED
= DON’T CARE
22
CY7C1354V25
CY7C1356V25
PRELIMINARY
Switching Waveforms (continued)
Burst Sequences
CLK
t
t
CYC
t
ALH
ALS
t
t
CL
CH
ADV/LD
ADDRESS
WE
t
t
AH
AS
RA1
WA2
RA3
t
t
WS
WH
t
t
WS
WH
BWS
CE
x
t
t
CES
CEH
t
t
CLZ
CHZ
t
t
DH
DOH
t
CLZ
Q3
Data-
In/Out
Q1
Q1+2
Out
Q1+3
Out
D2
In
D2+2
In
D2+3
Q1+1
Out
D2+1
In
Out
Out
In
Device
originally
deselected
t
CO
t
t
CO
DS
The combination of WE & BWS (x=a, b c, d) define a write cycle (see Write Cycle Definition table).
x
CE is the combination of CE , CE , and CE . All chip enables need to be active in order to select
1
2
3
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS input signals.
x
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
= UNDEFINED
= DON’T CARE
23
CY7C1354V25
CY7C1356V25
PRELIMINARY
Switching Waveforms (continued)
OE Timing
OE
t
EOV
t
EOHZ
Three-State
I/Os
t
EOLZ
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
200
CY7C1354V25-200AC/
CY7C1356V25-200AC
A101
TBD
A101
TBD
A101
TBD
A101
TBD
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1354V25-200BAC/
CY7C1356V25-200BAC
7 x 17 BGA
166
133
100
CY7C1354V25-166AC/
CY7C1356V25-166AC
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
7 x 17 BGA
CY7C1354V25-166BAC/
CY7C1356V25-166BAC
CY7C1354V25-133AC/
CY7C1356V25-133AC
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
7 x 17 BGA
CY7C1354V25-133BAC/
CY7C1356V25-133BAC
CY7C1354V25-100AC/
CY7C1356V25-100AC
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
7 x 17 BGA
CY7C1354V25-100BAC/
CY7C1356V25-100BAC
Shaded areas contain advance information.
Document #: 38-00762
24
CY7C1354V25
CY7C1356V25
PRELIMINARY
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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