CY7C1356B-250BZC [CYPRESS]
ZBT SRAM, 512KX18, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165;
| 型号： | CY7C1356B-250BZC |
| 厂家： | 
CYPRESS |
| 描述： | ZBT SRAM, 512KX18, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165 时钟 静态存储器 内存集成电路 |
| 文件： | 总25页 (文件大小：717K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1354B
CY7C1356B
PRELIMINARY
256K x 36/512K x 18 Pipelined SRAM with
NoBL™ Architecture
Latency™ (NoBL ) logic, respectively. They are designed
specifically to support unlimited true back-to-back Read/Write
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 166 MHz
operations without the insertion of wait states. The
CY7C1354B and CY7C1356B are equipped with the
advanced (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write/Read transitions. The CY7C1354B and
CY7C1356B are pin compatible and functionally equivalent to
ZBT devices.
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Separate VDDQ for 3.3V or 2.5V I/O
• Single 3.3V power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device).
— 3.0ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA
packages
Write operations are controlled by the Byte Write Selects
(BWSa–BWSd for CY7C1354B and BWSa–BWSb for
CY7C1356B) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
• IEEE 1149.1 JTAG-compatible Boundary Scan
• Burst capability—linear or interleaved burst order
•“ZZ” Sleep Mode option and Stop Clock option
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Functional Description
The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and
512K x 18 Synchronous pipelined burst SRAMs with No Bus
Logic Block Diagram
D
CLK
Data-In REG.
CE
Q
ADV/LD
A
x
CEN
CE
CONTROL
and WRITE
LOGIC
256KX36/
512KX18
MEMORY
ARRAY
1
CE
CE
2
DQ
x
3
WE
DQP
x
CY7C1354B CY7C1356B
BWS
x
X = 17:0
X = 18:0
A
X
Mode
X = a, b, c, d X = a, b
DQ
X
X = a, b, c, d X = a, b
X = a, b, c, d X = a, b
DQP
X
BWS
X
OE
Selection Guide
CY7C1354B-250
CY7C1356B-250
CY7C1354B-200
CY7C1356B-200
CY7C1354B-166
CY7C1356B-166
Unit
ns
Maximum Access Time
2.6
250
30
3.0
220
30
3.5
180
30
Maximum Operating Current
Com’l
mA
mA
Maximum CMOS Standby Current Com’l
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05114 Rev. **
Revised August 16, 2002
CY7C1354B
CY7C1356B
PRELIMINARY
Pin Configurations
100-pin TQFP Packages
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
1
2
3
4
5
6
7
8
A
NC
NC
78
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
NC
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
DQc
DQc
VSS
NC
NC
DQb
DQb
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
DQc
DQc
VSS
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQb
DQb
NC
VDD
NC
VSS
CY7C1354B
(256K x 36)
NC
VDD
ZZ
CY7C1356B
(512K x 18)
VDD
ZZ
DQa
DQa
DQb
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
DQb
VDDQ
VSS
VDDQ
VSS
DQa
DQa
DQb
DQb
DQa DQPb
DQa
VSS
VDDQ
DQa
DQa
DQPa
NC
VSS
VDDQ
NC
VSS
VDDQ
NC
NC
NC
VDDQ
DQd
DQd
DQPd
NC
NC
NC
Document #: 38-05114 Rev. **
Page 2 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Pin Configurations (continued)
119-ball BGA Pinout
CY7C1354B (256K x 36)–7 x 17 BGA
1
2
3
4
5
6
7
VDDQ
A
A
E(18)
A
A
VDDQ
A
NC
NC
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
B
C
D
E
F
G
H
J
DQc
DQPc
DQc
VSS
NC
VSS
VSS
VSS
BWS
DQPb
DQ
b
DQ
VSS
VSS
CE1
OE
A
DQ
DQb
VDDQ
DQb
c
b
VDDQ
DQ
DQb
c
DQ
DQc
BWSc
VSS
DQ
c
b
b
DQc
DQ
WE
VDD
CLK
NC
CEN
A1
DQb
VDD
DQ
VSS
NC
c
b
VDDQ
VDD
DQd
NC
VDDQ
DQa
DQ
VSS
VSS
BWSa
VSS
DQ
K
L
d
a
DQd
VDDQ
DQd
DQ
BWSd
VSS
DQa
DQ
d
a
DQd
DQ
VDDQ
M
N
P
a
DQ
VSS
VSS
DQa
DQ
d
a
DQ
DQPd
A
VSS
A0
VSS
DQP
DQa
NC
d
a
NC
NC
MODE
A
VDD
A
NC
A
A
R
T
E(72)
TMS
E(36)
NC
ZZ
VDDQ
TDI
TCK
TDO
VDDQ
U
CY7C1356B (512K x 18)–7 x 17 BGA
1
2
3
4
5
6
7
VDDQ
A
A
E(18)
A
A
VDDQ
A
B
C
D
E
F
NC
NC
CE2
A
A
ADV/LD
VDD
A
CE3
A
NC
NC
A
A
DQb
NC
NC
DQb
NC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPa
NC
NC
CE1
DQa
VDDQ
VDDQ
OE
DQa
NC
DQb
VDDQ
DQb
NC
VDD
BWSb
VSS
NC
A
VSS
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
G
H
J
WE
VDD
NC
DQb
VDDQ
DQb
NC
DQb
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
CLK
NC
VSS
BWSa
VSS
VSS
VSS
NC
NC
DQa
NC
DQa
NC
A
DQa
NC
K
L
DQb
NC
CEN
A1
VDDQ
NC
M
N
P
R
T
DQPb
A
A0
DQa
NC
NC
VDD
E(36)
TCK
E(72)
VDDQ
A
A
A
ZZ
TMS
TDI
TDO
NC
VDDQ
U
Document #: 38-05114 Rev. **
Page 3 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Pin Configurations (continued)
165-Ball fBGA Pinout
CY7C1354B (256K x 36)–13 x 15 fBGA
1
2
A
3
CE1
4
BWc
5
BWb
6
CE3
7
8
9
A
10
A
11
NC
E(288)
CEN
WE
VSS
VSS
VSS
ADV/LD
A
B
C
D
NC
A
CE2
VDDQ
VDDQ
BWd
VSS
VDD
BWa
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
E(18)
VDDQ
VDDQ
A
E(144)
DQPb
DQb
DQPc
DQc
NC
DQc
NC
DQb
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQb
DQb
DQb
NC
DQb
E
F
DQc
DQc
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQb
DQb
ZZ
G
H
J
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
K
L
DQd
DQPd
NC
DQd
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
DQa
DQPa
NC
M
N
P
E(72)
TDO
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
R
CY7C1356B (512K x 18)–13 x 15 fBGA
1
E(288)
NC
2
A
3
CE1
4
BWc
5
BWb
6
CE3
7
8
9
A
10
A
11
A
CEN
WE
VSS
VSS
VSS
ADV/LD
A
B
C
D
A
CE2
VDDQ
VDDQ
BWd
VSS
VDD
VDD
BWa
VSS
VSS
CLK
VSS
VSS
VSS
OE
VSS
VDD
VDD
E(18)
VDDQ
VDDQ
A
E(144)
DQPb
DQb
DQb
NC
NC
NC
NC
NC
NC
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
NC
E
F
NC
NC
DQb
DQb
VDD
NC
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
NC
NC
DQb
DQb
ZZ
G
H
J
NC
NC
DQb
DQb
VDDQ
VDDQ
DQa
DQa
NC
NC
VDDQ
VDDQ
VSS
VSS
VDDQ
VDDQ
NC
K
L
DQb
NC
NC
VDD
VDD
VSS
VSS
VSS
NC
A1
VSS
VDD
VDD
VSS
DQa
DQa
NC
A
NC
DQb
DQPb
NC
VDDQ
VDDQ
A
VSS
NC
VSS
NC
VDDQ
VDDQ
A
NC
NC
NC
M
N
P
NC
E(72)
TDI
TDO
A
A
A
A
MODE
E(36)
A
TMS
A0
TCK
A
A
A
R
Document #: 38-05114 Rev. **
Page 4 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
BWSa
BWSb
BWSc
BWSd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWSa controls DQa and DQPa, BWSb controls DQb and
DQPb, BWSc controls DQc and DQPc, BWSd controls DQd and DQPd.
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
CLK
CE1
CE2
CE3
OE
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
Input-
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the first clock when emerging from a
deselected state and when the device has been deselected.
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQa
DQb
DQc
DQd
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are
automatically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state of
OE.
DQPa
DQPb
DQPc
DQPd
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During
write sequences, DQPa is controlled by BWSa, DQPb is controlled by BWSb, DQPc is controlled
by BWSc, and DQPd is controlled by BWSd.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
TDI
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
VDD
JTAG-Clock
Clock input to the JTAG circuitry.
Power Supply
Power supply for the 3.3V control logic.
VDDQ
I/O Power Supply Either 3.3V or 2.5V power supply for the I/O circuitry.
Document #: 38-05114 Rev. **
Page 5 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Pin Definitions
Pin Name
VSS
I/O Type
Pin Description
Ground
Ground for the device. Should be connected to ground of the system.
No connects.
NC
–
–
E(18,36,7
2, 144,
288)
These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
and 288M densities.
ZZ
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. During normal operation, this pin can be connected to Vss or left
floating.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will three-state following
the next clock rise.
Introduction
Functional Overview
The CY7C1354B and CY7C1356B are synchronous-pipelined
Burst NoBL SRAMs designed specifically to eliminate wait
states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of
the clock. The clock signal is qualified with the Clock Enable
input signal (CEN). If CEN is HIGH, the clock signal is not
recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 2.6 ns (250-MHz device).
Burst Read Accesses
The CY7C1354B and CY7C1356B have an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BWS[d:a] can be used to
conduct byte write operations.
Single Write Accesses
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to A0–A16 is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b for CY7C1354B and DQa,b/DQPa,b for
CY7C1356B). In addition, the address for the subsequent
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are
asserted).
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 3.0 ns
(200-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b for CY7C1354B
& DQa,b/DQPa,b for
CY7C1356B) (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the write is complete.
The data written during the Write operation is controlled by
BWS (BWSa,b,c,d for CY7C1354B and BWSa,b for
CY7C1356B) signals. The CY7C1354B/56BV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Write Enable input (WE) with the selected
Byte Write Select (BWS) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A Synchronous self-timed write
mechanism has been provided to simplify the write operations.
Document #: 38-05114 Rev. **
Page 6 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Byte write capability has been included in order to greatly
simplify Read/Modify/Write sequences, which can be reduced
to simple byte write operations.
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BWS (BWSa,b,c,d for CY7C1354B and BWSa,b for
CY7C1356B) inputs must be driven in each cycle of the burst
write in order to write the correct bytes of data.
Because the CY7C1354B and CY7C1356B are common I/O
devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b for CY7C1354B and DQa,b/DQPa,b for
CY7C1356B) inputs. Doing so will three-state the output
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
drivers. As a safety precaution, DQ and DQP (DQa,b,c,d
/
DQPa,b for CY7C1354B and DQa,b/DQPa,b for CY7C1356B)
are automatically three-stated during the data portion of a write
cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1354B/56B has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four WRITE operations without reasserting the address
inputs. ADV/LD must be driven LOW in order to load the initial
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD − 0.2V
Min
Max
35
Unit
mA
ns
tZZS
ZZ > VDD − 0.2V
ZZ < 0.2V
2tCYC
tZZREC
2tCYC
ns
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Address
Used
Operation
CE CEN ADV/LD/ WE BWSx CLK
Comments
Deselected External
Suspend
1
X
0
0
1
0
0
0
L
X
0
0
1
X
X
1
X
X
L-H I/Os three-state following next recognized clock.
L-H Clock ignored, all operations suspended.
L-H Address latched.
–
Begin Read External
Begin Write External
X
0
0
Valid
X
L-H Address latched, data presented two valid clocks later.
Burst Read Internal
Operation
X
X
L-H Burst Read operation. Previous access was a Read
operation. Addresses incremented internally in
conjunction with the state of Mode.
Burst Write Internal
Operation
X
0
1
X
Valid
L-H Burst Write operation. Previous access was a Write
operation. Addresses incremented internally in
conjunction with the state of MODE. Bytes written are
determined by BWS[d:a]
.
Interleaved Burst Sequence
Linear Burst Sequence
First
Second
Third
Fourth
First
Second
Third
Fourth
Address
Address
Address
A[1:0]
10
Address
Address
Address
Address
Address
A[1:0]
00
A[1:0]
01
A[1:0]
11
A[1:0]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
01
00
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
Notes:
1. X = ”don't care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWS = 0 signifies at least one Byte Write Select is active, BWS
=
x
x
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS . See Write Cycle Description table for details.
x
3. The DQ and DQP pins are controlled by the current cycle and the OE signal.
4. CEN = 1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
Document #: 38-05114 Rev. **
Page 7 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Write Cycle Description[1, 2]
Function (CY7C1354B)
Read
WE
1
BWSd
BWSc
BWSb
BWSa
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Write – No bytes written
Write Byte 0 – (DQa and DQPa)
Write Byte 1 – (DQb and DQPb)
Write Bytes 1, 0
0
0
0
0
Write Byte 2 – (DQc and DQPc)
Write Bytes 2, 0
0
0
Write Bytes 2, 1
0
Write Bytes 2, 1, 0
0
Write Byte 3 – (DQd and DQPd)
Write Bytes 3, 0
0
0
Write Bytes 3, 1
0
Write Bytes 3, 1, 0
0
Write Bytes 3, 2
0
Write Bytes 3, 2, 0
0
Write Bytes 3, 2, 1
0
Write All Bytes
0
Function (CY7C1356B)
WE
1
BWSb
BWSa
Read
x
1
1
0
0
x
1
0
1
0
Write – No Bytes Written
Write Byte 0 – (DQa and DQPa)
Write Byte 1 – (DQb and DQPb)
Write Both Bytes
0
0
0
0
Test Access Port–Test Clock
IEEE 1149.1 Serial Boundary Scan (JTAG)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
The CY7C1354B/CY7C1356B incorporates a serial boundary
scan Test Access Port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This port
operates in accordance with IEEE Standard 1149.1-1900, but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 3.3V I/O logic levels.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
Document #: 38-05114 Rev. **
Page 8 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data, or control signals into
the SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
EXTEST
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
Bypass Register
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a xx-bit-long
register, and the x18 configuration has a yy-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.
Identification (ID) Register
When the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
Document #: 38-05114 Rev. **
Page 9 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
Bypass
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05114 Rev. **
Page 10 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
TAP Controller State Diagram[7]
TEST-LOGIC
1
RESET
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
7. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05114 Rev. **
Page 11 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
1
1
0
TDO
Instruction Register
TDI
29
Identification Register
31 30
.
.
2
0
0
.
68 .
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[8, 9]
Parameter
Description
Test Conditions
IOH = –2.0 mA, VDDQ = 3.3V
Min.
2.0
1.7
2.0
2.0
Max.
Unit
V
VOH1
Output HIGH Voltage
IOH = –2.0 mA, VDDQ = 2.5V
IOH = –100 µA, VDDQ = 3.3V
IOH = –100 µA, VDDQ = 2.5V
IOL = 2.0 mA
V
VOH2
Output HIGH Voltage
V
V
VOL1
VOL2
VIH
VIL
IX
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
0.7
0.2
V
IOL = 100 µA
V
1.7
–0.3
–30
–30
VDD + 0.3
0.7
V
V
GND ≤ VI ≤ VDDQ
30
µA
µA
IX
Input Load Current TMS and TDI GND ≤ VI ≤ VDDQ
30
[10, 11]
TAP AC Switching Characteristics Over the Operating Range
Parameter
tTCYC
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
ns
MHz
ns
tTF
10
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tTDIS
tCS
Notes:
8. All voltage referenced to ground.
9. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05114 Rev. **
Page 12 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range (continued)[10, 11]
Parameter
Hold Times
tTMSH
Description
Min.
Max.
Unit
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
tTDIH
tCH
Capture Hold after clock rise
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
20
ns
ns
0
TAP Timing and Test Conditions
1.5V for 3.3V V
1.25V for 2.5V V
ALL INPUT PULSES
1.5V or 1.25V
DDQ
DDQ
3.0V or 2.5V
1.5 ns
0V
50Ω
1.5 ns
TDO
Z = 50Ω
0
C = 20 pF
L
tTL
tTH
(a)
GND
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
Device Depth (27:23)
TBD
TBD
TBD
TBD
TBD
TBD
Reserved for version number.
Defines depth of SRAM.
Defines width of the SRAM.
Reserved for future use.
Device Width (22:18)
Cypress Device ID (17:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Document #: 38-05114 Rev. **
Page 13 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Scan Register Sizes
Register Name
Instruction
Bit Size
3
Bypass
1
ID
32
69
Boundary Scan
Identification Codes
Instruction
EXTEST
Code
Description
000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE
001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
SAMPLE Z
RESERVED
010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Capturesthe Input/Output ringcontents. Placestheboundaryscanregister betweenTDI andTDO.
Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1-compliant.
RESERVED
RESERVED
BYPASS
101 Do Not Use: This instruction is reserved for future use.
110
111
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Boundary Scan Exit Order (x36)
Boundary Scan Exit Order (x36) (continued)
Bit #
1
Signal Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
119-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
165-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bit #
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Signal Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
119-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
165-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Document #: 38-05114 Rev. **
Page 14 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Boundary Scan Exit Order (x36) (continued)
Boundary Scan Exit Order (x18) (continued)
Bit #
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Signal Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
119-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
165-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bit #
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Signal Name 119-Ball ID
165-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Boundary Scan Exit Order (x18)
Bit #
1
Signal Name 119-Ball ID
165-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Document #: 38-05114 Rev. **
Page 15 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature ................................–65×C to +150×C
Operating Range
Ambient Temperature with
Power Applied............................................–55×C to +125×C
Ambient
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
DC to Outputs in High-Z State[13]........ –0.5V to VDDQ + 0.5V
DC Input Voltage[13] ............................ –0.5V to VDDQ + 0.5V
Range
Temperature[12]
VDD/VDDQ
Commercial 0°C to +70°C
3.135 – 3.6V /
3.135 – 3.6V or 2.375 – 2.9V
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.465
VDD
Unit
V
Power Supply Voltage I0H=1.0 mA
VDDQ
VOH
VOL
VIH
VIL
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VDDQ = 3.3V
VDDQ = 2.5V
V
2.9
V
VDD = Min., IOH = −4.0 mA, VDDQ = 3.3V
VDD = Min., IOH = −1.0 mA, VDDQ = 2.5V
VDD = Min., IOH = 8.0 mA, VDDQ = 3.3V
VDD = Min., IOH = 1.0 mA, VDDQ = 2.5V
VDDQ = 3.3V
V
2.0
V
0.4
V
0.4
V
2.0
1.7
VDD + 0.3V
V
VDDQ = 2.5V
VDD + 0.3V
0.8
V
Input LOW Voltage[13] VDDQ = 3.3V
–0.3
–0.3
–5
V
VDDQ = 2.5V
0.7
V
IX
Input Load Current
GND ≤ VI ≤ VDDQ
5
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
Input Current of MODE
–30
–5
30
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
5
VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
250
220
180
250
220
180
30
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
V
IN ≥ VIH or VIN ≤ VIL, f = fMAX
=
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
1/tCYC
ISB2
Automatic CE
Power-down
Max. VDD, Device Deselected, All speed grades
IN ≤ 0.3V or VIN > VDDQ − 0.3V,
V
Current—CMOS Inputs f = 0
ISB3
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX = 1/tCYC
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
250
220
180
40
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
ISB4
Automatic CE
Power-down
Max. VDD, Device Deselected, All speed grades
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Notes:
12.
TA is the case temperature.
13. Minimum voltage equals −2.0V for pulse durations of less than 1 ns or -0.5V for 20 ns.
Document #: 38-05114 Rev. **
Page 16 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Capacitance[15]
Parameter
Description
Input Capacitance
Test Conditions
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
VDD = 3.3V VDDQ = 2.5V
4
4
4
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
AC Test Loads and Waveforms
R=1667/317Ω
V
[14]
DDQ
OUTPUT
ALL INPUT PULSES
DQ
3.0/2.5V
90%
10%
90%
10%
Z = 50Ω
0
1.5/1.25V
R = 50Ω
L
5 pF
0V
R = 1538/351Ω
< 1.0 ns
< 1.0 ns
V = 1.5V/1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Thermal Resistance
Parameters
Description
Test Conditions
BGA Typ. fBGA Typ. TQFP Typ.
Unit Notes
QJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x
1.125 inch, 4-layer printed
circuit board
25
27
25
°C/W
15
QJC
Thermal Resistance
(Junction to Case)
6
6
9
°C/W
15
[16, 20]
Switching Characteristics Over the Operating Range
-250
-200
-166
Parameter
Clock
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
4.0
5
6
ns
MHz
ns
FMAX
tCH
Maximum Operating Frequency
Clock HIGH
250
200
166
1.7
1.7
2.0
2.0
2.4
2.4
tCL
Clock LOW
ns
Output Times
tCO
Data Output Valid After CLK Rise
OE LOW to Output Valid[15, 17, 19]
Data Output Hold After CLK Rise
Clock to High-Z[15, 16, 17, 18, 19]
Clock to Low-Z[15, 16, 17, 18, 19]
OE HIGH to Output High-Z[16, 17, 19]
OE LOW to Output Low-Z[16, 17, 19]
2.6
2.6
3.0
3.0
3.5
3.5
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
1.25
1.25
1.25
1.5
1.5
1.5
1.5
1.5
1.5
tCHZ
2.6
2.6
3.0
3.0
3.5
3.5
tCLZ
tEOHZ
tEOLZ
Set-up Times
tAS
0
0
0
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
1.2
1.2
1.5
1.5
1.5
1.5
ns
ns
tDS
Notes:
14. Input waveform should have a slew rate of > 1 V/ns.
15. Tested initially and after any design or process change that may affect these parameters.
16. Unless otherwise noted, test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.5V or 1.25V, input pulse levels of 0 to 3.0V
or 2.5V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC test loads.
17.
tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
18. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
19. This parameter is sampled and not 100% tested.
20. AC parameters may violate minimums and maximums during the first 20 microseconds of operation.
Document #: 38-05114 Rev. **
Page 17 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[16, 20]
-250
-200
-166
Parameter
tCENS
tWES
tALS
Description
CEN Set-up Before CLK Rise
WE, BWSx Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
Min.
1.2
1.2
1.2
1.2
Max.
Min.
1.5
1.5
1.5
1.5
Max.
Min.
1.5
1.5
1.5
1.5
Max.
Unit
ns
ns
ns
tCES
ns
Hold Times
tAH
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
tALH
WE, BWx Hold After CLK Rise
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
tCEH
Shaded areas contain advance information.
Document #: 38-05114 Rev. **
Page 18 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Switching Waveforms
[21]
READ/WRITE/DESELECT Sequence
CLK
CEN
tCENH
tCENS
tCL
tCH
tCYC
tAH
tAS
CEN HIGH blocks
all synchronous inputs
WA2
WA5
RA1
RA3
RA4
RA6
ADDRESS
RA7
WE &
BWSx
tWS
tWH
tCEH
tCES
CE
tDH
tDS
tCHZ
tCHZ
tDOH
tCLZ
tDOH
Q4
Q1
Out
D2
In
Data-
In/Out
D5
In
Q3
Out
Q6
Out
Q7
Out
Out
Device
originally
tCO
deselected
= UNDEFINED
= DON’T CARE
Note:
21. The combination of WE and BWSx (x = a, b, c, d for CY7C1354B and x = a, b for CY7C1356B) define a write cycle (see Write Cycle Description table) CE is
the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands
for Read Address X, WAx Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW. OE held LOW.
Document #: 38-05114 Rev. **
Page 19 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Switching Waveforms (continued)
[22]
Burst Sequences
CLK
tCYC
tALH
tALS
ADV/LD
tCL
tCH
tAH
tAS
RA1
WA2
ADDRESS
WE
RA3
tWS
tWH
tWS
tWH
BWSx
tCES
tCEH
CE
tCLZ
tCHZ
tDH
tDOH
tCLZ
Q3
Data-
In/Out
Q1
Q1+2
Out
Q1+3
Out
D2
In
D2+2
In
D2+3
Q1+1
Out
D2+1
In
Out
Out
In
Device
originally
deselected
tCO
tCO
tDS
= UNDEFINED
= DON’T CARE
Note:
22. The combination of WE and BWSx(x = a, b c, d) define a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip
enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for Write Address
X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the
appropriate BWSx input signals. Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
Document #: 38-05114 Rev. **
Page 20 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Switching Waveforms (continued)
OE Timing
OE
tEOV
tEOHZ
Three-state
I/Os
tEOLZ
Ordering Information
Speed
Package
Operating
Range
(MHz)
Ordering Code
CY7C1354B-250AC
CY7C1356B-250AC
CY7C1354B-250BGC
CY7C1356B-250BGC
CY7C1354B-250BZC
CY7C1356B-250BZC
CY7C1354B-200AC
CY7C1356B-200AC
CY7C1354B-200BGC
CY7C1356B-200BGC
CY7C1354B-200BZC
CY7C1356B-200BZC
CY7C1354B-166AC
CY7C1356B-166AC
CY7C1354B-166BGC
CY7C1356B-166BGC
CY7C1354B-166BZC
CY7C1356B-166BZC
Name
Package Type
250
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Commercial
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
200
166
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Shaded areas contain advance information.
Document #: 38-05114 Rev. **
Page 21 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05114 Rev. **
Page 22 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4) BG119
51-85115-*A
Document #: 38-05114 Rev. **
Page 23 of 25
CY7C1354B
CY7C1356B
PRELIMINARY
Package Diagrams (continued)
165-ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*B
ZBT is a registered trademark of Integrated Device Technology. No Bus Latency and NoBL are trademarks of Cypress Semicon-
ductor Corporation.
Document #: 38-05114 Rev. **
Page 24 of 25
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1354B
CY7C1356B
PRELIMINARY
Document Title: CY7C1354B/CY7C1356B 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05114
Issue
Date
Orig. of
Change
REV.
ECN No.
Description of Change
117904
**
08/28/02
RCS
New Data Sheet
Document #: 38-05114 Rev. **
Page 25 of 25
相关型号：
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ZBT SRAM, 512KX18, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CYPRESS
CY7C1356BV25-225BZI
ZBT SRAM, 512KX18, 2.8ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CYPRESS
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