CY7C135_05 [CYPRESS]
4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores; 4K ×8双端口静态RAM和4K ×8双端口SRAM与信号灯
| 型号： | CY7C135_05 |
| 厂家： | 
CYPRESS |
| 描述： | 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores |
| 文件： | 总12页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C135
CY7C1342
4K x 8 Dual-Port Static RAM and 4K x 8
Dual-Port SRAM with Semaphores
Functional Description
Features
• True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
The CY7C135 and CY7C1342 are high-speed CMOS 4K x 8
dual-port static RAMs. The CY7C1342 includes semaphores
that provide a means to allocate portions of the dual-port RAM
or any shared resource. Two ports are provided permitting
independent, asynchronous access for reads and writes to
any location in memory. Application areas include interpro-
cessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
• 4K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). The
CY7C135 is suited for those systems that do not require
on-chip arbitration or are intolerant of wait states. Therefore,
the user must be aware that simultaneous access to a location
is possible. Semaphores are offered on the CY7C1342 to
assist in arbitrating between ports. The semaphore logic is
comprised of eight shared latches. Only one side can control
the latch (semaphore) at any time. Control of a semaphore
indicates that a shared resource is in use. An automatic
power-down feature is controlled independently on each port
by a chip enable (CE) pin or SEM pin (CY7C1342 only).
• Semaphoresincludedonthe7C1342topermitsoftware
handshaking between ports
• Available in 52-pin PLCC
• Pb-Free packages available
The CY7C135 and CY7C1342 are available in 52-pin PLCC.
Logic Block Diagram
R/W
L
R/W
R
CE
OE
CE
R
L
OE
R
L
I/O
I/O
7L
7R
0R
I/O
CONTROL
I/O
CONTROL
I/O
0L
I/O
A
A
11L
0L
11R
0R
ADDRESS
DECODER
ADDRESS
DECODER
MEMORY
ARRAY
A
A
SEMAPHORE
ARBITRATION
(7C1342 only)
CE
L
CE
R
OE
L
OE
R
R/W
R/W
R
L
(7C1342 only)
(7C1342 only)
SEM
SEM
R
L
Cypress Semiconductor Corporation
Document #: 38-06038 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 6, 2005
CY7C135
CY7C1342
Selection Guide
7C135-15
7C135-20
7C135-25
7C135-35
7C135-55
7C1342-15
7C1342-20
7C1342-25
7C1342-35
7C1342-55
Unit
ns
Maximum Access Time
15
20
25
35
55
Maximum Operating
Current
Commercial
Commercial
220
190
180
160
160
mA
Maximum Standby
Current for ISB1
60
50
40
30
30
mA
Pin Configurations
PLCC
Top View
7
6
5
4
3
2
1
52 51 50 49 48 47
46
A
OE
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
8
R
A
A
A
A
A
A
A
A
9
45
44
43
42
41
40
39
38
37
36
35
34
0R
10
11
12
13
14
15
16
17
18
19
20
1R
2R
3R
4R
5R
A
A
A
7C135
A
A
A
6R
A
7R
A
8R
A
9R
A
I/O
I/O
I/O
I/O
2L
NC
I/O
3L
7R
21 22 23 24 25 26 27 28 29 30 31 32 33
PLCC
Top View
7
6 5 4 3 2 1 52 51 50 49 48 47
A
OE
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
2L
3L
8
46
45
44
43
42
41
40
39
38
37
36
35
34
R
A
A
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
9
10
11
12
13
14
15
16
17
18
19
20
A
A
A
7C1342
A
A
A
I/O
I/O
I/O
I/O
A
A
8R
9R
NC
I/O
7R
21 22 23 24 25 26 27 28 29 30 31 32 33
Pin Definitions
Left Port
A0L–11L
Right Port
Description
A0R–11R
CER
Address Lines
Chip Enable
CEL
OEL
OER
Output Enable
Read/Write Enable
R/WL
R/WR
SEMR
SEML
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three
(CY7C1342 only) (CY7C1342 only) least significant bits of the address lines will determine which semaphore to write or read.
The I/O0 pin is used when writing to a semaphore. Semaphores are requested by writing
a 0 into the respective location.
Document #: 38-06038 Rev. *C
Page 2 of 12
CY7C135
CY7C1342
Maximum Ratings[1]
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................–65°C to+150°C
Latch-Up Current....................................................> 200 mA
Ambient Temperature with
Power Applied..............................................–55°C to+125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 48 to Pin 24) ............................................–0.5V to+7.0V
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High Z State ................................................–0.5V to+7.0V
DC Input Voltage[2]......................................... –3.0V to +7.0V
Electrical Characteristics Over the Operating Range
7C135-15
7C135-20
7C135-25
7C1342-15 7C1342-20 7C1342-25
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Test Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 4.0 mA
Min. Max. Min. Max. Min. Max. Unit
VOH
VOL
VIH
VIL
2.4
2.4
2.4
V
V
V
V
0.4
0.8
0.4
0.8
0.4
0.8
2.2
2.2
2.2
IIX
GND ≤ VI ≤ VCC
–10 +10 –10 +10 –10 +10 µA
–10 +10 –10 +10 –10 +10 µA
IOZ
Outputs Disabled,
GND ≤ VO ≤ VCC
ICC
Operating Current
VCC = Max.,
Com’l
Ind.
220
60
190
50
180 mA
190
IOUT = 0 mA
ISB1
ISB2
ISB3
Standby Current
(Both Ports TTL Levels)
CEL and CER ≥ VIH,
Com’l
Ind.
40
50
mA
[3]
f = fMAX
Standby Current
(One Port TTL Level)
CEL and CER ≥ VIH,
Com’l
Ind.
130
15
120
15
110 mA
120
[3]
f = fMAX
Standby Current
Both Ports CE and CER
≥
Com’l
15
mA
(Both Ports CMOS Levels) VCC – 0.2V,
V
IN ≥ VCC – 0.2V
Ind.
30
or VIN ≤ 0.2V, f = 0[3]
ISB4
Standby Current
(One Port CMOS Level)
One Port CEL or
CER ≥ VCC – 0.2V,
Com’l
Ind.
125
115
100 mA
115
V
V
IN ≥VCC – 0.2V or
IN ≤ 0.2V,
Active Port Outputs,
[3]
f = fMAX
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Pulse width < 20 ns.
3. f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
MAX
RC RC
standby I
.
SB3
Document #: 38-06038 Rev. *C
Page 3 of 12
CY7C135
CY7C1342
Electrical Characteristics Over the Operating Range (continued)
7C135-35
7C135-55
7C1342-35 7C1342-55
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
VCC = Min., IOH = –4.0 mA
Min. Max. Min. Max. Unit
VOH
VOL
VIH
VIL
IIX
2.4
2.2
2.4
2.2
V
V
VCC = Min., IOL = 4.0 mA
0.4
0.8
0.4
0.8
V
Input LOW Voltage
Input Load Current
Output Leakage Current
Operating Current
V
GND ≤ VI ≤ VCC
–10 +10 –10 +10
–10 +10 –10 +10
µA
µA
mA
IOZ
ICC
Outputs Disabled, GND ≤ VO ≤ VCC
VCC = Max., IOUT = 0 mA
VCC = Max., IOUT = 0 mA
Com’l
Ind.
160
180
30
160
180
30
[3]
ISB1
ISB2
ISB3
Standby Current
(Both Ports TTL Levels)
CEL and CER ≥ VIH, f = fMAX
Com’l
Ind.
mA
mA
mA
40
40
[3]
Standby Current
(One Port TTL Level)
CEL and CER ≥ VIH, f = fMAX
Com’l
Ind.
100
110
15
100
110
15
Standby Current
Both Ports CE and CER ≥ VCC – 0.2V, Com’l
(Both Ports CMOS Levels) VIN ≥ VCC – 0.2V
Ind.
30
30
or VIN ≤ 0.2V, f = 0[3]
ISB4
Standby Current
(One Port CMOS Level)
One Port CEL or CER ≥ VCC – 0.2V,
IN ≥ VCC – 0.2V or VIN ≤ 0.2V,
Active Port Outputs, f = fMAX
Com’l
Ind.
90
90
mA
V
100
100
[3]
Capacitance[4]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 5.0V
Max.
Unit
CIN
Input Capacitance
Output Capacitance
10
10
pF
pF
V
COUT
AC Test Loads and Waveforms
5V
R1 = 893Ω
RTH = 250Ω
RTH = 250Ω
OUTPUT
OUTPUT
C = 30 pF
OUTPUT
C = 5 pF
C = 30 pF
R1 = 347Ω
VX
VTH = 1.4V
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 3)
ALL INPUT PULSES
3.0V
GND
90%
90%
10%
≤ 3 ns
10%
≤3 ns
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06038 Rev. *C
Page 4 of 12
CY7C135
CY7C1342
Switching Characteristics Over the Operating Range[5]
7C135-15
7C135-20
7C135-25
7C135-35
7C135-55
7C1342-15 7C1342-20 7C1342-25 7C1342-35 7C1342-55
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
15
3
20
3
25
3
35
3
55
3
ns
ns
ns
tAA
Address to Data Valid
15
20
25
35
55
tOHA
Output Hold From Address
Change
tACE
tDOE
tLZOE
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
15
10
20
13
25
15
35
20
55
25
ns
ns
ns
ns
ns
ns
ns
ns
[6,7,8]
[6,7,8]
3
3
0
3
3
0
3
3
0
3
3
0
3
3
0
tHZOE
OE HIGH to High Z
CE LOW to Low Z
10
10
15
13
13
20
15
15
25
20
20
35
25
25
55
[6,7,8]
tLZCE
[6,7,8]
tHZCE
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
[8]
tPU
[8]
tPD
WRITE CYCLE
tWC Write Cycle Time
tSCE
tAW
15
12
12
2
20
15
15
2
25
20
20
2
35
30
30
2
55
50
50
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
Write Pulse Width
tHA
tSA
0
0
0
0
0
tPWE
tSD
12
10
0
15
13
0
20
15
0
25
15
0
50
25
0
Data Set-Up to Write End
Data Hold from Write End
R/W LOW to High Z
tHD
[7,8]
tHZWE
10
13
15
20
25
[7,8]
tLZWE
R/W HIGH to Low Z
3
3
3
3
3
[9]
tWDD
Write Pulse to Data Delay
30
25
40
30
50
30
60
35
70
40
[9]
tDDD
Write Data Valid to Read Data
Valid
SEMAPHORE TIMING[10]
tSOP
SEM Flag Update Pulse
(OE or SEM)
10
10
10
15
15
ns
tSWRD
SEM Flag Write to Read Time
SEM Flag Contention Window
5
5
5
5
5
5
5
5
5
5
ns
ns
tSPS
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
6. At any given temperature and voltage condition for any given device, t
is less than t
and t
is less than t
.
LZOE
HZCE
LZCE
HZOE
7. Test conditions used are Load 3.
8. This parameter is guaranteed but not tested.
9. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
10. Semaphore timing applies only to CY7C1342.
Document #: 38-06038 Rev. *C
Page 5 of 12
CY7C135
CY7C1342
Switching Waveforms
Read Cycle No. 1[11,12]
Either Port Address Access
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2[11,13]
Either Port CE/OE Access
[10]
or CE
OE
SEM
t
HZCE
t
ACE
t
HZOE
t
DOE
t
LZOE
t
LZCE
DATA VALID
DATA OUT
t
PU
t
PD
ICC
ISB
Read Timing with Port-to-Port[14]
t
wc
ADDRESSR
R/WR
MATCH
t
PWE
t
t
SD
HD
DATA
VALID
INR
ADDRESSL
MATCH
t
DDD
DATA
VALID
OUTL
t
WDD
Notes:
11. R/W is HIGH for read cycle.
12. Device is continuously selected, CE = V and OE = V
.
IL
IL
13. Address valid prior to or coincident with CE transition LOW.
14. CE = CE =LOW; R/W = HIGH
L
R
L
Document #: 38-06038 Rev. *C
Page 6 of 12
CY7C135
CY7C1342
Switching Waveforms (continued)
Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[15, 16, 17]
t
WC
ADDRESS
[10]
t
SCE
SEM
OR CE
t
t
HA
AW
t
PWE
R/W
t
SA
t
t
HD
SD
DATA
IN
DATA VALID
OE
t
t
HZOE
LZOE
HIGH IMPEDANCE
DATA
OUT
Write Cycle No. 2:R/W Three-States Data I/Os (Either Port)[16, 18]
t
WC
ADDRESS
t
t
HA
SCE
[10]
SEM
OR
CE
t
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATA VALID
DATA
IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA
OUT
Notes:
15. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
16. R/W must be HIGH during all address transactions.
17. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the I/O drivers to turn off and data to
HZWE SD
PWE
be placed on the bus for the required t . If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write
SD
pulse can be as short as the specified t
.
PWE
18. Data I/O pins enter high-impedance when OE is held LOW during write.
Document #: 38-06038 Rev. *C
Page 7 of 12
CY7C135
CY7C1342
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side (CY7C1342 only)[19]
t
AA
t
OHA
A0–A2
VALID ADDRESS
VALID ADDRESS
t
AW
t
ACE
t
SEM
HA
t
SCE
t
SOP
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
SA
t
PWE
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention (CY7C1342 only)[20, 21, 22]
A0L–A2L
MATCH
R/WL
SEML
tSPS
A0R–A2R
MATCH
R/WR
SEMR
Notes:
19. CE = HIGH for the duration of the above timing (both write and read cycle).
20. I/O = I/O = LOW (request semaphore); CE = CE = HIGH.
0R
0L
R
L
21. Semaphores are reset (available to both ports) at cycle start.
22. If t is violated, it is guaranteed that only one side will gain access to the semaphore.
SPS
Document #: 38-06038 Rev. *C
Page 8 of 12
CY7C135
CY7C1342
zero (the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore. Table 2 shows sample semaphore operations.
Architecture
The CY7C135 consists of an array of 4K words of 8 bits each
of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). Two semaphore control pins exist for
the CY7C1342 (SEML/R).
When reading a semaphore, all eight data lines output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports request a semaphore
control by writing a 0 to a semaphore within tSPS of each other,
it is guaranteed that only one side will gain access to the
semaphore.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. Since there is no
on-chip arbitration, the user must be sure that a specific
location will not be accessed simultaneously by both ports or
erroneous data could result. A write operation is controlled by
either the OE pin (see Write Cycle No. 1 timing diagram) or the
R/W pin (see Write Cycle No. 2 timing diagram). Data can be
written tHZOE after the OE is deasserted or tHZWE after the
falling edge of R/W. Required inputs for write operations are
summarized in Table 1.
Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All
semaphores on both sides should have a one written into them
at initialization from both sides to assure that they will be free
when needed.
Table 1. Non-Contending Read/Write
If a location is being written to by one port and the opposite
port attempts to read the same location, a port-to-port
flowthrough delay is met before the data is valid on the output.
Data will be valid on the port wishing to read the location tDDD
after the data is presented on the writing port.
Inputs
Outputs
CE R/W OE SEM I/O0 – I/O7
Operation
Power-Down
H
H
X
H
X
L
H
L
High Z
Data Out
Read
Semaphore
Read Operation
X
H
L
X
L
H
X
L
X
L
High Z
I/O Lines Disabled
Write to Semaphore
Read
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE are asserted. If the user of the CY7C1342 wishes to
access a semaphore, the SEM pin must be asserted instead
of the CE pin. Required inputs for read operations are summa-
rized in Table 1.
Data In
Data Out
Data In
H
L
H
H
L
L
X
X
Write
L
X
Illegal Condition
Semaphore Operation
Table 2. Semaphore Operation Example
The CY7C1342 provides eight semaphore latches which are
separate from the dual port memory locations. Semaphores
are used to reserve resources which are shared between the
two ports. The state of the semaphore indicates that a
resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a
semaphore location. The left port then verifies its success in
setting the latch by reading it. After writing to the semaphore,
SEM or OE must be deasserted for tSOP before attempting to
read the semaphore. The semaphore value will be available
I/O0-7 I/O0-7
Function
No Action
Left Right
Status
1
0
1
1
Semaphore free
Left port writes
semaphore
Left port obtains
semaphore
Right port writes 0 to
semaphore
0
1
1
0
1
1
1
0
1
1
0
0
1
1
0
1
1
1
Right side is denied
access
Left port writes 1 to
semaphore
Right port is granted
access to Semaphore
t
SWRD + tDOE after the rising edge of the semaphore write. If
the left port was successful (reads a zero), it assumes control
over the shared resource, otherwise (reads a one) it assumes
the right port has control and continues to poll the semaphore.
When the right side has relinquished control of the semaphore
(by writing a one), the left side will succeed in gaining control
of the semaphore. If the left side no longer requires the
semaphore, a one is written to cancel its request.
Left port writes 0 to
semaphore
No change. Left port is
denied access
Right port writes 1 to
semaphore
Left port obtains
semaphore
Left port writes 1 to
semaphore
No port accessing
semaphore address
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches. CE
must remain HIGH during SEM LOW. A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
Right port writes 0 to
semaphore
Right port obtains
semaphore
Right port writes 1 to
semaphore
No port accessing
semaphore
Left port writes 0 to
semaphore
Left port obtains
semaphore
When writing to the semaphore, only I/O0 is used. If a 0 is
written to the left port of an unused semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing a
Left port writes 1 to
semaphore
No port accessing
semaphore
Document #: 38-06038 Rev. *C
Page 9 of 12
CY7C135
CY7C1342
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
140
120
100
80
1.4
1.2
1.0
ISB
ICC
1.2
1.0
ISB3
0.8
0.6
0.4
0.8
0.6
0.4
VCC = 5.0V
TA = 25°C
VCC = 5.0V
VIN = 5.0V
60
40
0.2
0.6
0.2
ICC
0.0
20
0
4.0
4.5
5.0
5.5
6.0
–55
25
125
0
1.0
2.0
3.0
4.0 5.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
1.1
100
90
1.10
1.05
TA = 25°C
80
70
1.0
0.9
V
CC = 5.0V
1.00
0.95
VCC = 5.0V
TA = 25°C
60
50
0.8
–55
0.0
1.0
2.0
3.0
4.0 5.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED ICC vs. CYCLE TIME
1.25
20.0
1.0
VCC = 5.0V
TA = 25°C
V
IN = 5.0V
15.0
10.0
0.75
0.50
1.0
0.75
VCC = 4.5V
5.0
0
0.25
0.0
TA = 25°C
0.50
10
20
30
40
50
0
200 400 600 800 1000
CAPACITANCE (pF)
0
1.0
2.0
3.0
4.0 5.0
CYCLE FREQUENCY (MHz)
SUPPLY VOLTAGE (V)
Document #: 38-06038 Rev. *C
Page 10 of 12
CY7C135
CY7C1342
Ordering Information
4K x8 Dual-Port SRAM
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
15
CY7C135–15JC
CY7C135-15JXC
CY7C135–20JC
CY7C135–25JC
CY7C135-25JXC
CY7C135–25JI
CY7C135–35JC
CY7C135–35JI
CY7C135–55JC
CY7C135–55JI
J69
J69
J69
J69
J69
J69
J69
J69
J69
J69
52-Lead Plastic Leaded Chip Carrier
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
Commercial
20
25
Commercial
Commercial
Industrial
35
55
Commercial
Industrial
Commercial
Industrial
4K x8 Dual-Port SRAM with Semaphores
Speed
Package
Type
Operating
Range
(ns)
Ordering Code
Package Type
15
CY7C1342–15JC
J69
J69
J69
J69
J69
J69
J69
J69
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
Commercial
Industrial
20
CY7C1342–20JC
CY7C1342–25JC
CY7C1342–25JI
CY7C1342–35JC
CY7C1342–35JI
CY7C1342–55JC
CY7C1342–55JI
25
35
55
Commercial
Industrial
Commercial
Industrial
Package Diagrams
52-Lead Plastic Leaded Chip Carrier J69
52-Lead Pb-Free Plastic Leaded Chip Carrier J69
51-85004-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06038 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C135
CY7C1342
Document History Page
Document Title: CY7C135/CY7C1342 4K x 8 Dual Port Static RAM and 4K x 8 Dual Port Static RAM w/Semaphores
Document Number: 38-06038
Issue
Orig. of
Change
REV.
**
ECN NO. Date
Description of Change
110181
122288
236763
393413
10/21/01
SZV
RBI
Change from Spec number: 38-00541 to 38-06038
Power up requirements added to Maximum Ratings Information
Removed cross information from features section
*A
*B
*C
12/27/02
SEE ECN
See ECN
YDT
YIM
Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C135-15JXC, CY7C135-25JXC
Document #: 38-06038 Rev. *C
Page 12 of 12
相关型号：
©2020 ICPDF网 联系我们和版权申明