CY7C1362C-166BGC [CYPRESS]
9-Mbit (256K x 36/512K x 18) Pipelined SRAM; 9兆位（ 256K ×36 / 512K ×18 ）流水线式SRAM
| 型号： | CY7C1362C-166BGC |
| 厂家： | 
CYPRESS |
| 描述： | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| 文件： | 总31页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1360C
CY7C1362C
PRELIMINARY
9-Mbit (256K x 36/512K x 18) Pipelined SRAM
Features
Functional Description[1]
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36
and 524,288 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP,
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
ADV), Write Enables (BW , and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
and
— 2.8 ns (for 250-MHz device)
X
— 3.0 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the Byte Write control inputs. GW when active
• Asynchronous output enable
• Single Cycle Chip Deselect
• Offered in Lead-Free 100-pin TQFP, 119-ball BGA and
165-Ball fBGA packages
LOW cause
s all bytes to be written.
The CY7C1360C/CY7C1362C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
Logic Block Diagram – CY7C1360C (256K x 36)
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND
CLR
Q0
LOGIC
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D ,DQPD
DQ
BYTE
WRITE DRIVER
D ,DQPD
BW
D
DQC ,DQP
BYTE
WRITE DRIVER
C
DQC ,DQP
BYTE
WRITE REGISTER
C
BW
C
OUTPUT
BUFFERS
OUTPUT
MEMORY
DQ s
SENSE
AMPS
ARRAY
REGISTERS
DQP
DQP
DQP
A
DQB ,DQP
BYTE
WRITE DRIVER
B
E
DQB ,DQP
BYTE
WRITE REGISTER
B
B
C
BW
BW
B
A
DQPD
DQ
BYTE
WRITE DRIVER
A ,DQPA
DQ
A ,DQPA
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE is for A version of TQFP (3 Chip Enable option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.
3
Cypress Semiconductor Corporation
Document #: 38-05540 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 23, 2005
CY7C1360C
CY7C1362C
PRELIMINARY
Logic Block Diagram – CY7C1362C (512K x 18)
ADDRESS
REGISTER
A0, A1, A
MODE
A[1:0]
2
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQB,DQP
B
DQB,DQP
WRITE REGISTER
B
WRITE DRIVER
OUTPUT
DQs
BW
B
A
OUTPUT
REGISTERS
SENSE
AMPS
MEMORY
ARRAY
BUFFERS
DQP
A
B
DQP
DQA,DQP
A
E
DQA,DQP
WRITE REGISTER
A
WRITE DRIVER
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE1
CE2
PIPELINED
ENABLE
CE3
OE
SLEEP
CONTROL
ZZ
Selection Guide
250 MHz
200 MHz
166 MHz
Unit
Maximum Access Time
2.8
250
30
3.0
220
30
3.5
180
30
ns
Maximum Operating Current
mA
mA
Maximum CMOS Standby Current
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05540 Rev. *C
Page 2 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Pin Configurations
100-pin TQFP Pinout (3 Chip Enables) (A version)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQc
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
NC
14
VDD
15
NC
VDD
ZZ
CY7C1362C
(512K x 18)
CY7C1360C
(256K X 36)
NC
16
VDD
ZZ
VSS
17
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
20
21
VDDQ
VSSQ
DQD
22
DQD
23
DQD
24
DQD
25
26
27
NC
VSSQ
VDDQ
DQD
DQD
29
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
28
DQPD
30
Document #: 38-05540 Rev. *C
Page 3 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Pin Configurations (continued)
100-pin TQFP (2 Chip Enables) (AJ Version)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
NC
14
VDD
15
NC
VDD
ZZ
CY7C1362C
(512K x 18)
CY7C1360C
(256K X 36)
NC
16
VDD
ZZ
VSS
DQD
17
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
VDDQ
VSSQ
DQD
20
21
22
DQD
23
DQD
24
DQD
25
26
27
NC
VSSQ
VDDQ
DQD
DQD
29
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
28
DQPD
30
Document #: 38-05540 Rev. *C
Page 4 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Pin Configurations (continued)
119-ball BGA (2 Chip Enables with JTAG)
CY7C1360C (256K x 36)
1
2
3
4
5
6
7
VDDQ
A
A
A
A
VDDQ
A
ADSP
ADSC
VDD
B
C
NC/288M
NC/144M
CE2
A
A
A
A
A
A
A
NC/576M
NC/1G
DQC
DQC
VDDQ
DQPC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
D
E
F
CE1
DQC
DQB
VDDQ
OE
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
BWC
VSS
NC
BWB
VSS
NC
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
G
H
J
ADV
GW
VDD
DQD
VSS
CLK
NC
VSS
K
L
M
N
DQD
VDDQ
DQD
DQD
DQD
DQD
DQA
DQA
DQA
DQA
VDDQ
DQA
BWD
VSS
VSS
BWA
VSS
VSS
BWE
A1
P
R
DQD
NC
DQPD
A
VSS
A0
VSS
NC
DQPA
A
DQA
NC
MODE
VDD
T
NC
NC/72M
TMS
A
A
A
NC/36M
NC
ZZ
U
VDDQ
TDI
TCK
TDO
VDDQ
CY7C1362C (512K x 18)
2
A
1
3
A
4
5
A
6
A
7
VDDQ
NC/576M
NC/1G
NC
A
B
C
D
E
F
VDDQ
ADSP
NC/288M
NC/144M
DQB
CE2
A
A
A
A
ADSC
VDD
A
A
A
NC
DQB
NC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPA
NC
DQA
NC
DQA
CE1
VDDQ
VDDQ
OE
G
H
J
NC
DQB
NC
VDD
VSS
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
BWB
VSS
NC
ADV
DQB
VDDQ
GW
VDD
NC
DQB
VSS
CLK
NC
VSS
NC
DQA
K
L
DQB
VDDQ
DQB
NC
NC
DQB
NC
VSS
VSS
VSS
VSS
DQA
NC
NC
VDDQ
NC
BWA
VSS
M
N
P
BWE
A1
VSS
VSS
DQA
NC
DQPB
A0
DQA
R
T
NC
A
A
MODE
A
VDD
NC/36M
TCK
NC
A
A
A
NC
ZZ
NC/72M
VDDQ
U
TMS
TDI
TDO
NC
VDDQ
Document #: 38-05540 Rev. *C
Page 5 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Pin Configurations (continued)
165-ball fBGA (3 Chip Enable with JTAG)
CY7C1360C (256K x 36)
1
2
3
4
5
6
7
8
9
10
A
11
NC
NC / 288M
NC/144M
DQPC
A
B
C
D
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
OE
A
BWE
GW
VSS
VSS
ADV
ADSP
VDDQ
VDDQ
A
CE2
VDDQ
VDDQ
A
NC / 576M
DQPB
DQB
NC
VSS
VDD
NC/1G
DQB
DQC
DQC
DQC
DQC
DQC
NC
DQC
DQC
DQC
VSS
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC / 18M
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC / 72M
TDI
TDO
A0
MODE NC / 36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1362C (512K x 18)
1
NC / 288M
NC/144M
NC
2
A
3
4
5
NC
6
7
8
9
10
A
11
A
A
B
C
D
BWB
NC
CE3
CLK
VSS
VSS
CE1
CE2
BWE
GW
VSS
VSS
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
A
BWA
VSS
VSS
A
NC / 576M
DQPA
DQA
NC
VDDQ
VDDQ
VSS
VDD
VSS
NC/1G
NC
NC
DQB
VDD
NC
NC
DQB
DQB
DQB
VSS
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQB
DQB
DQB
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC / 18M
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
NC / 72M
TDI
TDO
MODE NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05540 Rev. *C
Page 6 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled
active. A , A are fed to the two-bit counter.
.
1
0
BWA, BWB
BWC, BWD
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the
SRAM. Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global Write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
BWE
CLK
CE1
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a Byte Write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is
HIGH. CE1 is sampled only when a new external address is loaded.
CE2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
[2]
CE3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device. Not available for AJ package
version. Not connected for BGA. Where referenced, CE3[2] is assumed active throughout
this document for BGA. CE3 is sampled only when a new external address is loaded.
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ADSC
ZZ
Input-
ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and DQPX are placed in a three-state condition.
DQs, DQPX
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
Ground for the I/O circuitry.
VSSQ
VDDQ
MODE
I/O Ground
I/O Power Supply Power supply for the I/O circuitry.
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode pin has an internal pull-up.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous
JTAG feature is not being utilized, this pin should be disconnected. This pin is not available
on TQFP packages.
Document #: 38-05540 Rev. *C
Page 7 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Pin Definitions (continued)
Name
I/O
Description
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not being utilized, this pin can be disconnected or connected to VDD. This pin
is not available on TQFP packages.
TMS
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not being utilized, this pin can be disconnected or connected to VDD. This pin
is not available on TQFP packages.
TCK
NC
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
–
No Connects. Not internally connected to the die
the chip select and either ADSP or ADSC signals, its output
will three-state immediately.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 2.8 ns
(250-MHz device).
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
[2]
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BWX) and
ADV inputs are ignored during this first cycle.
The CY7C1360C/CY7C1362C supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BWX
signals. The CY7C1360C/CY7C1362C provides Byte Write
capability that is described in the Write Cycle Descriptions
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write (BWX) input, will selectively write to only
the desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
Write mechanism has been provided to simplify the Write
operations.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Because the CY7C1360C/CY7C1362C is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQs inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
Single Read Accesses
Single Write Accesses Initiated by ADSC
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3[2] are all asserted active,
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BWX) are asserted active to conduct a Write to the
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
[2]
CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE1 is HIGH. The address presented to the address inputs
(A) is stored into the address advancement logic and the
address register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the output registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 2.8 ns (250-MHz device) if OE is
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always three-stated during the first cycle of the
access. After the first cycle of the access, the outputs are
controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
Document #: 38-05540 Rev. *C
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CY7C1360C
CY7C1362C
PRELIMINARY
Because the CY7C1360C/CY7C1362C is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQs inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Burst Sequences
The CY7C1360C/CY7C1362C provides a two-bit wraparound
counter, fed by A1, A0, that implements either an interleaved
or linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel Pentium applications.
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3[2], ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
50
Unit
mA
ns
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ < 0.2V
2tCYC
0
ns
ZZ Active to sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
ns
Truth Table [3, 4, 5, 6, 7, 8]
Address
Used
Operation
CE2
X
CE3
X
WRITE
CLK
DQ
CE1
H
ZZ ADSP ADSC ADV
OE
X
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
READ Cycle, Begin Burst
None
None
L
L
L
L
L
H
L
L
X
L
X
X
L
X
X
X
X
X
X
X
X
X
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
L
L
L
L
X
L
L
L
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
H
X
L
None
L
H
H
X
L
None
X
H
X
L
None
X
X
X
X
X
Three-State
Q
External
External
H
H
L
L-H
READ Cycle, Begin Burst
L
L
H
L-H Three-State
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the signal. OE is asynchronous and is not sampled with the clock.
OE
6. CE , CE , and CE are available only in the TQFP package. BGA package has only two chip selects CE and CE .
1
2
3
1
2
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
X
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the Write cycle
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE is
OE
.
is active (LOW)
inactive or when the device is deselected, and all data bits behave as output when
Document #: 38-05540 Rev. *C
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CY7C1360C
CY7C1362C
PRELIMINARY
Truth Table (continued)[3, 4, 5, 6, 7, 8]
Address
Operation
Used
External
External
External
Next
CE2
H
H
H
X
CE3
L
WRITE
CLK
DQ
CE1
L
ZZ ADSP ADSC ADV
OE
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
X
L
L
X
L-H
D
L
L
L
L
H
H
H
H
H
H
L
L
H
L
L-H
Q
L
L
L-H Three-State
L-H
L-H Three-State
L-H
L-H Three-State
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
X
L
H
L
Next
X
L
Q
Next
X
L
H
X
X
L
Next
X
L
L-H
L-H
L-H
D
D
Q
Next
X
L
L
Current
Current
Current
Current
Current
Current
X
H
H
H
H
H
H
H
H
H
H
L
X
H
L
L-H Three-State
L-H
L-H Three-State
X
Q
X
H
X
X
X
L-H
L-H
D
D
X
L
Partial Truth Table for Read/Write[5, 9]
Function (CY7C1360C)
Read
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
BWB
BWA
X
H
L
X
H
H
H
H
L
X
H
H
L
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
L
L
H
L
L
L
Write Byte C – (DQC and DQPC)
Write Bytes C, A
L
H
H
L
H
L
L
L
Write Bytes C, B
L
L
H
L
Write Bytes C, B, A
Write Byte D – (DQD and DQPD)
Write Bytes D, A
L
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
Write Bytes D, B
L
L
H
L
Write Bytes D, B, A
Write Bytes D, C
L
L
L
L
L
H
H
L
H
L
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes
X
X
X
X
X
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
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CY7C1360C
CY7C1362C
PRELIMINARY
Truth Table for Read/Write[5, 9]
Function (CY7C1362C)
Read
GW
H
BWE
BWB
X
BWA
X
H
L
L
L
L
L
X
Read
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
H
H
L
H
L
H
H
L
L
Write All Bytes
H
L
L
Write All Bytes
L
X
X
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1360C/CY7C1362C incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1360C/CY7C1362C contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
Test Data-In (TDI)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See Tap Controller Block Diagram.)
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
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CY7C1360C
CY7C1362C
PRELIMINARY
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
TAP Controller Block Diagram
0
Bypass Register
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
2
1
0
0
0
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
S
election
TDI
TDO
Circuitr
y
.
.
. 2 1
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
x
.
.
.
.
. 2 1
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
TAP Instruction Set
Overview
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
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CY7C1360C
CY7C1362C
PRELIMINARY
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
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CY7C1360C
CY7C1362C
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Clock
tTCYC
tTF
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
25
25
tTL
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
5
ns
ns
0
5
5
5
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 3.3V
Input rise and fall times..................... ..............................1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels ........................................... VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels................... ......................1.25V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50W
50W
TDO
TDO
ZO= 50W
ZO= 50W
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted) [12]
Parameter
VOH1
Description
Conditions
VDDQ = 3.3V
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
Output HIGH Voltage IOH = –4.0 mA
I
OH = –1.0 mA
VDDQ = 2.5V
VDDQ = 3.3V
V
VOH2
Output HIGH Voltage IOH = –100 µA
V
VDDQ = 2.5V
V
VOL1
Output LOW Voltage IOL = 8.0 mA
IOL = 8.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
0.4
0.4
V
V
Notes:
10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1ns.
R
F
Document #: 38-05540 Rev. *C
Page 14 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted) (continued)[12]
Parameter
VOL2
Description
Conditions
VDDQ = 3.3V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
Min.
Max.
0.2
Unit
V
Output LOW Voltage IOL = 100 µA
V
0.2
V
VIH
VIL
IX
Input HIGH Voltage
Input LOW Voltage
2.0
1.7
VDD + 0.3
VDD + 0.3
0.7
V
V
V
–0.5
–0.3
–5
V
V
0.7
V
Input Load Current
GND < VIN < VDDQ
5
µA
Identification Register Definitions
CY7C1360C
CY7C1362C
(512KX18)
Instruction Field
Revision Number (31:29)
Device Depth (28:24)[13]
(256KX36)
Description
000
000
Describes the version number
Reserved for Internal Use
01011
01011
000000
010110
Device Width (23:18)
000000
100110
00000110100
1
Defines memory type and architecture
Defines width and density
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
00000110100 Allows unique identification of SRAM vendor
1
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction
Bypass
ID
3
3
1
1
32
71
71
32
71
71
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Notes:
12. All voltages referenced to V (GND).
SS
13. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.
Document #: 38-05540 Rev. *C
Page 15 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
AC Test Loads and Waveforms[14]
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
INCLUDING
V = 1.5V
T
JIG AND
SCOPE
(a)
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R =1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
Note:
14. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05540 Rev. *C
Page 16 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
165-Ball fBGA Boundary Scan Order
CY7C1360C (256K x 36)
Signal
CY7C1362C (512K x 18)
Signal
Signal
Name
Signal
Name
Bit#
1
Ball ID
B6
Name
CLK
GW
BWE
OE
Bit#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Ball ID
R6
P6
Name
Bit#
1
Ball ID
B6
Bit#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Ball ID
R6
A0
CLK
GW
A0
A1
2
B7
A1
2
B7
P6
3
A7
R4
P4
A
3
A7
BWE
OE
R4
A
4
B8
A
4
B8
P4
A
5
A8
ADSC
ADSP
ADV
A
R3
P3
A
5
A8
ADSC
ADSP
ADV
A
R3
A
6
B9
A
6
B9
P3
A
7
A9
R1
N1
L2
MODE
DQPD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
Internal
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQPC
A
7
A9
R1
MODE
Internal
Internal
Internal
Internal
DQPB
DQB
8
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
P10
R9
8
B10
Internal
Internal
Internal
Internal
N1
9
A
9
A10
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
ZZ
K2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A11
A
J2
Internal
Internal
Internal
C11
Internal
Internal
Internal
DQPA
DQA
DQA
DQA
DQA
ZZ
M2
M1
L1
M1
L1
DQB
K1
D11
K1
DQB
J1
E11
J1
DQB
Internal
G2
F2
F11
Internal
G2
Internal
DQB
G11
H11
F2
DQB
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQPA
A
E2
J10
DQA
DQA
DQA
DQA
Internal
Internal
Internal
Internal
Internal
A
E2
DQB
D2
G1
F1
K10
D2
DQB
L10
Internal
Internal
Internal
Internal
Internal
B2
Internal
Internal
Internal
Internal
Internal
A
M10
Internal
Internal
Internal
Internal
Internal
R11
E1
D1
C1
B2
A2
A3
A
A2
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
A3
CE1
A
B3
R10
P10
A
B3
CE2
A
B4
A
Internal
Internal
A4
Internal
Internal
BWB
BWA
CE3
A
A4
R9
A
P9
A
A5
P9
A
R8
A
B5
R8
A
B5
P8
A
A6
P8
A
A6
P11
A
P11
A
Document #: 38-05540 Rev. *C
Page 17 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
119-Ball BGA Boundary Scan Order
CY7C1360C (256K x 36)
Signal
CY7C1362C (512K x 18)
Signal
Signal
Name
Signal
Name
Bit# Ball ID Name
BIT# BALL ID
Name
Bit#
1
Ball ID
Bit#
37
38
39
40
41
42
43
44
Ball ID
P4
1
2
3
4
5
6
7
8
CLK
GW
37
38
39
40
41
42
43
44
P4
N4
R6
T5
T3
R2
R3
P2
A0
CLK
GW
A0
K4
H4
M4
F4
B4
A4
G4
C3
K4
H4
M4
F4
B4
A4
G4
C3
A1
2
N4
A1
BWE
OE
A
3
BWE
OE
R6
A
A
4
T5
A
A
ADSC
ADSP
ADV
A
A
5
ADSC
ADSP
ADV
A
T3
A
6
R2
A
MODE
DQPD
7
R3
MODE
Internal
8
Internal
9
B3
D6
H7
G6
E6
D7
E7
F6
G7
H6
T7
K7
L6
A
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
ZZ
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
P1
L2
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
Internal
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQPC
A
9
B3
T2
A
A
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Internal
Internal
Internal
P2
Internal
Internal
Internal
DQPB
DQB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
K1
Internal
Internal
Internal
D6
Internal
Internal
Internal
DQPA
DQA
DQA
DQA
DQA
ZZ
N2
N1
N1
M2
L1
M2
DQB
E7
L1
DQB
K2
F6
K2
DQB
Internal
H1
G7
Internal
H1
Internal
DQB
H6
G2
E2
T7
G2
DQB
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQPA
A
K7
DQA
DQA
DQA
DQA
Internal
Internal
Internal
Internal
Internal
A
E2
DQB
D1
L6
D1
DQB
N6
P7
N7
M6
L7
H2
N6
Internal
Internal
Internal
Internal
Internal
C2
Internal
Internal
Internal
Internal
Internal
A
G1
F2
P7
Internal
Internal
Internal
Internal
Internal
T6
E1
D2
K6
P6
T4
A3
C5
B5
A5
C6
C2
A2
A
A2
A
E4
CE1
E4
CE1
A
B2
CE2
A3
A
B2
CE2
A
L3
BWD
BWC
BWB
BWA
Internal
C5
A
Internal
Internal
G3
Internal
Internal
BWB
A
G3
G5
L5
B5
A
A
A5
A
A
C6
A
L5
BWA
35
36
A6
B6
A
A
Internal
35
36
A6
B6
A
A
Internal
Internal
Document #: 38-05540 Rev. *C
Page 18 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.....................................................> 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND ...... –0.5V to +4.6V
Range
Temperature
VDD
VDDQ
DC Voltage Applied to Outputs
in Three-State ....................................–0.5V to VDDQ + 0.5V
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
to VDD
Industrial
–40°C to +85°C
DC Input Voltage...................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range[15, 16]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
Unit
V
VDDQ
VDDQ = 3.3V
DDQ = 2.5V
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
DDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDD
V
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[15]
Input LOW Voltage[15]
V
V
2.0
V
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
0.4
0.4
V
V
2.0
1.7
VDD + 0.3V
VDD + 0.3V
0.8
V
V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
GND ≤ VI ≤ VDDQ
V
–0.3
–0.3
–5
V
V
0.7
V
Input Load Current
except ZZ and MODE
5
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
µA
30
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
µA
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
4.0-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
250
220
180
130
120
110
30
mA
mA
mA
mA
mA
mA
mA
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
ISB2
Automatic CE
Power-down
Current—CMOS Inputs f = 0
VDD = Max, Device Deselected, All speeds
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
ISB3
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX = 1/tCYC
VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz
120
110
100
40
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
ISB4
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected, All Speeds
VIN ≥ VIH or VIN ≤ VIL, f = 0
Shaded areas contain advance information.
Notes:
15. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
16. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05540 Rev. *C
Page 19 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Thermal Resistance[14]
100 TQFP
Package
119 BGA
Package
165 fBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient) methods and procedures for
Test conditions follow standard test
29.41
34.1
16.8
°C/W
measuring thermal impedance, per
EIA/JESD51.
ΘJC
Thermal Resistance
(Junction to Case)
6.13
14.0
3
°C/W
Capacitance[14]
100 TQFP
Package
119 BGA
165 fBGA
Package
Parameter
CIN
Description
Input Capacitance
Test Conditions
Package
Unit
pF
TA = 25°C, f = 1 MHz,
DD = 3.3V
DDQ = 2.5V
5
5
5
5
5
7
5
5
7
V
V
CCLK
Clock Input Capacitance
Input/Output Capacitance
pF
CI/O
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
INCLUDING
V = 1.5V
(a)
T
JIG AND
SCOPE
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R =1538Ω
≤ 1 ns
≤ 1 ns
INCLUDING
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Switching Characteristics Over the Operating Range [17, 18]
250 MHz
Min. Max
200 MHz
166 MHz
Min. Max
Parameter
tPOWER
Clock
Description
VDD(Typical) to the First Access[19]
Min.
Max
Unit
1
1
1
ms
tCYC
Clock Cycle Time
Clock HIGH
4.0
1.8
1.8
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCO
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
2.8
3.0
3.5
ns
ns
tDOH
1.25
1.25
1.25
Notes:
17. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
18. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05540 Rev. *C
Page 20 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[17, 18]
250 MHz
200 MHz
166 MHz
Parameter
tCLZ
Description
Clock to Low-Z[20, 21, 22]
Clock to High-Z[20, 21, 22]
Min.
1.25
1.25
Max
Min.
Max
Min.
1.25
1.25
Max
Unit
ns
1.25
1.25
tCHZ
2.8
2.8
3.0
3.0
3.5
3.5
ns
tOEV
OE LOW to Output Valid
ns
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low-Z[20, 21, 22]
OE HIGH to Output High-Z[20, 21, 22]
0
0
0
ns
2.8
3.0
3.5
ns
Address Set-up before CLK Rise
ADSC, ADSP Set-up before CLK Rise
ADV Set-up before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
tDS
tCES
Hold Times
tAH
Address Hold after CLK Rise
ADSP, ADSC Hold after CLK Rise
ADV Hold after CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
tADVH
tWEH
GW, BWE, BWX Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
tDH
tCEH
Shaded areas contain advance information.
Notes:
19. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a Read or Write operation
DD
POWER
can be initiated.
20. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
21. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
Document #: 38-05540 Rev. *C
Page 21 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Switching Waveforms
Read Cycle Timing[23]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BWx
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
OELZ
t
CHZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
23. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05540 Rev. *C
Page 22 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Switching Waveforms (continued)
Write Cycle Timing[23, 24]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
ADDRESS
BWE,
t
t
AH
AS
A1
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note:
24.
Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05540 Rev. *C
Page 23 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[23, 25, 26]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE,
t
t
WEH
WES
BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes:
25.
26. GW is HIGH.
ADSP or ADSC.
The data bus (Q) remains in high-Z following a Write cycle, unless a new Read access is initiated by
Document #: 38-05540 Rev. *C
Page 24 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Switching Waveforms (continued)
ZZ Mode Timing [27, 28]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Part and Package Type
250
CY7C1360C-250AXC
CY7C1362C-250AXC
A101
A101
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
CY7C1360C-250AXI
CY7C1362C-250AXI
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
CY7C1360C-250AJXC
CY7C1362C-250AJXC
CY7C1360C-250AJXI
CY7C1362C-250AJXI
CY7C1360C-250BGC
CY7C1362C-250BGC
CY7C1360C-250BGI
CY7C1362C-250BGI
CY7C1360C-250BZC
CY7C1362C-250BZC
CY7C1360C-250BZI
CY7C1362C-250BZI
CY7C1360C-250BGXC
CY7C1362C-250BGXC
CY7C1360C-250BGXI
CY7C1362C-250BGXI
CY7C1360C-250BZXC
CY7C1362C-250BZXC
CY7C1360C-250BZXI
CY7C1362C-250BZXI
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
Commercial
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
Industrial
Commercial
Industrial
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Commercial
Industrial
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and Commercial
JTAG
BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and Industrial
JTAG
BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial
3 Chip Enables and JTAG
BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Industrial
Notes:
27. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
28. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05540 Rev. *C
Page 25 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Ordering Information (continued)
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Part and Package Type
200
CY7C1360C-200AXC
CY7C1362C-200AXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
CY7C1360C-200AXI
CY7C1362C-200AXI
A101
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
CY7C1360C-200AJXC
CY7C1362C-200AJXC
CY7C1360C-200AJXI
CY7C1362C-200AJXI
CY7C1360C-200BGC
CY7C1362C-200BGC
CY7C1360C-200BGI
CY7C1362C-200BGI
CY7C1360C-200BZC
CY7C1362C-200BZC
CY7C1360C-200BZI
CY7C1362C-200BZI
CY7C1360C-200BGXC
CY7C1362C-200BGXC
CY7C1360C-200BGXI
CY7C1362C-200BGXI
CY7C1360C-200BZXC
CY7C1362C-200BZXC
CY7C1360C-200BZXI
CY7C1362C-200BZXI
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
Commercial
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
Industrial
Commercial
Industrial
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Commercial
Industrial
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and Commercial
JTAG
BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and Industrial
JTAG
BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial
3 Chip Enables and JTAG
BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Industrial
Document #: 38-05540 Rev. *C
Page 26 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Ordering Information (continued)
Speed
(MHz)
Package
Operating
Range
Ordering Code
CY7C1360C-166AXC
CY7C1362C-166AXC
CY7C1360C-166AXI
CY7C1362C-166AXI
CY7C1360C-166AJXC
CY7C1362C-166AJXC
CY7C1360C-166AJXI
CY7C1362C-166AJXI
CY7C1360C-166BGC
CY7C1362C-166BGC
CY7C1360C-166BGI
ICY7C1362C-166BGI
CY7C1360C-166BZC
CY7C1362C-166BZC
CY7C1360C-166BZI
ICY7C1362C-166BZI
CY7C1360C-166BGXC
CY7C1362C-166BGXC
CY7C1360C-166BGXI
ICY7C1362C-166BGXI
CY7C1360C-166BZXC
CY7C1362C-166BZXC
CY7C1360C-166BZXI
CY7C1362C-166BZXI
Name
Part and Package Type
166
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
A101
A101
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
Commercial
Industrial
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG
Commercial
Industrial
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Commercial
Industrial
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA
2 Chip Enables and JTAG
Commercial
Industrial
BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA
2 Chip Enables and JTAG
BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial
3 Chip Enables and JTAG
BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Industrial
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.
Document #: 38-05540 Rev. *C
Page 27 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
SEE DETAIL
A
(ꢀX)
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
0°-7°
0.60 0.ꢁ5
0.20 MIN.
ꢁ.00 REF.
51-85050-*A
DETAIL
A
Document #: 38-05540 Rev. *C
Page 28 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05540 Rev. *C
Page 29 of 31
CY7C1360C
CY7C1362C
PRELIMINARY
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 MM BB165D
51-85180-**
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05540 Rev. *C
Page 30 of 31
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1360C
CY7C1362C
PRELIMINARY
Document History Page
Document Title: CY7C1360C/CY7C1362C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
Document Number: 38-05540
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
241690
278130
See ECN
See ECN
RKF
RKF
New data sheet
*A
Changed Boundary Scan order to match the B rev of these devices.
Changed TQFP pkg to Lead-free TQFP in Ordering Information section
Added comment of Lead-free BG and BZ packages availability
*B
*C
248929
323636
See ECN
See ECN
VBL
PCI
Changed ISB1 and ISB3 from DC Characteristics table as follows:
ISB1: 225 MHz -> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA
ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA
Changed IDDZZ to 50mA.
Added BG and BZ pkg lead-free part numbers to ordering info section.
Changed frequency of 225 MHz into 250 MHz
Added tCYC of 4.0 ns for 250 MHz
Changed ΘJA and ΘJC for TQFP Package from 25 and 9 °C/W to 29.41 and
6.13 °C/W respectively
Changed ΘJA and ΘJC for BGA Package from 25 and 6 °C/W to 34.1 and
14.0 °C/W respectively
Changed ΘJA and ΘJC for FBGA Package from 27 and 6 °C/W to 16.8 and
3.0 °C/W respectively
Modified address expansion as per JEDEC Standard
Removed comment of Lead-free BG and BZ packages availability
Document #: 38-05540 Rev. *C
Page 31 of 31
相关型号：
CY7C1362C-166BGCT
Cache SRAM, 512KX18, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CYPRESS
CY7C1362C-166BZCT
Cache SRAM, 512KX18, 3.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
ROCHESTER
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