CY7C1363D [CYPRESS]
9-Mbit (512 K x 18) Flow-Through SRAM; 9兆位（ 512K的×18 ）流通型SRAM
| 型号： | CY7C1363D |
| 厂家： | 
CYPRESS |
| 描述： | 9-Mbit (512 K x 18) Flow-Through SRAM |
| 文件： | 总22页 (文件大小：755K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1363D
9-Mbit (512 K × 18) Flow-Through SRAM
9-Mbit (512
K × 18) Flow-Through SRAM
Features
Functional Description
■ Supports 133 MHz bus operations
■ 512 K × 18 common I/O
The CY7C1363D is a 3.3 V, 512 K × 18 synchronous flow-through
SRAM, respectively designed to interface with high speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
chip enable (CE1), depth-expansion chip enables (CE2 and
CE3[1]), burst control inputs (ADSC, ADSP, and ADV), write
enables (BWx, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
■ 3.3 V – 5% and +10% core power supply (VDD
)
■ 2.5 V or 3.3 V I/O power supply (VDDQ
)
■ Fast clock-to-output times
❐ 6.5 ns (133-MHz version)
■ Provide high performance 2-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
The CY7C1363D enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ TQFP available with 3-chip enable
■ “ZZ” sleep mode option
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The CY7C1363D operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
Selection Guide
Description
Maximum access time
133 MHz Unit
6.5
250
40
ns
Maximum operating current
mA
mA
Maximum CMOS standby current
Industrial
Note
1. CE is for A version of 100-pin TQFP (3 Chip Enable Option).
3
Cypress Semiconductor Corporation
Document Number: 001-86215 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 20, 2013
CY7C1363D
Logic Block Diagram – CY7C1363D
ADDRESS
REGISTER
A0,A1,A
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,DQP B
DQ
B,DQP B
WRITE DRIVER
WRITE REGISTER
BW
B
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQP A
DQ A,DQP A
WRITE REGISTER
WRITE DRIVER
BW
A
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
1
2
3
CE
OE
SLEEP
CONTROL
ZZ
Document Number: 001-86215 Rev. **
Page 2 of 22
CY7C1363D
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................5
Functional Overview ........................................................6
Single Read Accesses ................................................6
Single Write Accesses Initiated by ADSP ...................6
Single Write Accesses Initiated by ADSC ...................7
Burst Sequences .........................................................7
Interleaved Burst Address Table .................................7
Linear Burst Address Table .........................................7
Sleep Mode .................................................................7
ZZ Mode Electrical Characteristics ..............................7
Truth Table ........................................................................8
Partial Truth Table for Read/Write ..................................9
Maximum Ratings ...........................................................10
Operating Range .............................................................10
Neutron Soft Error Immunity .........................................10
Electrical Characteristics ...............................................10
Capacitance ....................................................................11
Thermal Resistance ........................................................11
AC Test Loads and Waveforms .....................................12
Switching Characteristics ..............................................13
Timing Diagrams ............................................................14
Ordering Information ......................................................18
Ordering Code Definitions .........................................18
Package Diagrams ..........................................................19
Acronyms ........................................................................20
Document Conventions .................................................20
Units of Measure .......................................................20
Document History Page .................................................21
Sales, Solutions, and Legal Information ......................22
Worldwide Sales and Design Support .......................22
Products ....................................................................22
PSoC Solutions .........................................................22
Document Number: 001-86215 Rev. **
Page 3 of 22
CY7C1363D
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enables - A version)
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1363D
(512 K × 18)
NC
VSS
VDD
ZZ
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
Document Number: 001-86215 Rev. **
Page 4 of 22
CY7C1363D
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK
synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2] are sampled active. A[1:0] feed the 2-bit
counter.
BWA,BWB
GW
Input-
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
synchronous on the rising edge of CLK.
Input-
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write is
synchronous conducted (all bytes are written, regardless of the values on BWX and BWE).
CLK
Input-
clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
Input-
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
Input-
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3[2] to select/deselect the device. CE2 is sampled only when a new external address is loaded.
[2]
CE3
Input- Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded.
Input- Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
OE
asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins.
OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Advance input signal, sampled on the rising edge of CLK. When asserted, it automatically
synchronous increments the address in a burst cycle.
ADSP
Input-
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when
is deasserted HIGH.
CE1
ADSC
Input-
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
BWE
ZZ
Input-
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
synchronous LOW to conduct a byte write.
Input-
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
I/O-
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
DQs
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
I/O-
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
DQPX
synchronous sequences, DQPX is controlled by BWX correspondingly.
MODE
Input-
static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode Pin has an internal pull-up.
VDD
Power supply Power supply inputs to the core of the device.
Note
2. CE is for A version of 100-pin TQFP (3 Chip Enable Option).
3
Document Number: 001-86215 Rev. **
Page 5 of 22
CY7C1363D
Pin Definitions (continued)
Name
VDDQ
I/O
Description
I/O power Power supply for the I/O circuitry.
supply
VSS
VSSQ
NC
Ground
Ground for the core of the device.
I/O ground Ground for the I/O circuitry.
–
No connects. Not internally connected to the die. 18M, 36M, 72M, 144M, 288M, 576M, and 1G are
address expansion pins and are not internally connected to the die.
VSS/DNU
Ground/DNU This pin can be connected to ground or should be left floating.
Single Read Accesses
Functional Overview
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCDV) is 6.5 ns (133 MHz device).
[3]
asserted active and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deasserted
during this first cycle). The address presented to the address
inputs is latched into the address register and the burst
counter/control logic and presented to the memory core. If the
OE input is asserted LOW, the requested data will be available
at the data outputs a maximum to tCDV after clock rise. ADSP is
ignored if CE1 is HIGH.
The CY7C1363D supports secondary cache in systems using
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486™ processors. The linear
burst sequence is suited for processors that use a linear burst
sequence. The burst order is user-selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the processor address strobe (ADSP) or the controller
address strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3[3] are all asserted active
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX) are ignored during this first clock cycle. If the write
inputs are asserted active (see Partial Truth Table for Read/Write
on page 11 for appropriate states that indicate a write) on the
next clock rise, the appropriate data will be latched and written
into the device.Byte writes are allowed. All I/Os are tristated
during a byte write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the I/Os
must be tristated prior to the presentation of data to DQs. As a
safety precaution, the data lines are tristated once a write cycle
is detected, regardless of the state of OE.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3[3]) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Note
3. CE is for A version of 100-pin TQFP (3 Chip Enable Option).
3
Document Number: 001-86215 Rev. **
Page 6 of 22
CY7C1363D
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3[4] are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQ[A:B] is written into the
specified address location. Byte writes are allowed. All I/Os are
tristated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tristated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tristated once a write cycle is detected, regardless of
the state of OE.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
Burst Sequences
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
The CY7C1363D provides an on-chip two-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0], and
can follow either a linear or interleaved burst order. The burst
order is determined by the state of the MODE input. A LOW on
MODE will select a linear burst sequence. A HIGH on MODE
selects an interleaved burst order. Leaving MODE unconnected
causes the device to default to a interleaved burst sequence.
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation ‘sleep’ mode. Two clock
cycles are required to enter into or exit from this ‘sleep’ mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the ‘sleep’ mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the ‘sleep’ mode. CE1, CE2,
CE3[4], ADSP, and ADSC must remain inactive for the duration
of tZZREC after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Test Conditions
Industrial
Min
Max
Unit
Sleep mode standby current
ZZ > VDD– 0.2 V
–
50
mA
tZZS
Device operation to ZZ
ZZ recovery time
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
2tCYC
–
2tCYC
–
ns
ns
ns
ns
tZZREC
tZZI
ZZ active to sleep current
This parameter is sampled
2tCYC
–
tRZZI
ZZ Inactive to exit sleep current This parameter is sampled
0
Note
4. CE is for A version of 100-pin TQFP (3 Chip Enable Option).
3
Document Number: 001-86215 Rev. **
Page 7 of 22
CY7C1363D
Truth Table
The Truth Table for CY7C1363D follows. [5, 6, 7, 8, 9]
Cycle Description
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselected cycle, power-down
Deselected cycle, power-down
Deselected cycle, power-down
Deselected cycle, power-down
Deselected cycle, power-down
Sleep mode, power-down
Read cycle, begin burst
None
None
H
L
X
L
X
X
H
X
X
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L–H Tri-state
L–H Tri-state
L–H Tri-state
L–H Tri-state
L–H Tri-state
None
L
X
L
L
None
L
H
H
X
L
None
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
X
Tri-state
Q
External
External
External
External
External
Next
L–H
Read cycle, begin burst
L
L
L
H
X
L
L–H Tri-state
D
Q
Write cycle, begin burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L–H
L–H
Read cycle, begin burst
L
L
L
H
H
H
H
H
H
L
Read cycle, begin burst
L
L
L
H
L
L–H Tri-state
Q
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Write cycle, continue burst
Write cycle, continue burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Write cycle, suspend burst
Write cycle, suspend burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
L–H
L–H Tri-state
L–H
L–H Tri-state
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L–H
L–H
L–H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L–H Tri-state
L–H
L–H Tri-state
Q
H
X
X
L–H
L–H
D
D
L
Notes
5. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
6. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
7. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
8. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after
X
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care
for the remainder of the write cycle.
9. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-86215 Rev. **
Page 8 of 22
CY7C1363D
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1363D follows. [10, 11]
GW
H
BWE
BWB
X
BWA
X
Function (CY7C1363D)
Read
Read
H
L
L
L
L
X
H
H
H
Write byte A – (DQA and DQPA)
Write byte B – (DQB and DQPB)
Write all bytes
H
H
L
H
L
H
H
L
L
Write all bytes
L
X
X
Notes
10. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
11. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.
X
Document Number: 001-86215 Rev. **
Page 9 of 22
CY7C1363D
Maximum Ratings
Operating Range
Ambient
Temperature
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Range
VDD
VDDQ
Industrial
–40 °C to +85 °C 3.3 V– 5% / 2.5 V – 5% to
Storage temperature ............................... –65 °C to + 150 °C
+ 10%
VDD
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Neutron Soft Error Immunity
Supply voltage on VDD relative to GND ......–0.5 V to + 4.6 V
Supply voltage on VDDQ relative to GND ..... –0.5 V to + VDD
Test
Parameter Description
Conditions
Typ Max* Unit
DC voltage applied to outputs
in tri-state ..........................................–0.5 V to VDDQ + 0.5 V
LSBU
LMBU
SEL
Logical
single-bit
upsets
25 °C
25 °C
85 °C
361 394
FIT/
Mb
DC input voltage .................................–0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Logical
multi-bit
upsets
0
0
0.01 FIT/
Mb
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Single event
latch up
0.1
FIT/
Dev
Latch-up current ................................................... > 200 mA
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”
Electrical Characteristics
Over the Operating Range
Parameter [12, 13]
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
Unit
V
VDD
3.6
VDDQ
for 3.3 V I/O
for 2.5 V I/O
VDD
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH voltage[12]
Input LOW voltage[12]
for 3.3 V I/O, IOH =4.0 mA
for 2.5 V I/O, IOH =1.0 mA
for 3.3 V I/O, IOL=8.0 mA
for 2.5 V I/O, IOL= 1.0 mA
for 3.3 V I/O
–
V
2.0
–
0.4
V
–
V
–
0.4
V
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
V
DD + 0.3 V
V
for 3.3 V I/O
–0.3
–0.3
–5
0.8
0.7
5
V
for 2.5 V I/O
V
Input leakage current except ZZ GND VI VDDQ
and MODE
A
Input current of MODE
Input = VSS
–30
–
–
5
A
A
A
A
A
Input = VDD
Input current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
Output leakage current
GND < VI < VDDQ, output disabled
–5
Notes
12. Overshoot: V
< V + 1.5 V (Pulse width less than t
/2), undershoot: V
> –2 V (Pulse width less than t
/2).
IH(AC)
DD
CYC
IL(AC)
CYC
13. T
: Assumes a linear ramp from 0 V to V
within 200 ms. During this time V < V and V
V
.
Power-up
DD(min)
IH
DD
DDQ
DD
Document Number: 001-86215 Rev. **
Page 10 of 22
CY7C1363D
Electrical Characteristics (continued)
Over the Operating Range
Parameter [12, 13]
Description
Test Conditions
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
Min
Max
Unit
IDD
VDD operating supply current
7.5 ns cycle,
133 MHz
–
250
mA
ISB1
ISB2
ISB3
ISB4
Automatic CE power-down
current – TTL inputs
Max VDD, device deselected,
VIN> VIH or VIN < VIL, f = fMAX, 133 MHz
inputs switching
7.5 ns cycle,
–
–
–
–
110
40
mA
mA
mA
mA
Automatic CE power-down
current – CMOS inputs
Max VDD, device deselected,
7.5 ns cycle,
VIN > VDD – 0.3 V or VIN < 0.3 V, 133 MHz
f = 0, inputs static
Automatic CE power-down
current – CMOS inputs
Max VDD, device deselected,
7.5 ns cycle,
100
40
VIN > VDDQ – 0.3 V or VIN < 0.3 V, 133 MHz
f = fMAX, inputs switching
Automatic CE power-down
current – TTL inputs
Max VDD, device deselected,
7.5 ns cycle,
133 MHz
VIN > VIH or VIN < VIL,
f = 0, inputs static
Capacitance
100-pin TQFP
Max
Parameter [14]
Description
Test Conditions
Unit
CIN
Input capacitance
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
5
5
5
pF
pF
pF
CCLK
CI/O
Clock input capacitance
Input/output capacitance
Thermal Resistance
100-pin TQFP
Package
Parameter [14]
Description
Test Conditions
Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and proce-
dures for measuring thermal impedance, according to
EIA/JESD51
29.41
°C/W
JC
Thermal resistance
(junction to case)
6.31
°C/W
Note
14. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-86215 Rev. **
Page 11 of 22
CY7C1363D
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
R = 50
10%
L
GND
5 pF
R = 351
1 ns
1 ns
INCLUDING
JIG AND
SCOPE
V
= 1.5 V
T
(a)
2.5 V I/O Test Load
(b)
(c)
R = 1667
2.5 V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50
0
R = 50
10%
L
GND
5 pF
R = 1538
1 ns
1 ns
V
= 1.25 V
T
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
Document Number: 001-86215 Rev. **
Page 12 of 22
CY7C1363D
Switching Characteristics
Over the Operating Range
-133
Parameter [15, 16]
Description
VDD(typical) to the first access [17]
Unit
Min
Max
tPOWER
Clock
tCYC
1
–
ms
Clock cycle time
Clock HIGH
7.5
3.0
3.0
–
–
–
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z [18, 19, 20]
–
2.0
0
6.5
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
tCHZ
Clock to high Z [18, 19, 20]
–
3.5
3.5
–
tOEV
OE LOW to output valid
–
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to output low Z [18, 19, 20]
OE HIGH to output high Z [18, 19, 20]
0
–
3.5
Address setup before CLK rise
ADSP, ADSC setup before CLK rise
ADV setup before CLK rise
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BW[A:B] setup before CLK rise
Data input setup before CLK rise
Chip enable setup
tDS
tCES
Hold Times
tAH
Address hold after CLK rise
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
ADSP, ADSC hold after CLK rise
GW, BWE, BW[A:B] hold after CLK rise
ADV hold after CLK rise
tWEH
tADVH
tDH
Data input hold after CLK rise
Chip enable hold after CLK rise
tCEH
Notes
15. Timing reference level is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
16. Test conditions shown in (a) of Figure 2 on page 12 unless otherwise noted.
17. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V
initially, before a read or write operation can
POWER
DD(minimum)
be initiated.
18. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of Figure 2 on page 12. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
19. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
OEHZ
OELZ
CHZ
CLZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
Document Number: 001-86215 Rev. **
Page 13 of 22
CY7C1363D
Timing Diagrams
Figure 3. Read Cycle Timing [21]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
X
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2
+
2)
Q(A2
+
3)
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
21. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document Number: 001-86215 Rev. **
Page 14 of 22
CY7C1363D
Timing Diagrams (continued)
Figure 4. Write Cycle Timing [22, 23]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BWX
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Notes
22. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
23.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document Number: 001-86215 Rev. **
Page 15 of 22
CY7C1363D
Timing Diagrams (continued)
Figure 5. Read/Write Cycle Timing [24, 25, 26]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
Notes
24. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
25. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
26.
GW is HIGH.
Document Number: 001-86215 Rev. **
Page 16 of 22
CY7C1363D
Timing Diagrams (continued)
Figure 6. ZZ Mode Timing [27, 28]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
27. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
28. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-86215 Rev. **
Page 17 of 22
CY7C1363D
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your
local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary
page at http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
133 CY7C1363D-133AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free (3 Chip Enable)
lndustrial
Ordering Code Definitions
X
CY
7
C
1363
D
-
133
A
I
Temperature Range:
I = Industrial
Pb-free
Package Type:
A = 100-pin TQFP (3 Chip Enable)
Speed Grade: 133 MHz
Process Technology: D 90 nm
Part Identifier:
1363 = FT, 512 Kb × 18 (9 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-86215 Rev. **
Page 18 of 22
CY7C1363D
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 001-86215 Rev. **
Page 19 of 22
CY7C1363D
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BGA
CMOS
CE
ball grid array
Symbol
°C
Unit of Measure
complementary metal oxide semiconductor
chip enable
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
millivolt
MHz
µA
mA
mm
ms
mV
ns
EIA
electronic industries alliance
fine-pitch ball grid array
input/output
FBGA
I/O
JEDEC
LMBU
LSB
joint electron devices engineering council
logical multi-bit upsets
least significant bit
nanosecond
ohm
LSBU
MSB
OE
logical single-bit upsets
most significant bit
%
percent
output enable
pF
V
picofarad
volt
PBGA
SEL
plastic ball grid array
single event latch up
W
watt
SRAM
TQFP
TTL
static random access memory
thin quad flat pack
transistor-transistor logic
Document Number: 001-86215 Rev. **
Page 20 of 22
CY7C1363D
Document History Page
Document Title: CY7C1363D, 9-Mbit (512 K × 18) Flow-Through SRAM
Document Number: 001-86215
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
3908991
02/20/2013
PRIT
New data sheet.
Document Number: 001-86215 Rev. **
Page 21 of 22
CY7C1363D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-86215 Rev. **
Revised February 20, 2013
Page 22 of 22
All products and company names mentioned in this document may be the trademarks of their respective holders.
相关型号：
CY7C1364C-166AXCT
Cache SRAM, 256KX32, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
CYPRESS
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