CY7C1364C-250AXI [CYPRESS]
9-Mbit (256K x 32) Pipelined Sync SRAM; 9兆位（ 256K ×32）流水线同步SRAM的
| 型号： | CY7C1364C-250AXI |
| 厂家： | 
CYPRESS |
| 描述： | 9-Mbit (256K x 32) Pipelined Sync SRAM |
| 文件： | 总18页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1364C
9-Mbit (256K x 32) Pipelined Sync SRAM
Features
Functional Description[1]
• Registered inputs and outputs for pipelined operation
• 256K × 32 common I/O architecture
The CY7C1364C SRAM integrates 256K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
• 3.3V core power supply (VDD
)
• 2.5V/3.3V I/O power supply (VDDQ
)
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW when active
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• “ZZ” Sleep Mode Option
causes all bytes to be written.
LOW
The CY7C1364C operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram-CY7C1364C (256K x 32)
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D
DQ
BYTE
WRITE DRIVER
D
BW
D
DQ
BYTE
C
DQ
BYTE
C
BW
C
OUTPUT
BUFFERS
WRITE DRIVER
OUTPUT
REGISTERS
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
DQ s
DQ
B
E
DQ
B
BYTE
WRITE DRIVER
BYTE
WRITE REGISTER
BW
BW
B
A
DQ
A
DQ
A
BYTE
WRITE DRIVER
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE is not available on 2 Chip Enable TQFP package.
3
Cypress Semiconductor Corporation
Document #: 38-05689 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 14, 2006
[+] Feedback
CY7C1364C
Selection Guide
250 MHz
2.8
200 MHz
3.0
166 MHz
Unit
ns
Maximum Access Time
3.5
180
40
Maximum Operating Current
Maximum CMOS Standby Current
250
220
mA
mA
40
40
Pin Configuration
100-Pin TQFP Pinout (2 Chip Enables) (AJ version)
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
BYTE C
BYTE B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
VSS
CY7C1364C
NC
VDD
ZZ
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
BYTE D
BYTE A
Document #: 38-05689 Rev. *E
Page 2 of 18
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CY7C1364C
Pin Configuration (continued)
100-Pin TQFP Pinout (3 Chip Enables) (A version)
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
BYTE C
BYTE B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
VSS
CY7C1364C
NC
VDD
ZZ
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
BYTE D
BYTE A
Document #: 38-05689 Rev. *E
Page 3 of 18
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CY7C1364C
Pin Definitions
Name
TQFP
I/O
Description
Address Inputs used to select one of the 256K address locations.
A0, A1, A
37, 36, 32, 33, 34, 35, 43,
Input-
44, 45, 46, 47, 48, 49, 50, Synchronous Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW,
81, 82, 99, 100
and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
BWA, BWB
BWC, BWD
93, 94, 95, 96
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct
Synchronous byte writes to the SRAM. Sampled on the rising edge of CLK.
GW
88
Input- Global Write Enable Input, active LOW. When asserted LOW on the
Synchronous rising edge of CLK, a global Write is conducted (ALL bytes are written,
regardless of the values on BW[A:D] and BWE).
BWE
CLK
87
89
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of
Synchronous CLK. This signal must be asserted LOW to conduct a Byte Write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also
used to increment the burst counter when ADV is asserted LOW, during
a burst operation.
CE1
98
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE2 and CE3 to select/deselect the device.
ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new
external address is loaded.
CE2
CE3
97
92
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.
and to select/deselect the device.
CE2 is sampled only when a new external address is loaded.
Synchronous Used in conjunction with
CE1
CE3
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.
(for 3 Chip Enable Version) Synchronous Used in conjunction with CE1 and CE2 to select/deselect the
device.CE3 is assumed active throughout this document for BGA. CE3
is sampled only when a new external address is loaded.
OE
86
Input-
Output Enable, asynchronous input, active LOW. Controls the
Asynchronous direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OEis masked during the first clock of a Read cycle when emerging
from a deselected state.
ADV
83
84
Input-
Advance Input signal, sampled on the rising edge of CLK, active
Synchronous LOW. Whenasserted, itautomatically increments the address in a burst
cycle.
ADSP
Input-
Synchronous CLK, active LOW. When asserted LOW, A is captured in the address
registers. A[1:0] are also loaded into the burst counter. When and
Address Strobe from Processor, sampled on the rising edge of
ADSP
ADSC are both asserted, only ADSP is recognized. ASDP is ignored
when CE1 is deasserted HIGH.
ADSC
ZZ
85
Input-
Address Strobe from Controller, sampled on the rising edge of
Synchronous CLK, active LOW. When asserted LOW, A is captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
64
Input-
ZZ “sleep” Input, active HIGH. This input, when High places the
Asynchronous device in a non-time-critical “sleep” condition with data integrity
preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
DQs
52, 53, 56, 57, 58, 59, 62,
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data
63, 68, 69, 72, 73, 74, 75, Synchronous register that is triggered by the rising edge of CLK. As outputs, they
78, 79, 2, 3, 6, 7, 8, 9, 12,
13, 18, 19, 22, 23, 24, 25,
28, 29
deliver the data contained in the memory location specified by “A”
during the previous clock rise of the Read cycle. The direction of the
pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQ are placed in a tri-state condition.
VDD
VSS
15, 41, 65, 91
17, 40, 67, 90
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the core of the device.
Document #: 38-05689 Rev. *E
Page 4 of 18
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CY7C1364C
Pin Definitions (continued)
Name
VDDQ
TQFP
I/O
Description
4, 11, 20, 27, 54, 61, 70, 77 I/O Power Power supply for the I/O circuitry.
Supply
VSSQ
5, 10, 21, 26, 55, 60, 71, 76 I/O Ground Ground for the I/O circuitry.
MODE
31
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
This is a strap pin and should remain static during device operation.
Mode pin has an internal pull-up.
NC
1, 14, 16, 30, 38, 39, 42,
51, 66, 80
No Connects. Not internally connected to the die
Single Write Accesses Initiated by ADSP
Functional Overview
This access is initiated when both of the following conditions
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the RAM
array. The Write signals (GW, BWE, and BW[A:D]) and ADV
inputs are ignored during this first cycle.
The CY7C1364C supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BW[A:D]
signals. The CY7C1364C provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW[A:D]) input, will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Because the CY7C1364C is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQ are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BW[A:D]) are asserted active to conduct a Write to
the desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQ is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE1 is HIGH. The address presented to the address inputs
(A) is stored into the address advancement logic and the
address register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the output registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within tCO if OE is active LOW. The only
exception occurs when the SRAM is emerging from a
deselected state to a selected state, its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE signal.
Consecutive single Read cycles are supported. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will tri-state immediately.
Because the CY7C1364C is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Document #: 38-05689 Rev. *E
Page 5 of 18
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CY7C1364C
Burst Sequences
Interleaved Burst Address Table
(MODE = Floating or VDD
)
The CY7C1364C provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
First
Address
A[1:0]
Second
Address
A[1:0]
Third
Address
A[1:0]
Fourth
Address
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Linear Burst Address Table (MODE = GND)
Sleep Mode
First
Address
A[1:0]
Second
Address
A[1:0]
Third
Address
A[1:0]
Fourth
Address
A[1:0]
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
returns LOW
.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
Unit
mA
ns
50
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ recovery time
ZZ < 0.2V
2tCYC
0
ns
ZZ Active to Sleep current
ZZ Inactive to exit Sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ns
Document #: 38-05689 Rev. *E
Page 6 of 18
[+] Feedback
CY7C1364C
Truth Table[3, 4, 5, 6, 7, 8]
Address
Next Cycle
Unselected
Used
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
CE3
X
H
X
H
X
L
CE2
X
X
L
CE1
H
L
ADSP
X
ADSC
L
ADV
X
X
X
X
X
X
X
L
OE
X
X
X
X
X
X
X
H
L
DQ
Write
None
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
DQ
X
Unselected
None
L
X
X
Unselected
None
L
L
X
X
Unselected
None
X
L
L
H
H
L
L
X
Unselected
None
L
L
X
Begin Read
External
External
Next
H
H
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
X
X
Begin Read
L
L
H
H
H
X
L
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
X
X
X
X
X
X
X
X
X
X
L
X
X
H
H
X
X
H
H
X
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
Next
L
Next
L
H
L
Tri-State
DQ
Next
X
L
Current
Current
Current
Current
Current
Current
External
Next
H
H
X
H
H
H
H
H
H
X
H
H
H
H
X
H
L
Tri-State
DQ
H
L
Tri-State
DQ
X
H
X
X
X
X
X
X
X
X
X
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Begin Write
Begin Write
H
H
X
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “Sleep”
X
X
X
X
X
X
H
X
H
X
Next
Current
Current
None
H
X
X
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals (BW ,BW ,BW ,BW and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
)
D
A
B
C
(BW ,BW ,BW ,BW
5. The DQ pins are controlled by the current cycle and the
,
.
),
D
BWE
=
A
B
C
GW
H
signal.
is asynchronous and is not sampled with the clock.
OE
OE
6. CE , CE , and CE are available only in the TQFP package.
1
2
3
7. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A:D]
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05689 Rev. *E
Page 7 of 18
[+] Feedback
CY7C1364C
Truth Table for Read/Write[3, 4]
Function
Read
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
BWA
X
H
L
X
H
H
L
Read
Write Byte A – DQA
Write Byte B – DQB
Write Bytes B, A
Write Byte C – DQC
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – DQD
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
H
L
L
L
L
H
H
L
H
L
L
L
L
L
H
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
L
L
H
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes
X
X
X
X
X
Document #: 38-05689 Rev. *E
Page 8 of 18
[+] Feedback
CY7C1364C
DC Input Voltage................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW) .........................................20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current ..................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........–0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND...... –0.5V to +VDD
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VDD
VDDQ
3.3V –
5%/+10%
2.5V – 5% to
VDD
DC Voltage Applied to Outputs
in tri-state.............................................–0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range [9, 10]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
Max.
Unit
V
3.135
3.135
2.375
2.4
3.6
VDD
VDDQ
for 3.3 V I/O
for 2.5V I/O
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[9]
Input LOW Voltage[9]
for 3.3 V I/O, IOH = –4.0 mA
for 2.5V I/O, IOH = –1.0 mA
for 3.3 V I/O, IOL = 8.0 mA
for 2.5V I/O, IOL = 1.0 mA
for 3.3 V I/O
V
2.0
V
0.4
0.4
V
V
2.0
1.7
VDD + 0.3V
V
for 2.5V I/O
V
DD + 0.3V
V
for 3.3 V I/O
–0.3
–0.3
–5
0.8
0.7
5
V
for 2.5V I/O
V
Input Leakage Current GND ≤ VI ≤ VDDQ
except ZZ and MODE
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
µA
30
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
µA
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
250
220
180
130
120
110
40
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max., Device Deselected, 4-ns cycle, 250 MHz
VIN ≥ VIH or VIN ≤ VIL,
f = fMAX = 1/tCYC
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
ISB2
Automatic CE
Power-down
Current—CMOS Inputs f = 0
VDD = Max., Device Deselected, All speeds
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
mA
mA
ISB3
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX = 1/tCYC
VDD = Max., Device Deselected, 4-ns cycle, 250 MHz
or VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
120
110
100
40
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
ISB4
Automatic CE
VDD = Max., Device Deselected, All speeds
mA
Power-down
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL,
f = 0
Notes:
9. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
10. T
: Assumes a linear ramp from 0Vv to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05689 Rev. *E
Page 9 of 18
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CY7C1364C
Capacitance[11]
100 TQFP
Parameter
Description
Input Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz,
5
5
5
pF
pF
pF
VDD = 3.3V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
VDDQ = 2.5V
Thermal Resistance[11]
Parameter
Description
Test Conditions
100 TQFP Package
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
29.41
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
6.13
°C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
INCLUDING
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
(a)
T
JIG AND
SCOPE
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R =1538Ω
≤ 1 ns
≤ 1 ns
INCLUDING
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Note:
11. Tested initially and after any design or process change that may affect these parameters
Document #: 38-05689 Rev. *E
Page 10 of 18
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CY7C1364C
Switching Characteristics Over the Operating Range[12,13]
–250
Min.
–200
Min.
–166
Parameter
tPOWER
Description
VDD(Typical) to the First Access[14]
Max.
Max.
Min.
Max.
Unit
1
1
1
ms
Clock
tCYC
Clock Cycle Time
Clock HIGH
4.0
1.8
1.8
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCO
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z[15, 16, 17]
2.8
3.0
3.5
ns
ns
ns
ns
ns
ns
ns
tDOH
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
tCLZ
tCHZ
Clock to High-Z[15, 16, 17]
2.8
2.8
3.0
3.0
3.5
3.5
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low-Z[15, 16, 17]
OE HIGH to Output High-Z[15, 16, 17]
0
0
0
2.8
3.0
3.5
Address Set-up before CLK Rise
1.25
1.25
1.25
1.25
1.25
1.25
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tADS
ADSC, ADSP Set-up before CLK Rise
tADVS
tWES
ADV Set-up before CLK Rise
GW, BWE, BW[A:D] Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-up before CLK Rise
tDS
tCES
Hold Times
tAH
Address Hold after CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
ADSP, ADSC Hold after CLK Rise
ADV Hold after CLK Rise
tADVH
tWEH
GW, BWE, BW[A:D] Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
tDH
tCEH
Notes:
12. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
13. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
14. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V minimum initially before a Read or Write operation
POWER
DD
can be initiated.
15. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
16. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document #: 38-05689 Rev. *E
Page 11 of 18
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CY7C1364C
Switching Waveforms
Read Cycle Timing[18]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BW[A:D]
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
t
CHZ
OELZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
Note:
18. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05689 Rev. *E
Page 12 of 18
[+] Feedback
CY7C1364C
Switching Waveforms (continued)
Write Cycle Timing[18,19]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A :D]
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note:
19.
Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW.
[A:D]
Document #: 38-05689 Rev. *E
Page 13 of 18
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CY7C1364C
Switching Waveforms (continued)
Read/Write Cycle Timing[18,20, 21]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE,
BW[A:D]
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes:
20. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
21. GW is HIGH.
Document #: 38-05689 Rev. *E
Page 14 of 18
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CY7C1364C
Switching Waveforms (continued)
ZZ Mode Timing[22, 23]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
23. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05689 Rev. *E
Page 15 of 18
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CY7C1364C
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
166
200
250
CY7C1364C-166AXC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
Commercial
CY7C1364C-166AJXC
CY7C1364C-166AXI
CY7C1364C-166AJXI
CY7C1364C-200AXC
CY7C1364C-200AJXC
CY7C1364C-200AXI
CY7C1364C-200AJXI
CY7C1364C-250AXC
CY7C1364C-250AJXC
CY7C1364C-250AXI
CY7C1364C-250AJXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
Industrial
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
Commercial
Industrial
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
Commercial
Industrial
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
Document #: 38-05689 Rev. *E
Page 16 of 18
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CY7C1364C
Package Diagram
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
1.40 0.05
14.00 0.10
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
0.25
1. JEDEC STD REF MS-026
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05689 Rev. *E
Page 17 of 18
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1364C
Document History Page
Document Title: CY7C1364C 9-Mbit (256K x 32) Pipelined Sync SRAM
Document Number: 38-05689
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
286269
320834
See ECN
See ECN
PCI
PCI
New data sheet
Changed 225 MHz into 250 MHz
*A
Changed ΘJA and ΘJC for TQFP from 25 and 9 °C/W to 29.41 and 6.13 °C/W
respectively
Modified VOL, VOH test conditions
Added Industrial Operating Range
Changed Snooze to Sleep in the ZZ Mode Electrical Characteristics
Shaded 250 MHz speed bin in the AC/DC table and Selection Guide
Added AJXC package in the Ordering Information
Updated Ordering Information Table
*B
*C
377095
408725
See ECN
See ECN
PCI
Changed ISB2 from 30 to 40 mA
Modified test condition in note# 9 from VIH < VDD to VIH < VDD
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed three-state to tri-state
Converted from Preliminary to Final
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the ordering information
*D
*E
429278
501828
See ECN
See ECN
NXR
VKN
Added 2.5 V I/O option
Included 2 Chip Enable Pinout
Updated Ordering Information Table
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Updated the Ordering Information table.
Document #: 38-05689 Rev. *E
Page 18 of 18
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