CY7C136E-55NXC [CYPRESS]
1 K / 2 K Ã 8 Dual-port Static RAM; 1 K / 2 K A ？ 8双端口静态RAM
| 型号： | CY7C136E-55NXC |
| 厂家： | 
CYPRESS |
| 描述： | 1 K / 2 K Ã 8 Dual-port Static RAM |
| 文件： | 总19页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
1 K / 2 K × 8 Dual-port Static RAM
1
K / 2 K × 8 Dual-port Static RAM
Features
Functional Description
■ True dual-ported memory cells, which allow simultaneous
reads of the same memory location
CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are
high-speed, low-power CMOS 1 K / 2 K × 8 dual-port static
RAMs. Two ports are provided permitting independent access to
any location in memory. The CY7C131E / CY7C131AE /
CY7C136E / CY7C136AE can be used as a standalone dual-port
static RAM. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or multi-
processor designs.
■ 1 K / 2 K × 8 organization
■ 0.35 micron complementary metal oxide semiconductor
(CMOS) for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: ICC = 110 mA (typical),
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). Two flags are provided
on each port, BUSY and INT. The BUSY flag signals that the port
is trying to access the same location, which is currently being
accessed by the other port. The INT is an interrupt flag indicating
that data is placed in a unique location[1]. The BUSY and INT
flags are push pull outputs. An automatic power-down feature is
controlled independently on each port by the chip enable (CE)
pins.
Standby: ISB3 = 0.05 mA (typical)
■ Fully asynchronous operation
■ Automatic power-down
■ BUSY output flag to indicate access to the same location by
both ports
■ INT flag for port-to-port communication
■ Available in 52-pin plastic leaded chip carrier (PLCC), 52-pin
plastic quad flat package (PQFP)
The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are
available in 52-pin Pb-free PLCC and 52-pin Pb-free PQFP.
■ Pb-free packages available
Logic Block Diagram
R/
W
L
L
R/
W
R
CE
OE
CE
R
OE
L
R
I/O
I/O
I/O
I/O
7L
7R
I/O
CONTROL
I/O
CONTROL
0R
0L
[2]
[2]
[4]
BUSY
BUSY
R
L
A
A
A
9/10L
0L
9/10R
0R
MEMORY
ARRAY
ADDR
DECODER
ADDR
DECODER
[4]
A
7C131E/7C131AE/
7C136E/7C136AE
ARBITRATION LOGIC
CE
L
CE
R
OE
L
OE
R
INTERRUPT LOGIC
R/
W
L
R/W
R
[3]
L
[3]
INT
INT
R
Notes
1. Unique location used by interrupt flag: 1 K × 8: Left port reads from 3FE, Right port reads from 3FF; 2 K × 8: Left port reads from 7FE, Right port reads from 7FF.
2. BUSY is a push-pull output. No pull-up resistor required.
3. INT: push-pull output. No pull-up resistor required.
4. 1 K × 8: A0–A9, 2 K × 8: A0–A10, address lines are for both left and right ports.
Cypress Semiconductor Corporation
Document Number: 001-64231 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 15, 2012
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Contents
Pin Configurations ...........................................................3
Pin Definitions ..................................................................3
Selection Guide ................................................................3
Maximum Ratings............................................................. 4
Operating Range............................................................... 4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
AC Test Loads and Waveforms .......................................5
Switching Characteristics ................................................6
Switching Characteristics ................................................8
Switching Waveforms ....................................................10
Ordering Information ......................................................15
Ordering Code Definitions .........................................15
Package Diagrams ..........................................................16
Acronyms ........................................................................17
Document Conventions .................................................17
Units of Measure .......................................................17
Document History Page .................................................18
Sales, Solutions, and Legal Information ......................19
Worldwide Sales and Design Support .......................19
Products ....................................................................19
PSoC Solutions .........................................................19
Document Number: 001-64231 Rev. *D
Page 2 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Pin Configurations
Figure 1. Pin Diagram - 52-pin PLCC (Top View)
Figure 2. Pin Diagram - 52-pin PQFP (Top View)
[5]
[5]
[5]
[5]
7
6
5
4
3
2
1
52 51 50 49 48 47
A
A
OE
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
8
46
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
9
45
44
43
42
41
40
39
38
37
36
35
34
A
52 51 50 49 48 47 46 45 44 43 42 41 40
OE
10
11
12
13
14
15
16
17
18
19
20
A
A
A
A
A
A
A
1L
2L
3L
4L
5L
6L
1
39
38
37
36
35
34
33
32
31
30
29
28
27
R
A
A
A
A
A
A
A
2
0R
A
3
1R
7C131E/7C131AE
7C136E/7C136AE
A
4
2R
3R
4R
5R
A
5
A
6R
A
7R
A
8R
A
9R
A
6
7C131E/7C131AE
7C136E/7C131AE
A
A
A
I/O
I/O
7L
8L
7
A
6R
A
7R
A
8R
A
9R
8
9L
0L
1L
I/O
I/O
9
2L
NC
I/O
I/O
I/O
10
11
12
13
3L
7R
2122 23 24 25 26 27 28 29 30 31 32 33
I/O
I/O
NC
I/O
2L
3L
7R
14 15 16 17 18 19 20 21 22 23 24 25 26
Pin Definitions
Left Port
Right Port
Description
CEL
CER
Chip Enable
R/WL
OEL
R/WR
OER
Read/Write Enable
Output Enable
Address
[5]
[5]
A0L–A9/10L
A0R–A9/10R
I/O0R–I/O7R
INTR
I/O0L–I/O7L
INTL
Data Bus Input/Output
Interrupt Flag
Busy Flag
BUSYL
VCC
BUSYR
Power
GND
Ground
Selection Guide
7C131E-55
7C136E-55
7C136AE-55
7C131E-15
7C131AE-15
7C131E-25
7C136E-25
Parameter
Unit
Maximum Access Time
15
110
50
25
100
45
55
95
ns
Typical Operating Current
mA
mA
mA
Typical Standby Current for ISB1 (both ports TTL level)
Typical Standby Current for ISB3 (Both ports CMOS level)
45
0.05
0.05
0.05
Note
5. 1 K × 8: A0–A9, 2 K × 8: A0–A10, address lines are for both left and right ports.
Document Number: 001-64231 Rev. *D
Page 3 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
DC input voltage[8] .......................................–0.5 V to +7.0 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage .......................................... >1100 V
Latch up current ..................................................... >200 mA
Maximum Ratings
Exceeding maximum ratings [6] may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied .......................................... –55 C to +125 C
Operating Range
Range
Commercial
Industrial
Ambient Temperature
VCC
Supply voltage to ground potential ..............–0.3 V to +7.0 V
0C to +70 C
–40 C to +85 C
5 V ± 10%
5 V ± 10%
DC voltage applied to outputs
in High Z State .............................................–0.5 V to +7.0 V
Electrical Characteristics
Over the Operating Range
7C131E-55
7C131E-15
7C131AE-15
7C131E-25
7C136E-25
7C136E-55
Parameter Description
Test Conditions
Unit
7C136AE-55
Min Typ[9] Max Min Typ[9] Max Min Typ[9] Max
VOH
VOL
VIH
VIL
Output HIGH
Voltage
VCC = Min, IOH = –4.0 mA
VCC = Min, IOL = 4.0 mA
2.4
–
–
–
–
–
–
2.4
–
–
–
–
–
–
2.4
–
–
–
–
–
V
V
V
V
Output LOW
Voltage
–
0.4
–
0.4
–
–
0.4
Input HIGH
Voltage
2.2
–
2.2
2.2
–
Input LOW
Voltage
0.8
0.8
0.8
IOZ
Output
Leakage
Current
GND < VO < VCC
,
–20
+20 –20
+20 –20
+20 A
Output disabled
ICC
VCC Operating VCC = Max, IOUT = 0 mA Commercial
–
–
110 190
115 200
–
–
100 170
110 180
–
–
95
160 mA
Supply Current Outputs disabled
Industrial
105 170
ISB1
Standby
CEL and CER > VIH,
Commercial
Industrial
50
65
70
95
45
65
65
95
45
65
65
95
mA
[7]
Current,
f = fMAX
Both Ports,
TTL Inputs
ISB2
Standby
CEL or CER > VIH,
Active Port Outputs
Open,
Commercial
Industrial
–
–
120 180
135 205
–
–
110 160
135 205
–
–
110 160 mA
135 205
Current,
One Port,
TTL Inputs
[7]
f = fMAX
ISB3
Standby
Both Ports
CEL and CER > VCC
0.2 V,
Commercial
Industrial
0.05 0.5
0.05 0.5
0.05 0.5
0.05 0.5
0.05 0.5 mA
0.05 0.5
Current,
–
Both Ports,
CMOS Inputs VIN > VCC – 0.2 V
or VIN < 0.2 V, f = 0
ISB4
Standby
Current,
One Port,
One Port
Commercial
–
110 160
125 175
–
100 140
125 175
–
100 140 mA
125 175
CEL or CER > VCC – 0.2 Industrial
V,
CMOS Inputs VIN > VCC – 0.2 V
or VIN < 0.2 V,
Active Port Outputs Open,
[7]
f = fMAX
Notes
6. The voltage on any I/O pin cannot exceed the power pin during power-up.
7. At f = f , address and data inputs are cycling at the maximum frequency of read cycle of 1/t and using AC Test Waveforms input levels of GND to 3 V.
MAX
RC
8. Pulse width < 20 ns.
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V (typ.), T = 25 °C.
CC
CC
A
Document Number: 001-64231 Rev. *D
Page 4 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Capacitance[10]
Parameter
Description
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 5.0 V
Max
15
Unit
pF
CIN
Input capacitance
Output capacitance
COUT
10
pF
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
5 V
5 V
R
TH
= 250
R1 = 893
OUTPUT
C = 30 pF
OUTPUT
R1 = 893
R2 = 347
OUTPUT
C = 5 pF
C = 30 pF
R2 = 347
V
TH
= 1.4 V
(a) Normal Load (Load 1)
(c) Three-State Delay(Load 2)
(b) Thévenin Equivalent (Load 1)
(Used for tLZ, tHZ, tHZWE, and tLZWE
including scope and jig)
ALL INPUT PULSES
(CY7C131E/CY7C131AE ONLY)
3.0 V
90%
10%
GND
90%
10%
5ns
5ns
Note
10. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-64231 Rev. *D
Page 5 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Switching Characteristics
Over the Operating Range
7C131E-15/7C131AE-15
7C131E-25/7C136E-25
Parameter [11]
Description
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
Address to data valid [12]
15
–
3
–
–
3
–
3
–
0
–
–
15
–
25
–
3
–
–
3
–
5
–
0
–
–
25
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data hold from Address change
CE LOW to data valid [12]
OE LOW to data valid [12]
OE LOW to Low Z [13, 14, 15]
OE HIGH to High Z [13, 14, 15]
CE LOW to Low Z [13, 14, 15]
CE HIGH to High Z [13, 14, 15]
CE LOW to power-up [13]
CE HIGH to power-down [13]
15
10
–
25
15
–
10
–
15
–
10
–
15
–
tPD
15
25
Write Cycle [16]
tWC
Write cycle time
15
12
12
0
–
–
25
20
20
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
R/W pulse width
–
–
tHA
–
–
tSA
0
–
0
–
tPWE
tSD
10
10
0
–
12
15
0
–
Data setup to write end
Data hold from write end
R/W LOW to High Z [15]
R/W HIGH to Low Z [15]
–
–
tHD
–
–
[13]
tHZWE
–
10
–
–
15
–
[13]
tLZWE
3
3
Notes
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specified I /I
OL OH,
and 30 pF load capacitance.
12. AC Test Conditions use V = 1.6 V and V = 1.4 V.
OH
OL
13. This parameter is guaranteed but not tested.
14. At any given temperature and voltage condition for any given device, t
is less than t
and t
is less than t
.
LZOE
HZCE
LZCE
HZOE
15. Parameters t
state voltage.
, t
, t
, t
, t
and t
are tested with C = 5 pF as in part (c) of Figure 3 on page 5. Transition is measured ±500 mV from steady
LZCE LZWE HZOE LZOE HZCE
HZWE L
16. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate
Document Number: 001-64231 Rev. *D
Page 6 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Switching Characteristics (continued)
Over the Operating Range
7C131E-15/7C131AE-15
7C131E-25/7C136E-25
Parameter [11]
Description
Unit
Min
Max
Min
Max
Busy/Interrupt Timing[17]
tBLA
BUSY LOW from Address match
BUSY HIGH from Address mismatch [18]
BUSY LOW from CE LOW
–
–
–
–
5
–
–
–
15
15
15
15
–
–
–
–
–
5
–
–
–
20
20
20
20
–
ns
ns
ns
ns
ns
ns
ns
ns
tBHA
tBLC
tBHC
BUSY HIGH from CE HIGH [18]
tPS
Port setup for priority
tBDD
BUSY HIGH to valid data
15
25
30
25
30
45
tDDD
Write data valid to read data valid [19]
Write pulse to data delay [19]
tWDD
Interrupt Timing
tWINS
tEINS
tINS
R/W to INTERRUPT set time
–
–
–
–
–
–
15
15
15
15
15
15
–
–
–
–
–
–
25
25
25
25
25
25
ns
ns
ns
ns
ns
ns
CE to INTERRUPT set time
Address to INTERRUPT set time
OE to INTERRUPT reset time [18]
CE to INTERRUPT reset time [18]
Address to INTERRUPT reset time [18]
tOINR
tEINR
tINR
Notes
17. Test conditions used are Load 2.
18. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.
19. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
Document Number: 001-64231 Rev. *D
Page 7 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Switching Characteristics
Over the Operating Range
7C131E-55
7C136E-55
7C136AE-55
Parameter
Description
Unit
Min
Max
Read Cycle
tRC
Read cycle time
55
–
3
–
–
3
–
5
–
0
–
–
55
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid [21]
Data hold from Address change
CE LOW to data valid [21]
OE LOW to data valid [21]
OE LOW to Low Z [21, 22, 23]
OE HIGH to High Z [21, 22, 23]
CE LOW to Low Z [21, 22, 23]
CE HIGH to High Z [21, 22, 23]
CE LOW to power-up [22]
CE HIGH to power-down [22]
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
55
25
–
25
–
25
–
tPD
35
Write Cycle
tWC
Write cycle time
55
40
40
2
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
R/W pulse width
–
tHA
–
tSA
0
–
tPWE
tSD
30
20
0
–
Data setup to write end
Data hold from write end
R/W LOW to High Z [24]
R/W HIGH to Low Z [24]
–
tHD
–
tHZWE
tLZWE
–
25
–
3
Busy/Interrupt Timing[20]
tBLA BUSY LOW from Address match
BUSY HIGH from Address mismatch [25]
–
–
–
–
5
–
30
30
30
30
–
ns
ns
ns
ns
ns
ns
tBHA
tBLC
tBHC
tPS
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH [25]
Port setup for priority
tBDD
BUSY HIGH to valid data
45
Notes
20. Test conditions used are Load 2.
21. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate
a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
22. AC Test Conditions use V = 1.6 V and V = 1.4 V.
OH
OL
23. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.
24. Parameters t
, t
, t
, t
, t
and t
are tested with C = 5 pF as in part (b) of Figure 3 on page 5. Transition is measured ±500 mV from steady
LZCE LZWE HZOE LZOE HZCE
HZWE
state voltage.
25. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
Document Number: 001-64231 Rev. *D
Page 8 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Switching Characteristics (continued)
Over the Operating Range
7C131E-55
7C136E-55
7C136AE-55
Parameter
Description
Unit
Min
Max
30
tDDD
tWDD
Interrupt Timing
Write data valid to read data valid [26]
Write pulse to data delay [26]
–
–
ns
ns
45
tWINS
tEINS
tINS
R/W to INTERRUPT set time
–
–
–
–
–
–
45
45
45
45
45
45
ns
ns
ns
ns
ns
ns
CE to INTERRUPT set time
Address to INTERRUPT set time
OE to INTERRUPT reset time [27]
CE to INTERRUPT reset time [27]
Address to INTERRUPT reset time [27]
tOINR
tEINR
tINR
Notes
26. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
27. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.
Document Number: 001-64231 Rev. *D
Page 9 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Switching Waveforms
Figure 4. Read Cycle No. 1 [28, 29]
Either Port ADDR Access
t
RC
ADDR
t
AA
t
OHA
DATA OUT
PREVIOUS DATAVALID
DATA VALID
Figure 5. Read Cycle No. 2 [28, 30]
Either Port CE/OE Access
CE
OE
t
HZCE
t
ACE
t
HZOE
t
DOE
t
LZOE
t
LZCE
DATA VALID
DATA OUT
t
PU
t
PD
I
CC
I
SB
Figure 6. Write Cycle No. 1 (OE Three-States Data I/Os – Either Port) [31, 32]
Either Port
t
WC
ADDR
t
SCE
CE
t
t
AW
HA
t
SA
t
PWE
R/W
t
t
HD
SD
DATAIN
OE
DATA VALID
t
HZOE
HIGH IMPEDANCE
D
OUT
Notes
28. R/W is HIGH for read cycle.
29. Device is continuously selected, CE = V and OE = V
.
IL
IL
30. Address valid prior to or coincident with CE transition LOW.
31. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
32. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or t
+ t to allow the data I/O pins to enter high impedance
PWE
HZWE SD
and for data to be placed on the bus for the required t
.
SD
Document Number: 001-64231 Rev. *D
Page 10 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (R/W Three-States Data I/Os – Either Port) [33, 34]
t
WC
ADDR
CE
t
t
HA
SCE
t
AW
[36]
PWE
t
SA
t
R/W
t
t
HD
SD
DATAIN
DATA VALID
[37]
HZWE
t
LZWE
t
HIGH IMPEDANCE
DATAOUT
Figure 8. Read Cycle No. 3 [35]
Read with BUSY
t
RC
ADDR
ADDR MATCH
R
tPWE
R/W
R
t
HD
D
INR
VALID
ADDR MATCH
ADDR
L
t
PS
t
BHA
BUSY
L
t
BLA
t
BDD
DOUT
VALID
L
t
DDD
t
WDD
Notes
33. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.
34. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state.
35. CEL = CER = LOW.
36. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and
data to be placed on the bus for the required tSD. If OE is HIGH during a R/Wn controlled write cycle, this requirements does not apply and the write pulse can
be as short as the specified tPWE.
37. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
Document Number: 001-64231 Rev. *D
Page 11 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Switching Waveforms (continued)
Figure 9. Busy Timing Diagram No. 1 (CE Arbitration)[38]
CEL Valid First:
ADDR L,R
ADDR MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CER Valid First:
ADDRL,R
ADDR MATCH
CE
R
t
PS
CE
L
t
t
BHC
BLC
BUSY
L
Figure 10. Busy Timing Diagram No. 2 (ADDR Arbitration)[38]
Left ADDR Valid First:
t
or t
WC
RC
ADDR MATCH
ADDR MISMATCH
ADDR
ADDR
L
t
PS
R
t
t
BHA
BLA
BUSY
R
Right Address Valid First:
t
or t
WC
RC
ADDR MATCH
ADDR MISMATCH
ADDR
R
t
PS
ADDR
L
t
t
BHA
BLA
BUSY
L
Note
38. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Document Number: 001-64231 Rev. *D
Page 12 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Switching Waveforms (continued)
Figure 11. Interrupt Timing Diagrams
Left Side Sets INTR
t
WC
ADDR
WRITE 3FF/7FF
L
[40]
[39]
t
t
HA
INS
CE
L
t
EINS
R/W
L
t
SA
t
WINS
INT
R
Right Side Clears INTR
t
RC
ADDR
READ 3FF/7FF
[39]
R
[40]
t
t
INR
HA
CE
R
t
EINR
R/W
R
OE
R
t
OINR
INT
R
Notes
39. Parameter t
or t
depends on which enable pin (CE or R/W ) is asserted last.
L L
INS
INR
40. Parameter t depends on which enable pin (CE or R/W ) is deasserted first.
HA
L
L
Document Number: 001-64231 Rev. *D
Page 13 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Switching Waveforms (continued)
Figure 12. Interrupt Timing Diagrams
Right Side Sets INTL
t
WC
ADDR
WRITE 3FE/7FE
R
[41]
[42]
t
t
HA
INS
CE
R
t
EINS
R/W
R
t
SA
t
WINS
INT
L
Left Side Clears INTL
t
RC
ADDR
READ 3FE/7FE
[41]
R
[42]
HA
t
t
INR
CE
L
t
EINR
R/W
L
OE
L
t
OINR
INT
L
Notes
41. Parameter t
or t
depends on which enable pin (CE or R/W ) is asserted last.
L L
INS
INR
42. Parameter t depends on which enable pin (CE or R/W ) is deasserted first.
HA
L
L
Document Number: 001-64231 Rev. *D
Page 14 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Ordering Information
Speed
Ordering Code
(ns)
Package Name
Package Type
Operating Range
1 K × 8 Dual-port SRAM
15
25
55
CY7C131AE-15JXI
CY7C131E-15NXI
CY7C131E-25JXC
CY7C131E-25NXC
CY7C131E-55JXC
CY7C131E-55NXC
CY7C131E-55JXI
CY7C131E-55NXI
51-85004
51-85042
51-85004
51-85042
51-85004
51-85042
51-85004
51-85042
52-pin Pb-free Plastic Leaded Chip Carrier
52-pin Pb-free Plastic Quad Flatpack
52-pin Pb-free Plastic Leaded Chip Carrier
52-pin Pb-free Plastic Quad Flatpack
52-pin Pb-free Plastic Leaded Chip Carrier
52-pin Pb-free Plastic Quad Flatpack
52-pin Pb-free Plastic Leaded Chip Carrier
52-pin Pb-free Plastic Quad Flatpack
Industrial
Commercial
Commercial
Industrial
2 K × 8 Dual-port SRAM
25
CY7C136E-25JXC
CY7C136E-25NXC
CY7C136E-25JXI
CY7C136E-55JXC
CY7C136E-55NXC
CY7C136AE-55JXI
CY7C136AE-55NXI
51-85004
51-85042
51-85004
51-85004
51-85042
51-85004
51-85042
52-pin Pb-free Plastic Leaded Chip Carrier
52-pin Pb-free Plastic Quad Flatpack
52-pin Pb-free Plastic Leaded Chip Carrier
52-pin Pb-free Plastic Leaded Chip Carrier
52-pin Pb-free Plastic Quad Flatpack
52-pin Pb-free Plastic Leaded Chip Carrier
52-pin Pb-free Plastic Quad Flatpack
Commercial
Industrial
55
Commercial
Industrial
Ordering Code Definitions
CY 7 C 13X X E -
X
XX X
X
Temperature Grade: X = I or C
I = Industrial; C = Commercial
Pb-free
Package Type: X = J or N
J = 52-pin PLCC; N = 52-pin PQFP
Speed Grade: XX = 15 ns or 25 ns or 55 ns
Process Version R4 = E
X = A or blank
Part Identifier: 13X = 131 or 136
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-64231 Rev. *D
Page 15 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Package Diagrams
Figure 13. 52-pin PLCC (0.756 × 0.756 Inches) J52 Package Outline, 51-85004
51-85004 *C
Figure 14. 52-pin PQFP (10 × 10 × 2.0 mm) N5210 Package Outline, 51-85042
51-85042 *D
Document Number: 001-64231 Rev. *D
Page 16 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
CE
chip enable
Unit of Measure
CMOS
I/O
complementary metal oxide semiconductor
input/output
°C
µA
mA
mV
ns
degree Celsius
microampere
milliampere
millivolt
OE
output enable
PLCC
PQFP
SRAM
TTL
plastic leaded chip carrier
plastic quad flat package
static random access memory
transistor-transistor logic
write enable
nanosecond
ohm
%
percent
picofarad
volt
WE
pF
V
W
watt
Document Number: 001-64231 Rev. *D
Page 17 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Document History Page
Document Title: CY7C131E/CY7C131AE/CY7C136E/CY7C136AE, 1 K / 2 K × 8 Dual-port Static RAM
Document Number: 001-64231
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
3038037
3394800
ADMU
ADMU
09/24/2010 New data sheet
*A
10/04/2011 Changed status from Preliminary to Final.
Updated Maximum Ratings (Removed (Pin 48 to Pin 24)).
Updated Electrical Characteristics (changed minimum value of IOZ parameter
from –10 µA to –20 µA, changed maximum value of IOZ parameter from
+10 µA to +20 µA and changed maximum value of ISB3 from 0.5 mA to 15 mA
for both Commercial and Industrial temperature ranges).
Updated Package Diagrams (Updated revision of 51-85004 from *B to *C and
revision of 51-85042 from *A to *C).
Updated in new template.
*B
*C
3403147
3435230
ADMU
ADMU
10/12/2011 No technical updates.
11/17/2011 Updated Features (Removed a feature “Expandable data bus width to 16 bits
or more using Master/Slave chip select when using more than one device.”
and updated another feature to read as “BUSY output flag to indicate access
to the same location by both ports.”.
Updated Functional Description (Updated the sentence in the first paragraph
to read as “The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE can be
used as a standalone dual-port static RAM.”.
Updated Note 2 to read as “BUSY is a push-pull output. No pull-up resistor
required.”.
Updated Note 3 to read as “Interrupt: push-pull output. No pull-up resistor
required.”.
Updated Maximum Ratings (Removed “(per MIL-STD-883, Method 3015)”).
Updated Electrical Characteristics (Removed the Note “See the last page of
this specification for Group A subgroup testing information.” and its reference
in Parameter column.).
Updated Capacitance[10] (Changed maximum value of CIN parameter from 10
pF to 15 pF).
Updated AC Test Loads and Waveforms.
Updated Switching Characteristics (Removed the Note “See the last page of
this specification for Group A subgroup testing information.” and its reference
in Parameter column.).
Updated Switching Characteristics (Changed the minimum value of tOHA from
0 ns to 3 ns).
Removed the section “Typical DC and AC Characteristics”.
Removed the section “Reference Documents”.
*D
3620277
ADMU
06/15/2012 Added footnotes 9, 13, 17, 20, 36, 37, 39, 40, 41, and 42.
Missing overbars updated.
Removed “Slave Diagrams”.
Updated Figure 3 with value 5 ns.
Updated Maximum Ratings (updated Static discharge voltage from 2001 V to
1100 V).
Corrected the typo in Electrical Characteristics.
Updated Package Diagrams (51-85042 from Rev *C to *D).
Updated ICC parameters in Electrical Characteristics table.
Updated Typical Operating Current parameters in Selection Guide.
Document Number: 001-64231 Rev. *D
Page 18 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2010-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-64231 Rev. *D
Revised June 15, 2012
Page 19 of 19
All products and company names mentioned in this document may be the trademarks of their respective holders.
相关型号：
CY7C1370AV25-150AC
ZBT SRAM, 512KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
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