CY7C1370D-225AXC [CYPRESS]
18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture; 18兆位( 512K ×36 / 1M ×18 )流水线SRAM与NOBL架构型号: | CY7C1370D-225AXC |
厂家: | CYPRESS |
描述: | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
文件: | 总30页 (文件大小:345K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C1370D
CY7C1372D
PRELIMINARY
18-Mbit (512K x 36/1M x 18) Pipelined
SRAM with NoBL™ Architecture
Functional Description
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
The CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and
1 Mbit x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL™) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1370D and CY7C1372D are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1370D and CY7C1372D are
pin compatible and functionally equivalent to ZBT devices.
— Available speed grades are 250, 225, 200, and
167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 3.3V power supply
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1370D and BWa–BWb for CY7C1372D)
and a Write Enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
• Availableinlead-Free100TQFP,119BGA,and165fBGA
packages
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Logic Block Diagram-CY7C1370D (512K x 36)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
WRITE
DRIVERS
BW
BW
a
a
b
c
d
A
M
P
b
BW
BW
c
S
T
E
R
S
F
d
E
R
S
S
WE
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
Document #: 38-05555 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised October 12, 2004
CY7C1370D
CY7C1372D
PRELIMINARY
Logic Block Diagram-CY7C1372D (1 Mbit x 18)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
S
T
E
R
S
MEMORY
ARRAY
E
B
U
F
DQs
DQP
DQP
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
a
F
b
b
E
R
S
S
N
G
WE
E
E
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Selection Guide
CY7C1370D-250 CY7C1370D-225 CY7C1370D-200 CY7C1370D-167
CY7C1372D-250 CY7C1372D-225 CY7C1372D-200 CY7C1372D-167 Unit
Maximum Access Time
2.6
350
70
2.8
325
70
3.0
300
70
3.4
275
70
ns
Maximum Operating Current
mA
mA
Maximum CMOS Standby Current
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05555 Rev. *A
Page 2 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Pin Configurations
100-pin TQFP Packages
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
78
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
V
V
DDQ
VDDQ
VSS
V
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
V
SS
SS
DQc
DQc
NC
NC
DQb
NC
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
DQPa
DQa
DQa
DQc
DQc
9
DQb
9
V
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
V
V
DDQ
DDQ
V
DQa
DQa
DDQ
DQc
DQc
NC
DQb
DQb
NC
V
CY7C1370D
(512K × 36)
SS
V
V
DD
DD
NC
CY7C1372D
(1M × 18)
NC
NC
VDD
ZZ
DQa
DQa
V
DD
V
V
SS
SS
ZZ
DQd
DQb
DQb
DQa
DQa
DQd
V
V
DDQ
DDQ
VDDQ
VSS
DQa
DQa
V
DDQ
V
V
SS
SS
V
SS
DQd
DQd
DQd
DQd
DQb
DQb
DQa DQPb
DQa
DQa
NC
DQa
VSS
VDDQ
DQa
DQa
DQPa
NC
NC
V
SS
V
V
SS
SS
V
V
DDQ
DQd
DDQ
V
DDQ
NC
NC
NC
NC
NC
NC
DQd
DQPd
Document #: 38-05555 Rev. *A
Page 3 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Pin Configurations (continued)
119-ball BGA Pinout
CY7C1370D (512K × 36) – BGA
1
2
3
4
5
6
7
VDDQ
A
A
A
A
A
VDDQ
A
NC
NC
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
B
C
D
DQc
DQPc
VSS
NC
VSS
DQPb
DQb
DQc
VDDQ
DQc
DQc
DQc
DQc
DQc
VDD
VSS
VSS
CE1
VSS
VSS
DQb
DQb
DQb
DQb
VDD
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
E
F
OE
A
G
H
J
BWc
VSS
NC
BWb
VSS
NC
DQc
WE
VDD
VDDQ
DQd
DQd
VDDQ
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
VSS
BWd
VSS
CLK
NC
VSS
BWa
VSS
VSS
VSS
DQa
DQa
DQa
DQa
DQPa
K
L
M
N
P
CEN
A1
VSS
VSS
MODE
A
A0
NC
NC
A
VDD
A
A
NC
ZZ
R
T
NC
A
E(72)
TMS
E(36)
NC
VDDQ
TDI
TCK
TDO
VDDQ
U
CY7C1372D (1M x 18) – BGA
1
2
3
4
5
6
7
VDDQ
A
A
A
A
A
VDDQ
A
B
C
D
E
F
NC
NC
CE2
A
A
A
NC
NC
CE3
A
ADV/LD
VDD
A
A
DQb
NC
NC
DQb
NC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPa
NC
NC
DQa
VDDQ
CE1
VDDQ
DQa
OE
A
NC
DQb
VDDQ
DQb
NC
VDD
NC
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
G
H
J
BWb
VSS
NC
WE
VDD
NC
DQb
VDDQ
DQb
NC
DQb
NC
VSS
NC
CLK
NC
VSS
NC
DQa
NC
DQa
NC
A
DQa
NC
K
L
BWa
VSS
DQb
NC
VSS
VSS
VSS
MODE
A
VDDQ
NC
M
N
P
R
T
CEN
A1
VSS
VSS
NC
A
DQPb
A
A0
DQa
NC
NC
VDD
E(36)
TCK
E(72)
VDDQ
A
A
ZZ
TMS
TDI
TDO
NC
VDDQ
U
Document #: 38-05555 Rev. *A
Page 4 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Pin Configurations (continued)
165-Ball fBGA Pinout
CY7C1370D (512K × 36) – fBGA
1
2
A
3
4
5
6
7
8
9
A
10
A
11
NC
E(288)
ADV/LD
A
B
C
D
CE1
BWc
BWb
CE3
CLK
VSS
VSS
CEN
WE
VSS
VSS
NC
A
CE2
VDDQ
VDDQ
OE
VSS
VDD
A
A
E(144)
DQPb
DQb
BWd
VSS
VDD
BWa
VSS
VSS
DQPc
DQc
NC
DQc
VDDQ
VDDQ
NC
DQb
DQc
DQc
DQc
DQc
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQb
DQb
DQb
NC
DQb
E
F
DQc
DQc
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQb
DQb
ZZ
G
H
J
DQd
DQd
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
K
L
DQd
DQPd
NC
DQd
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
DQa
DQPa
NC
M
N
P
E(72)
TDI
TDO
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
R
CY7C1372D (1M × 18) – fBGA
1
E(288)
NC
2
A
3
4
5
NC
6
CE3
7
8
9
A
10
A
11
A
A
B
C
D
CE1
BWb
NC
CEN
ADV/LD
A
CE2
VDDQ
VDDQ
BWa
VSS
VSS
CLK
VSS
VSS
A
A
E(144)
DQPa
DQa
WE
VSS
VSS
OE
VSS
VDD
NC
NC
DQb
VSS
VDD
VDDQ
VDDQ
NC
NC
NC
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQa
DQa
DQa
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
NC
NC
NC
K
L
NC
NC
DQb
DQPb
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
NC
NC
NC
M
N
P
E(72)
TDI
TDO
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05555 Rev. *A
Page 5 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd.
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
WE
Input-
Synchronous
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
ADV/LD
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
CE1
CE2
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous
CE1 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
CE3
OE
Input-
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the first clock when emerging from a
deselected state and when the device has been deselected.
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
CEN
DQS
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are
automatically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state of OE.
DQPX
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQs. During write
sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
and DQPd is controlled by BWd.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
TDI
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
VDD
VDDQ
VSS
JTAG-Clock
Clock input to the JTAG circuitry.
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground
Ground for the device. Should be connected to ground of the system.
Document #: 38-05555 Rev. *A
Page 6 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
No connects. This pin is not connected to the die.
NC
–
–
E(36,72,
These pins are not connected. They will be used for expansion to the 36M, 72M, 144M and
144, 288)
288M densities.
ZZ
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. During normal operation, this pin can be connected to VSS or left
floating.
Burst Read Accesses
Introduction
The CY7C1370D and CY7C1372D have an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Functional Overview
The CY7C1370D and CY7C1372D are synchronous-pipelined
Burst NoBL SRAMs designed specifically to eliminate wait
states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of
the clock. The clock signal is qualified with the Clock Enable
input signal (CEN). If CEN is HIGH, the clock signal is not
recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 2.6 ns (250-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct byte write operations.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented is loaded into the
Address Register. The write signals are latched into the
Control Logic block.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370D and DQa,b/DQPa,b for
CY7C1372D). In addition, the address for the subsequent
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are
asserted).
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370D & DQa,b/DQPa,b for
CY7C1372D) (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the write is complete.
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(250-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will three-state following
the next clock rise.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1370D and BWa,b for CY7C1372D)
signals. The CY7C1370D/CY7C1372D provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple byte write operations.
Because the CY7C1370D and CY7C1372D are common I/O
devices, data should not be driven into the device while the
Document #: 38-05555 Rev. *A
Page 7 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370D and DQa,b/DQPa,b for
CY7C1372D) inputs. Doing so will three-state the output
Interleaved Burst Address Table
(MODE = Floating or VDD
)
drivers. As a safety precaution, DQ and DQP (DQa,b,c,d
/
First
Second
Address
Third
Fourth
Address
DQPa,b,c,d for CY7C1370D and DQa,b/DQPa,b for
CY7C1372D) are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Address
Address
A1,A0
10
A1,A0
00
A1,A0
01
A1,A0
11
Burst Write Accesses
01
00
11
10
The CY7C1370D/CY7C1372D has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subse-
quent clock rise, the chip enables (CE1, CE2, and CE3) and
WE inputs are ignored and the burst counter is incremented.
The correct BW (BWa,b,c,d for CY7C1370D and BWa,b for
CY7C1372D) inputs must be driven in each cycle of the burst
write in order to write the correct bytes of data.
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
00
A1,A0
01
A1,A0
10
A1,A0
11
01
10
11
00
Sleep Mode
10
11
00
01
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD − 0.2V
Min.
Max
Unit
80
mA
tZZS
ZZ > VDD − 0.2V
2tCYC
ns
ns
ns
ns
tZZREC
tZZI
ZZ < 0.2V
2tCYC
0
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
tRZZI
Document #: 38-05555 Rev. *A
Page 8 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Truth Table[1, 2, 3, 4, 5, 6, 7]
Address
Used
Operation
CE
H
X
L
ZZ
L
ADV/LD WE BWx
OE
CEN CLK
DQ
Deselect Cycle
None
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
X
L
L
L
L
L
L
L
L
L
L
H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
Three-State
Three-State
Data Out (Q)
Data Out (Q)
Three-State
Three-State
Data In (D)
Data In (D)
Three-State
Three-State
–
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/Write Abort (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
None
L
X
L
External
Next
L
X
L
L
H
L
L
External
Next
L
H
H
X
X
X
X
X
X
X
L
L
H
L
External
Next
L
X
L
L
H
L
X
L
L
None
L
H
H
X
X
Next
X
X
X
L
H
X
X
X
X
X
Current
None
L
Sleep Mode
H
Three-State
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW . See Write Cycle Description table for details.
X
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ and DQP = Three-state when OE
s
X
is inactive or when the device is deselected, and DQ = data when OE is active.
s
8. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.
X
Document #: 38-05555 Rev. *A
Page 9 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1370D)
Read
WE
H
L
BWd
BWc
X
H
H
H
H
L
BWb
BWa
X
H
L
X
H
H
H
H
H
H
H
H
L
X
H
H
L
Write – No bytes written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Bytes b, a
L
L
H
L
L
L
Write Byte c – (DQc and DQPc)
Write Bytes c, a
L
H
H
L
H
L
L
L
Write Bytes c, b
L
L
H
L
Write Bytes c, b, a
L
L
L
Write Byte d – (DQd and DQPd)
Write Bytes d, a
L
H
H
H
H
L
H
H
L
H
L
L
L
Write Bytes d, b
L
L
H
L
Write Bytes d, b, a
L
L
L
Write Bytes d, c
L
L
H
H
L
H
L
Write Bytes d, c, a
L
L
L
Write Bytes d, c, b
L
L
L
H
L
Write All Bytes
L
L
L
L
Function (CY7C1372D)
Read
WE
H
L
BWb
BWa
x
H
H
L
x
H
L
Write – No Bytes Written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
L
L
H
L
L
L
Disabling the JTAG Feature
IEEE 1149.1 Serial Boundary Scan (JTAG)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
The CY7C1370D/CY7C1372D incorporates a serial boundary
scan test access port (TAP). This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3V or
2.5V I/O logic levels.
The CY7C1370D/CY7C1372D contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Document #: 38-05555 Rev. *A
Page 10 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
TAP Controller State Diagram
TAP Controller Block Diagram
0
TEST-LOGIC
1
RESET
0
Bypass Register
1
1
1
2
1
0
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
0
0
Selection
TDI
TDO
1
1
Circuitr
y
CAPTURE-DR
CAPTURE-IR
.
.
.
2
1
0
0
0
SHIFT-DR
0
SHIFT-IR
0
x
.
.
.
.
. 2 1 0
1
1
Boundary Scan Register
TAP CONTROLLER
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
0
TCK
TMS
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
Performing a TAP Reset
1
0
1
0
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Test Access Port (TAP)
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select (TMS)
Instruction Register
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass-
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
Document #: 38-05555 Rev. *A
Page 11 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
TAP Instruction Set
Overview
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri-
or to the selection of another boundary scan test operation.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
IDCODE
Reserved
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05555 Rev. *A
Page 12 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Clock
tTCYC
tTF
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
25
25
tTL
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
5
ns
ns
0
5
5
5
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes:
9. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document #: 38-05555 Rev. *A
Page 13 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ............................................... .VSS to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
ZO= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[11]
Parameter
VOH1
Description
Test Conditions
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
IOH = –4.0 mA, VDDQ = 3.3V
Output HIGH Voltage
I
OH = –1.0 mA, VDDQ = 2.5V
OH = –100 µA VDDQ = 3.3V
VDDQ = 2.5V
IOL = 8.0 mA, VDDQ = 3.3V
OL = 8.0 mA, VDDQ = 2.5V
IOL = 100 µA VDDQ = 3.3V
DDQ = 2.5V
V
I
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
V
0.4
0.4
V
I
V
0.2
V
V
0.2
V
V
DDQ = 3.3V
2.0
1.7
VDD + 0.3
V
VDDQ = 2.5V
VDDQ = 3.3V
VDD + 0.3
V
–0.5
–0.3
–5
0.7
0.7
5
V
V
VIL
Input LOW Voltage
Input Load Current
V
DDQ = 2.5V
µA
IX
GND < VIN < VDDQ
Note:
11.All voltages referenced to V (GND).
SS
Document #: 38-05555 Rev. *A
Page 14 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Identification Register Definitions
Instruction Field
CY7C1370D
000
CY7C1372D
Description
Reserved for version number.
Revision Number (31:29)
000
Cypress Device ID (28:12)[12] 01011001000100101 01011001000010101 Reserved for future use.
Cypress JEDEC ID (11:1)
ID Register Presence (0)
00000110100
1
00000110100
1
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (x18)
Bit Size (x36)
Instruction
Bypass
ID
3
3
1
1
32
85
89
32
85
89
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
001
010
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
011
100
RESERVED
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
101
110
111
RESERVED
RESERVED
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
BYPASS
Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
Note:
12. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.
Document #: 38-05555 Rev. *A
Page 15 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
119-ball BGA Boundary Scan[13, 14]
CY7C1370D (1M x 36)
CY7C1370D (1M x 36)
Bit#
1
Ball ID
Bit#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
B6
D4
B4
F4
Bit#
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
H4
T4
T5
T6
R5
L5
N2
P2
2
3
R3
4
T1
5
M4
A5
K4
E4
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
R1
6
T2
7
R6
U6
R7
T7
P6
N7
M6
L7
L3
8
R2
9
T3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
L4
N4
P4
Internal
K6
P7
N6
L6
K7
J5
H6
G7
F6
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
G1
H2
D1
E2
G2
H1
J3
2K
L1
M2
N1
P1
K1
L2
Notes:
13. Balls which are NC (No Connect) are pre-set LOW
14. Bit# 85 is pre-set HIGH
Document #: 38-05555 Rev. *A
Page 16 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
119-ball BGA Boundary Scan Order[13, 14]
CY7C1372D (2M x 18)
Ball ID
CY7C1372D (2M x 18)
Bit #
1
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
B6
D4
B4
F4
Bit #
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
H4
T4
T5
T6
R5
L5
N2
P2
2
3
R3
4
T1
5
M4
A5
K4
E4
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
R1
6
T2
7
R6
U6
R7
T7
P6
N7
M6
L7
L3
8
R2
9
T3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
L4
N4
P4
Internal
K6
P7
N6
L6
K7
J5
H6
G7
F6
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
G1
H2
D1
E2
G2
H1
J3
2K
L1
M2
N1
P1
K1
L2
Document #: 38-05555 Rev. *A
Page 17 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
165-Ball fBGA Boundary Scan Order[13, 15]
CY7C1370D (1M x 36)
Ball ID
CY7C1370D (1M x 36)
Bit #
1
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
A9
B9
C10
A8
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
Bit #
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
K2
N6
N7
2
L2
3
10N
P11
P8
M2
N1
4
5
N2
6
R8
P1
7
R9
R1
8
P9
R2
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
P3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
R3
P2
R4
P4
N5
P6
R6
Internal
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
G1
D2
E2
F2
G2
H1
H3
J1
K1
L1
M1
J2
Note:
15. Bit# 89 is Pre-Set HIGH
Document #: 38-05555 Rev. *A
Page 18 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
165-Ball fBGA Boundary Scan Order[13, 15]
CY7C1372D (2M x 18)
Ball ID
CY7C1372D (2M x 18)
Bit #
1
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
A9
B9
C10
A8
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
Bit #
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
K2
N6
N7
2
L2
3
10N
P11
P8
M2
N1
4
5
N2
6
R8
P1
7
R9
R1
8
P9
R2
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
P3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
R3
P2
R4
P4
N5
P6
R6
Internal
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
G1
D2
E2
F2
G2
H1
H3
J1
K1
L1
M1
J2
Document #: 38-05555 Rev. *A
Page 19 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Temperature
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC to Outputs in Tri-State................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Range
VDD
VDDQ
Commercial 0°C to +70°C 3.3V–5%/+10% 2.5V –5% to
VDD
Industrial
–40°C to +85°C
[16, 17]
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
Unit
V
VDDQ
VOH
VOL
VIH
VDDQ = 3.3V
VDDQ = 2.5V
VDD
V
2.625
V
Output HIGH Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
V
2.0
V
Output LOW Voltage
0.4
0.4
V
V
DDQ = 2.5V, VDD = Min., IOL = 1.0 mA
Input HIGH Voltage[16] VDDQ = 3.3V
DDQ = 2.5V
V
2.0
1.7
VDD + 0.3V
VDD + 0.3V
0.8
V
V
V
VIL
Input LOW Voltage[16] VDDQ = 3.3V
–0.3
–0.3
–5
V
VDDQ = 2.5V
0.7
V
IX
Input Load Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
5
µA
Input Current of MODE Input = VSS
Input = VDD
–5
–30
–5
µA
µA
30
Input Current of ZZ
Input = VSS
Input = VDD
µA
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
5
µA
VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
350
325
300
275
160
TBD
150
140
70
mA
mA
mA
mA
mA
mA
mA
mA
mA
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX =
1/tCYC
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB2
Automatic CE
Power-down
Current—CMOS Inputs f = 0
Max. VDD, Device Deselected, All speed grades
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
ISB3
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX = 1/tCYC
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
135
TBD
130
125
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
Shaded areas contain advance information.
Notes:
16. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
.
17. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
Power-up
DD
IH
DD
DDQ DD
Document #: 38-05555 Rev. *A
Page 20 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Electrical Characteristics Over the Operating Range (continued)[16, 17]
Parameter
ISB4
Description
Automatic CE
Power-down
Test Conditions
Min.
Max.
Unit
Max. VDD, Device Deselected, All speed grades
VIN ≥ VIH or VIN ≤ VIL, f = 0
80
mA
Current—TTL Inputs
Capacitance[18]
TQFP
BGA
fBGA
Parameter
Description
Test Conditions
Package
Package
Package
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
DD = 3.3V.
VDDQ = 2.5V
5
5
5
8
8
8
9
9
9
V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
Thermal Resistance[18]
TQFP
Package
BGA
Package
fBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures
for measuring thermal
31
6
45
7
46
3
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
°C/W
impedance, per EIA / JESD51.
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
V = 1.5V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 1538Ω
≤ 1ns
≤ 1ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
18. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05555 Rev. *A
Page 21 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Switching Characteristics Over the Operating Range [23, 24]
-250
-225
-200
-167
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
[19]
tPower
VCC (typical) to the first access read or write
1
1
1
1
ms
Clock
tCYC
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
4.0
4.4
5
6
ns
MHz
ns
FMAX
tCH
250
225
200
167
1.7
1.7
2.0
2.0
2.0
2.0
2.2
2.2
tCL
Clock LOW
ns
Output Times
tCO
Data Output Valid After CLK Rise
OE LOW to Output Valid
2.6
2.6
2.8
2.8
3.0
3.0
3.4
3.4
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
Data Output Hold After CLK Rise
Clock to High-Z[20, 21, 22]
Clock to Low-Z[20, 21, 22]
OE HIGH to Output High-Z[20, 21, 22]
OE LOW to Output Low-Z[20, 21, 22]
1.0
1.0
0
1.0
1.0
0
1.3
1.3
0
1.3
1.3
0
tCHZ
2.6
2.6
2.8
2.8
3.0
3.0
3.4
3.4
tCLZ
tEOHZ
tEOLZ
Set-up Times
tAS
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
CEN Set-up Before CLK Rise
WE, BWx Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tDS
tCENS
tWES
tALS
tCES
Hold Times
tAH
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
WE, BWx Hold After CLK Rise
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
tALH
tCEH
Shaded areas contain advance information.
Notes:
19. This part has a voltage regulator internally; t
is the time power needs to be supplied above V minimum initially, before a Read or Write operation can be
DD
Power
initiated.
20. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ EOLZ
EOHZ
21. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
EOHZ
EOLZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
23. Timing reference is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05555 Rev. *A
Page 22 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Switching Waveforms
Read/Write/Timing[25, 26, 27]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
x
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
25. For this waveform ZZ is tied LOW.
26. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH,CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
27. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.
Document #: 38-05555 Rev. *A
Page 23 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Switching Waveforms (continued)
NOP,STALL and DESELECT Cycles[25, 26, 28]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
ZZ Mode Timing[29, 30]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
28. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
29. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
30. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05555 Rev. *A
Page 24 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
CY7C1370D-250AXC
CY7C1372D-250AXC
CY7C1370D-250BGC
CY7C1372D-250BGC
CY7C1370D-250BZC
CY7C1372D-250BZC
CY7C1370D-225AXC
CY7C1372D-225AXC
CY7C1370D-225BGC
CY7C1372D-225BGC
CY7C1370D-225BZC
CY7C1372D-225BZC
CY7C1370D-200AXC
CY7C1372D-200AXC
CY7C1370D-200BGC
CY7C1372D-200BGC
CY7C1370D-200BZC
CY7C1372D-200BZC
CY7C1370D-167AXC
CY7C1372D-167AXC
CY7C1370D-167BGC
CY7C1372D-167BGC
CY7C1370D-167BZC
CY7C1372D-167BZC
Package Type
250
A100RA Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Commercial
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
A100RA Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
225
200
167
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
A100RA Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
A100RA Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Document #: 38-05555 Rev. *A
Page 25 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Ordering Information (continued)
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
CY7C1370D-250AXI
CY7C1372D-250AXI
CY7C1370D-250BGI
CY7C1372D-250BGI
CY7C1370D-250BZI
CY7C1372D-250BZI
CY7C1370D-225AXI
CY7C1372D-225AXI
CY7C1370D-225BGI
CY7C1372D-225BGI
CY7C1370D-225BZI
CY7C1372D-225BZI
CY7C1370D-200AXI
CY7C1372D-200AXI
CY7C1370D-200BGI
CY7C1372D-200BGI
CY7C1370D-200BZI
CY7C1372D-200BZI
CY7C1370D-167AXI
CY7C1372D-167AXI
CY7C1370D-167BGI
CY7C1372D-167BGI
CY7C1370D-167BZI
CY7C1372D-167BZI
Package Type
250
225
200
167
A100RA Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Industrial
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
A100RA Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
A100RA Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
A100RA Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Lead-free BG and BZ packages
(Ordering Code: BGX, BZX) will be available in 2005.
Document #: 38-05555 Rev. *A
Page 26 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
SEE DETAIL
A
(ꢀX)
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
51-85050-*A
0°-7°
0.60 0.ꢁ5
0.20 MIN.
ꢁ.00 REF.
DETAIL
A
Document #: 38-05555 Rev. *A
Page 27 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05555 Rev. *A
Page 28 of 30
CY7C1370D
CY7C1372D
PRELIMINARY
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 MM BB165D
51-85180-**
ZBT is a trademark of Integrated Device Technology. NoBL and No Bus Latency are trademarks of Cypress Semiconductor
Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05555 Rev. *A
Page 29 of 30
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1370D
CY7C1372D
PRELIMINARY
Document History Page
Document Title: CY7C1370D/CY7C1372D 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05555
Orig. of
REV.
**
ECN No. Issue Date Change
Description of Change
254509
276690
See ECN
See ECN
RKF
VBL
New data sheet
*A
Changed TQFP pkg to Lead-free TQFP in Ordering Information section
Added comment of Lead-free BG and BZ packages availability
Document #: 38-05555 Rev. *A
Page 30 of 30
相关型号:
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