CY7C1370DV25-200AXCT [CYPRESS]
ZBT SRAM, 512KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100;
| 型号： | CY7C1370DV25-200AXCT |
| 厂家： | 
CYPRESS |
| 描述： | ZBT SRAM, 512KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总35页 (文件大小：679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THIS SPEC IS OBSOLETE
Spec No: 38-05558
Spec Title: CY7C1370DV25/CY7C1372DV25, 18-MBIT
(512K X 36/1M X 18) PIPELINED SRAM WITH
NOBL(TM) ARCHITECTURE
Replaced by: NONE
CY7C1370DV25
CY7C1372DV25
18-Mbit (512K × 36/1M × 18)
Pipelined SRAM with NoBL™ Architecture
18-Mbit (512K
× 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
The CY7C1370DV25 and CY7C1372DV25 are 2.5 V, 512K × 36
■ Pin-compatible and funequivalent to ZBT™
and 1M × 18 synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL logic, respectively. They are designed to
support unlimited true back-to-back read/write operations with
no wait states. The CY7C1370DV25 and CY7C1372DV25 are
equipped with the advanced NoBL logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent write/read
transitions. The CY7C1370DV25 and CY7C1372DV25 are
pin-compatible and functionally equivalent to ZBT devices.
■ Supports 200-Ms with zero wait states
❐ Available sand 167 MHz
■ Internally sr controo eliminate the need
to use as
■ Fully reoutpued operation
■ Byte writ
■ Single 2.5 V core power
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
.
■ 2.5 V I/O power supp
■ Fast clock-to-output t
❐ 3.0 ns (for 200-MHz d
■ Clock enable (CEN) pin to suspend peration
■ Synchronous self-timed writes
operations are controlled by the byte write selects
BWd for CY7C1370DV25 and BWa–BWb for
1372DV25) and a write enable (WE) input. All writes are
ucted won-chip synchronous self-timed write circuitry.
■ Available in JEDEC-standard Pb-freTQFP
Pb-free 165-ball FBGA packages
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability – linear or interleaved burst ord
■ “ZZ” sleep mode option and stop clock option
ree shronous chip enables (CE1, CE2, CE3) and an
asyncnous output enable (OE) provide for easy bank
seleon and output three-state control. In order to avoid bus
ctention, the output ers are synchronously three-stated
uring the data portorite sequence.
For a complete lof related umentation, click here.
Selection Guide
Description
Maximum access time
200 z
.0
7 MHz Unit
3.
70
ns
Maximum operating current
300
mA
mA
Maximum CMOS standby current
70
Errata: For information on silicon errata, see “Errata” on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05558 Rev. *P
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 3, 2016
CY7C1370DV25
CY7C1372DV25
Logic Block Diagram – CY7C1370DV25
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
ADV/LD
C
CLK
CEN
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
A
E
WRITE REGISTRY
ND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
WRITE
DRIVERS
DQP
DQP
DQP
DQP
a
b
c
d
A
M
P
b
BW
BW
c
S
T
E
R
S
F
d
E
R
S
S
W
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ
CE1
CE2
CE3
ROL
ZZ
Document Number: 38-05558 Rev. *P
Page 2 of 34
CY7C1370DV25
CY7C1372DV25
Logic Block Diagram – CY7C1372DV25
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
ADV/LD
C
WRITE DRESS
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
WRITE REGISTRY
DATA COHEREN
NTROL LOGI
A
R
E
G
I
MEMORY
ARRAY
E
B
U
F
DQs
DQP
DQP
WRITE
DRIVERS
BW
S
T
E
E
R
I
A
M
P
a
F
b
S
T
E
R
S
b
E
R
S
S
N
G
WE
E
E
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Document Number: 38-05558 Rev. *P
Page 3 of 34
CY7C1370DV25
CY7C1372DV25
Contents
Pin Configurations ...........................................................5
Pin Definitions ..................................................................7
Functional Overview ........................................................9
Single Read Accesses ................................................9
Burst Read Accesses ..................................................9
Single Write Acces........................................9
Burst Write Ac.....................................9
Sleep Mode ..................................10
Interleavle ...............................10
Linear .................................10
ZZ Moeristic.................10
Truth Tab......................11
Partial Trad/W..............12
Partial Trutr Read................12
IEEE 1149.1 Serial Bound[18]) .....13
Disabling the JTAG .......................
Test Access Port ........................1
PERFORMING A T.........................
TAP REGISTERS .................................3
TAP Instruction Set ........................................14
TAP Controller State Diagram ............................15
TAP Controller Block Diagram ..........................
TAP Timing .....................................................
TAP AC Switching Characteristics .................
2.5 V TAP AC Test Conditions ............................
2.5 V TAP AC Output Load Equivalent ............
TAP DC Electrical Characteristics and
Instruction Codes ...........................................................19
Boundary Scan Order ....................................................20
Maximum Ratings ...........................................................21
Operating Range .............................................................21
Electrical Characteristics ...............................................21
Capacitance ....................................................................22
Thermal Resistance ........................................................22
AC Test Loads and Waveforms .....................................22
Switching Characteristics ..............................................23
Switching Waveforms ....................................................24
Ordering Information ......................................................26
Ordering Code Definitions .........................................26
Package Diagrams ..........................................................27
Acronyms ........................................................................29
Document Conventions .................................................29
Units of Measure .......................................................29
Errata ...............................................................................30
Part Numbers Affected ..............................................30
Product Status ...........................................................30
Ram9 NoBL ZZ Pin & JTAG Issues
Summary ...............................................................30
ent History Page .................................................32
Solutions, and Legal Information ......................34
orldwiSales and Design Support .......................34
Produ....................................................................34
PS® Solutions ......................................................34
press Developer Community .................................34
Technical Support ..................................................34
Operating Conditions ..........................................
Scan Register Sizes .......................................................19
Identification Register Definitions ................................19
Document Number: 38-05558 Rev. *P
Page 4 of 34
CY7C1370DV25
CY7C1372DV25
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1]
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
78
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
7
0
69
68
67
66
65
64
63
62
6
54
53
52
51
80
79
V
V
DDQ
V
V
V
NC
DQPa
DQa
DQa
DDQ
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
V
V
SS
SS
SS
DQc
DQc
NC
NC
DQb
DQb
DQb
DQb
DQc
DQc
DQb
DQb
9
9
V
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
10
11
12
13
14
15
16
2
23
24
2
27
28
29
30
V
SS
SS
V
V
DDQ
DDQ
V
DQa
DQa
V
NC
Q
DDQ
DQc
DQc
NC
D
DQb
DQb
NC
C25
(512K × 36)
SS
V
V
DD
C
DD
CY7C1372DV25
(1M × 18)
NC
NC
V
V
ZZ
DD
DD
V
SS
ZZ
D
DQd
DQa
DQa
DQd
V
DDQ
V
V
DQa
DQa
NC
NC
V
V
DDQ
V
SS
SS
DQd
DQd
DQd
DQd
C
V
SS
V
SS
SS
V
V
DDQ
DD
DDQ
DDQ
DQd
DQd
DQPd
DQa
DQa
DQP
C
NC
NC
NC
NC
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see “Errata” on page 30.
Document Number: 38-05558 Rev. *P
Page 5 of 34
CY7C1370DV25
CY7C1372DV25
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout [2, 3]
CY7C1370DV25 (512K × 36)
1
2
A
3
4
5
6
7
8
9
A
10
A
11
NC
NC/576M
NC/1G
DQP
ADV/LD
A
B
C
D
CE1
BWc
BWd
VSS
VDD
BWb
BWa
VSS
VSS
CE3
CLK
VSS
VSS
CEN
WE
CE2
DQ
DDQ
OE
VSS
VDD
A
A
NC
VSS
VSS
VDDQ
VDDQ
NC
DQb
DQPb
DQb
D
c
NC
VDDQ
VD
VDD
DD
VDD
VD
V
VSS
VSS
VSS
VSS
VS
VS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
E
F
G
H
J
DQd
DQd
DQd
DQ
Q
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
K
L
DQd
DQd
NC
VDDQ
VD
VD
VSS
A
VSS
NC
VSS
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
DQa
DQPa
M
N
P
DQPd
NC/144M NC/72M
MODE NC/36M
T
TDO
NC/288M
A
TCK
A
A
A
A
R
× 18)
1
NC/576M
NC/1G
NC
2
A
3
4
CE3
7
8
9
A
10
A
11
A
A
B
C
D
CE1
BWb
NC
CEN
ADV/L
A
CE2
VDDQ
VDDQ
BWa
VSS
VSS
C
VSS
VSS
A
A
NC
WE
VSS
VSS
VSS
VDD
NC
DQb
VSS
VDD
DQ
VDDQ
NC
NC
DQPa
DQa
NC
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
VSS
VSS
VS
VSS
VSS
D
D
VDD
VDD
VDD
VDD
VD
VDDQ
VDDQ
VDD
NC
C
DQa
DQa
DQa
ZZ
E
F
NC
G
H
J
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ
Qa
Qa
C
NC
K
L
NC
NC
DQb
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VD
DDQ
NC
A
NC
NC
M
N
P
DQPb
NC/144M NC/72M
MODE NC/36M
TDI
TDO
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
R
Notes
2. Errata: The ZZ ball (H11) needs to be externally connected to ground. For more information, see “Errata” on page 30.
3. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 30.
Document Number: 38-05558 Rev. *P
Page 6 of 34
CY7C1370DV25
CY7C1372DV25
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
Input-
synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
BWa, BWb,
Input-
Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
BWc, BWd synchroing edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
Pc, BWd controls DQd and DQPd.
WE
nable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
e assered LOW to initiate a write sequence.
ADV/LD
ance/ut used to advance the on-chip address counter or load a new address. When
IGH (sserted LOW) the internal burst counter is advanced. When LOW, a new address
can be device for an access. After being deselected, ADV/LD should be driven LOW in
oraddress.
CLK
CE1
CE2
CE3
OE
Input-clock ed to capall synchronous inputs to the device. CLK is qualified with CEN. CLK is
ized if CEs acLOW.
Inpu
le 1 inpactive LW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronoto select/elect thevice.
Input-
Chip enab2 inpctive HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 select/deect the dev
Input-
Chip ele 3 inpuctive n the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 elect/delect
Input-
Output enable, active the syhronous logic block inside the device to control
asynchronous the direction of the I/O /O pine allowed to behave as outputs. When deasserted
HIGH, I/O pins are ths inpuata pins. OE is masked during the data portion of a
write sequence, durinhen erging from a deselected state and when the device has
been deselected.
CEN
DQS
Input-
Clock enable input, active LOW. Whasserted LOW the oignal is recognized by the SRAM.
synchronous When deasserted HIGH the clock sigis masked. Since dssertiN does not deselect the device,
CEN can be used to extend the prous cycle when reired.
I/O-
Bidirectional data I/O lines. As inthey feed in-chip data reger that is triggered by the
synchronous rising edge of CLK. As outputs, they dthe dacontain the memory tion specified by A[17:0]
during the previous clock rise of the read cyclThe directiof the pins is olled by OE and the
internal control logic. When OE is asserted Lthe pins can behave as outp. HIGH, DQa–DQd
are placed in a three-state condition. The outare automatically threeted durg the data portion
of a write sequence, during the first clock when ging from a deseled state, and n the device
is deselected, regardless of the state of OE.
DQPX
I/O-
Bidirectional data parity I/O lines. Functionally, these signaare identical DQs. Dwrite
synchronous sequences, DQPa is controlled by BWa, DQPb is controlled BWb, DQPc is ntrolled by Bc, and
DQPd is controlled by BWd.
MODE
Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the terleaverst order. Pulled
LOW selects the linear burst order. MODE should not change states dng operation. hen left floating
MODE will default HIGH, to an interleaved burst order.
Document Number: 38-05558 Rev. *P
Page 7 of 34
CY7C1370DV25
CY7C1372DV25
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
TDO [4]
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
synchronous
TDI [4]
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
inpu
sync
TMS [4]
n controls the Test access port state machine. Sampled on the rising edge of TCK.
TCK [4]
VDD
lock iJTAG circuitry.
y Powts to the core of the device.
VDDQ
power r the I/O circuitry.
supply
VSS
NC
Grou
the dee. Shoue connected to ground of the system.
ects. Thin is not cnected to the die.
–
–
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
e pins are nonnectd. They will be used for expansion to the 36M, 72M, 144M, 288M, 576M,
and 1G dsities.
ZZ [5]
Input-
ZZ “sleep” input. Thiaces tdevice in a non-time critical “sleep” condition with
asynchronous data integrity preservation, is pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Notes
4. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 30.
5. Errata: The ZZ pin needs to be externally connected to ground. For more information, see “Errata” on page 30.
Document Number: 38-05558 Rev. *P
Page 8 of 34
CY7C1370DV25
CY7C1372DV25
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (read
or write) is maintained throughout the burst sequence.
Functional Overview
The
CY7C1370DV25
and
CY7C1372DV25
are
synchronous-pipelined Burst NoBL SRAMs designed
specifically to eliminate wait states during write/read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (C. If CEN is HIGH, the clock signal
is not recognized anl states are maintained. All
synchronous operd with CEN. All data outputs
pass through oulled by the rising edge of the
clock. Maximthe clock rise (tCO) is 3.0 ns
(200-MHz d
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented is loaded into the
address register. The write signals are latched into the control
logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b for
CY7C1372DV25). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
Accesses asserte chip enables
(CE1, CEe risinclock. If clock
enable (CW anerted LOW, the
address prethe deviThe access can
either be a read or write ong on the tus of
the write enable (WE). Bd to condt byite
operations.
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 & DQa,b/DQPa,b for
CY7C1372DV25) (or a subset for byte write operations, see
e Cycle Description table for details) inputs is latched into the
and the write is complete.
Write operations are quarite enabWE). All es
are simplified with on-chip nous self-timrite ciritry.
Three synchronous chip enables (1, CE2, 3) and an
asynchronous output enable (OE) slify depth pansion
operations (reads, writes, and desel) are piped. A
should be driven LOW once the devas bdes
order to load a new address for the next ration.
ta written during the write operation is controlled by BW
,c,d for CY7C1370DV25 and BWa,b for CY7C1372DV25)
s. The CY7C1370DV25/CY7C1372DV25 provides byte
capaty that is described in the Write Cycle Description
ble. Aerting the write enable input (WE) with the selected
byte te select (BW) input will selectively write to only the
ded bytes. Bytes noselected during a byte write operation
Single Read Accesses
A read access is initiated when the following
satisfied at clock rise: (1) CEN is asserted LOW,
and CE3 are all asserted active, (3) the write enable inignal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and cont
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 3.0ns (200-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will three-state following the next clock rise.
remain unalter
A
synchronous self-timed write
mechanism has beprod to simplify the write operations.
Byte write capabhas beeluded in order to greatly simplify
read/modify/wsequences, hich can be reduced to simple
byte write ors.
causthe C1370DV25 aCY7C1372DV25 are
commI/O devicesdata should noiven into the device
whie outputs are active. The utpuable (OE) can be
deassHIGH before preseng data to the DQ and DQP
(DQa,b,c,dPa,b,c,d for CY7370DV25 and /DQPa,b for
CY7C137225) inputs. ng so will th-sthe output
drivers. As
a
safprecautioDQ DQP
(DQa,b,c,d/DQPa,b,c,d fCY7C1370DVand DQa,b/DPa,b for
CY7C1372DV25) aautomatically tated during the data
portion of a write cycle, regardlesf the of OE.
Burst Write Accesses
The CY7C1370DV25/CY7C1DV25 has an on-chip burst
counter that allows the user the to supply a single address
and conduct up to four write operas without reasserting the
address inputs. ADV/LD must be driven LOW in order to load the
initial address, as described in Single Write Accesses on page 9.
When ADV/LD is driven HIGH on the subsequent clock rise, the
chip enables (CE1, CE2, and CE3) and WE inputs are ignored
and the burst counter is incremented. The correct BW (BWa,b,c,d
for CY7C1370DV25 and BWa,b for CY7C1372DV25) inputs must
be driven in each cycle of the burst write in order to write the
correct bytes of data.
Burst Read Accesses
The CY7C1370DV25 and CY7C1372DV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load a
new address into the SRAM, as described in Single Read
Accesses. The sequence of the burst counter is determined by
the MODE input signal. A LOW input on MODE selects a linear
burst mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
Document Number: 38-05558 Rev. *P
Page 9 of 34
CY7C1370DV25
CY7C1372DV25
Sleep Mode
Linear Burst Address Table
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior ng the “sleep” mode. CE1, CE2,
and CE3, must remae duration of tZZREC after the
ZZ input returns
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
InterleaveTable
(MODE =
First
Address
A1:A0
d
dress
A1:A0
Fourth
Address
A1:
00
01
10
11
01
0
11
10
00
0
11
10
01
00
ZZ Mode Electrical Characteris
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
onditis
Min
Max
80
Unit
mA
ns
–
tZZS
V
Z
–
2tCYC
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parametesampled
2tCYC
–
ns
tRZZI
ZZ Inactive to exit sleep current This paramr is sampled
0
ns
Document Number: 38-05558 Rev. *P
Page 10 of 34
CY7C1370DV25
CY7C1372DV25
Truth Table
The truth table for CY7C1370DV25/CY7C1372DV25 follows. [6, 7, 8, 9, 10, 11, 12]
Operation
Address Used CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect cycle
None
None
H
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L
L
H
X
L–H
L–H
Tri-state
Tri-state
Continue deselect cy
Read cycle (beg
Read cycle (
NOP/dumm
Dummy r
Write cyc
Write cycle burst)
NOP/write abort (begin b
Write abort (continue
Ignore clock edge (stal
Sleep mode
External
Next
L–H Data out (Q)
L–H Data out (Q)
X
L
H
L
L
External
Next
H
H
X
X
X
X
X
X
L–H
L–H
Tri-state
Tri-state
X
L
H
L
External
Next
L–H Data in (D)
L–H Data in (D)
X
L
H
L
X
L
L
ne
H
H
X
X
L–H
L–H
L–H
X
Tri-state
Tri-state
–
t
X
X
X
H
X
X
X
X
X
Cent
None
Tri-state
Notes
6. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BW = valid signifies
x
that the desired byte write selects are asserted, see Write Cycle Description table for details.
7. Write is defined by WE and BW . See Write Cycle Description table for details.
X
8. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
9. The DQ and DQP pins are controlled by the current cycle and the OE signal.
10. CEN = H inserts wait states.
11. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
12. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ and DQP = three-state when OE is
s
X
inactive or when the device is deselected, and DQ = data when OE is active.
s
13. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document Number: 38-05558 Rev. *P
Page 11 of 34
CY7C1370DV25
CY7C1372DV25
Partial Truth Table for Read/Write
The partial truth table for Read/Write for CY7C1370DV25 follows. [14, 15, 16, 17]
Function (CY7C1370DV25)
WE
H
L
BWd
X
H
H
H
H
H
H
H
H
L
BWc
X
H
H
H
H
L
BWb
X
H
H
L
BWa
X
H
L
Read
Write – No bytes writ
Write byte a – (D
Write byte b
Write bytes
L
L
H
L
L
L
Write bytc)
Write byt
L
H
H
L
H
L
L
L
Write bytes
L
L
H
L
Write bytes c, b, a
L
L
L
Write byte d – (DQd a
Write bytes d, a
L
H
H
H
H
L
H
H
L
H
L
L
L
Write bytes d, b
L
L
H
L
Write bytes d, b, a
L
L
L
Write bytes d, c
L
H
H
L
H
L
Write bytes d, c, a
L
L
Write bytes d, c, b
L
L
L
H
L
Write all bytes
L
L
L
L
Partial Truth Table for Read/Write
The partial truth table for Read/Write for CY7C1372DV25 follo[14, 15, 16, 17]
Function (CY7C1372DV25)
WE
H
BWb
BWa
x
Read
x
H
H
L
Write – no bytes written
Write byte a – (DQa and DQPa)
Write byte b – (DQb and DQPb)
Write both bytes
H
L
L
L
L
L
Notes
14. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BW = valid signifies
x
that the desired byte write selects are asserted, see Write Cycle Description table for details.
15. Write is defined by WE and BW . See Write Cycle Description table for details.
X
16. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
17. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document Number: 38-05558 Rev. *P
Page 12 of 34
CY7C1370DV25
CY7C1372DV25
IEEE 1149.1 Serial Boundary Scan (JTAG [18]
)
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
The CY7C1370DV25/CY7C1372DV25 incorporates a serial
boundary scan test access port (TAP).This part is fully compliant
with 1149.1. The TAP operates using JEDEC-standard 3.3 V or
2.5 V I/O logic levels.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
The CY7C1370DV25/CY7C1372DV25 contains
a
TAP
controller, instruction reundary scan register, bypass
register, and ID regi
Disabling th
Instruction Register
It is possiblAM witut using the JTAG
feature. To troller, ust be tied LOW
(VSS) to the dand TMS are
internally may d. They may
alternately to VDp resistor. TDO
should be leonnected, the device will
come up in a reset state whre with thation
of the device.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 16. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Test Access Port (T
Test Clock (TCK)
s Register
The test clock is used only with the Tcontrollel inputs
captured on the rising edge of TCKoutputs adrive
the falling edge of TCK.
e time when serially shifting data through registers, it is
mes advantageous to skip certain chips. The bypass
er is a single-bit register that can be placed between the
and TDballs. This allows data to be shifted through the
Test Mode Select (TMS)
The TMS input is used to give commands to the T
and is sampled on the rising edge of TCK. It is allo
this ball unconnected if the TAP is not used. The b
internally, resulting in a logic HIGH level.
AM wminimal delay. The bypass register is set LOW (VSS
when tBYPASS instruction is executed.
)
Bndary Scan Regist
he boundary scan egiis connected to all the input and
bidirectional balls n the SR
Test Data-In (TDI)
The TDI ball is used to serially input information into the registe
and can be connected to the input of any of the registers. Th
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
The boundaran register is loaded with the contents of the
RAM I/O riwhe TAP contros in the Capture-DR state
d is tplacetween the TDd TDO balls when the
contror is moveto the Shift-ate. The EXTEST,
SAE/PRELOAD and SAMPLE nstns can be used to
captue contents of the I/O ri.
The BouScan Order oage 20 show er in which
the bits are nnected. Eacbit correspondo onhe bumps
on the SRAM package. e MSB of the ister is ccted to
TDI and the LSB is cected to TDO
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 19).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Identification (ID) Register
The ID register is loaded wia vendor-spific, 32-bit code
during the Capture-DR stahen the IDCODE command is
loaded in the instruction registhe IDCODE is hardwired into
the SRAM and can be shifted oen the TAP controller is in
the Shift-DR state. The ID register a vendor code and other
information described in Identification Register Definitions on
page 19.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Note
18. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 30.
Document Number: 38-05558 Rev. *P
Page 13 of 34
CY7C1370DV25
CY7C1372DV25
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK captured in the boundary scan
register.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail bel
Instructions are loacontroller during the Shift-IR
state when the iis placed between TDI and
TDO. During ns are shifted through the
instruction rI and TO balls. To execute
the instruct, the Ttroller needs to be
moved inte.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
EXTEST
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
The EXTEST instruction end data to be driven
out through the system oinstructioscts
the boundary scan reected foserial ass
between the TDI and DR conter state.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
d between the TDI and TDO balls. The advantage of the
S instruction is that it shortens the boundary scan path
ultiple devices are connected together on a board.
IDCODE
The IDCODE instruction causes a vdor-speci32-bit cod
to be loaded into the instruction ster. It alplaces
instruction register between the TDd TDO bs and
the IDCODE to be shifted out of teviwhen
controller enters the Shift-DR state.
ST Output Bus Tri-State
E Stanrd 1149.1 mandates that the TAP controller be able
put thoutput bus into a tri-state mode.
The IDCODE instruction is loaded into the instru
upon power-up or whenever the TAP controller
logic reset state.
The undary scan register has a special bit located at bbit #89
(f165-ball FBGA page). When this scan cell, called the
xtest output bus trtis latched into the preload register
during the “UpdatR” stathe TAP controller, it will directly
control the statf the output bus) pins, when the EXTEST is
entered as thrent instruction. When HIGH, it will enable the
utput bufs te the output When LOW, this bit will
ace thoutput bo a high Z con.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TA
controller is in a Shift-DR state. It also places all SRAM outpu
into a high Z state.
SAMPLE/PRELOAD
This can be set by entering tPLE/PRELOAD or
EXTcommand, and then shiftthe dered bit into that cell,
during “Shift-DR” state. ring “Update,” the value
loaded inat shift-registcell will latche preload
register. When the EXTEinstruction is nteres bit will
directly control the outpQ-bus pins. Ne that this bpreset
HIGH to enable the put when the e is powered-up, and
also when the TAP ontroller is in “Togic-Reset” state.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
Reserved
These instructions are not emented but are reserved for
future use. Do not use these intions.
Document Number: 38-05558 Rev. *P
Page 14 of 34
CY7C1370DV25
CY7C1372DV25
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RU
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-IR
0
1
0
XIT2-D
EXIT2-IR
1
UPD-DR
UTE-IR
1
0
1
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05558 Rev. *P
Page 15 of 34
CY7C1370DV25
CY7C1372DV25
TAP Controller Block Diagram
0
0
Bypass Register
2
1
Selection
Circuitry
Instruction Register
31 30 29 .
S
election
TDO
Circuitr
y
.
.
2
1
0
Identification Register
x
.
.
.
.
. 2 1 0
Boundary Scan Register
P CONTROLLER
T
T
TAP Timing
ng
1
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDO
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 38-05558 Rev. *P
Page 16 of 34
CY7C1370DV25
CY7C1372DV25
TAP AC Switching Characteristics
Over the Operating Range
Parameter [19, 20]
Clock
Description
Min
Max
Unit
tTCYC
TCK cle time
ency
time
W time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Ti
tTDOV
k LOW
clock Llid
–
0
10
–
ns
ns
tTDOX
Set-up Times
tTMSS
TMS clock rise
TDlock ris
Captuo TCK rise
5
5
5
–
–
–
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
tTDIH
TMS hold after Tclock rise
TDI hold after cloise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after ce
Notes
19. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
20. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document Number: 38-05558 Rev. *P
Page 17 of 34
CY7C1370DV25
CY7C1372DV25
2.5 V TAP AC Test Conditions
2.5 V TAP AC Output Load Equivalent
1.25V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination suge .......................... 1.25 V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC aracand Operating Conditions
(0 °C < TA D = 2.5 ss otherwise noted)
Parameter [21]
Outpu
Outpu
Output LOage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input load current
Test Conditions
IOH = –mA, VDDQ = 2.5 V
IOH = –0 µA, VDDQ = 2.5 V
OL = 80 mA, VDDQ = 2.5 V
Min
2.0
2.1
–
Max
Unit
V
VOH1
VOH2
VOL1
VOL2
VIH
–
–
0.4
V
V
L = 100 µ
VDDQ = 2.5 V
–
0.2
V
VDDQ = 2.5 V
VDDQ = 2.5 V
1.7
–0.3
–5
VDD + 0.3
0.7
V
VIL
V
IX
5
µA
Note
21. All voltages referenced to V (GND).
SS
Document Number: 38-05558 Rev. *P
Page 18 of 34
CY7C1370DV25
CY7C1372DV25
Scan Register Sizes
Register Name
Bit Size (× 18)
Bit Size (× 36)
Instruction
3
1
3
1
Bypass
ID
32
89
32
89
Boundary scaGA package)
Identifir De
Ins
Revision number (31:29)
Cypress device ID (28:
Cypress JEDEC ID (1
370DV25
CY7C1372DV25
000
Description
000
Reserved for version number.
Reserved for future use.
101100100101
00010100
01011001000100101
00000110100
Allows unique identification of
SRAM vendor.
ID register presence (0)
1
Indicate the presence of an ID
register.
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ts. Placthe boundary scan gister between TDI and TDO. Forces
all SRAM outputs to high Z se.
IDCODE
001
010
Loads the ID register with e vendor ID code aplaces tgister between TDI and TDO.
This operation does noect SRAM operas.
SAMPLE Z
Captures I/O ring contentsces the bodaan register ben TDI and TDO. Forces
all SRAM output drivers to a h Z st.
RESERVED
011
100
Do Not Use: This instruction is reed for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places toundary scan register tween TDI and TDO. Does
not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future u.
Places the bypass register between TDI and TDOThis operatiodot affect SRAM
operations.
Document Number: 38-05558 Rev. *P
Page 19 of 34
CY7C1370DV25
CY7C1372DV25
Boundary Scan Order
165-ball FBGA [22, 23]
Bit #
1
Ball ID
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
4
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
0
81
82
83
85
86
87
8
89
Ball ID
G1
D2
E2
N6
2
3
4
F2
5
G2
H1
H3
J1
8
R9
8
B9
9
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
C10
A8
K1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
L1
B8
M1
J2
A7
7
K2
6
L2
A6
M2
N1
N2
P1
B5
5
A4
B4
R1
R2
P3
B3
A3
A
R3
P2
H10
G11
F11
E11
D11
G10
F10
E10
2
R4
4
B1
A1
P6
C1
D1
R6
Internal
E1
F1
Notes
22. Balls which are NC (No Connect) are pre-set LOW.
23. Bit# 89 is pre-set HIGH.
Document Number: 38-05558 Rev. *P
Page 20 of 34
CY7C1370DV25
CY7C1372DV25
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage
(per MIL-STD-883, method 3015) ..........................> 2001 V
Storage temperature ................................ –65 °C to +150 °C
Latch-up current ....................................................> 200 mA
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Operating Range
Supply voltage on VND .......–0.5 V to +3.6 V
Supply voltage oGND ...... –0.5 V to +VDD
DC to outputs ....–0.5 V to VDDQ + 0.5 V
Range
Ambient Temperature
VDD/VDDQ
Commercial
0 °C to +70 °C
2.5 V ± 5%
Electrictics
Over the e
Parameter [
Powee
I/O
Test Conditions
Min
2.375
2.375
2.0
Max
Unit
VDD
VDDQ
VOH
VOL
VIH
2.625
V
V
for 2.I/O
VDD
Outputage
Output LOW voltag
Input HIGH volta26]
Input LOW voltag6]
for 2V I/O, IOH = 1.0 mA
for 2.5 V I/O, I1.0 mA
for 2.5
–
V
–
0.4
V
1.7
VDD + 0.3 V
V
VIL
fo
–0.3
–5
0.7
5
V
IX
Input leakage currept ZZ
and MODE
A
Input current of MODE
–30
–
–
5
A
A
A
A
A
mA
Input current of ZZ
VSS
–5
–
–
Input = VD
30
5
IOZ
IDD
Output leakage current
VDD operating supply
GND VDD, output disab
–5
VDD = MaxT = 0 mA,
f = fMAX = 1/t
.0-nscycle,
MHz
–
–
–
300
6.0-nscycle,
167 MHz
275
0
14
70
mA
mA
mA
mA
ISB1
Automatic CE power-down
current – TTL inputs
Max. VDD, device desed,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
5.0-nscycle
200 MHz
6.0-ncle,
16Hz
ISB2
Automatic CE power-down
current – CMOS inputs
Max. VDD, device deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V, grades
f = 0
Aspeed
ISB3
Automatic CE power-down
current – CMOS Inputs
Max. VDD, device deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V, 200 MHz
f = fMAX = 1/tCYC
5.0-nscyc
–
–
130
125
80
mA
mA
mA
6.0-nscycle,
167 MHz
ISB4
Automatic CE power-down
current—TTL Inputs
Max. VDD, device deselected,
VIN VIH or VIN VIL, f = 0
All speed
grades
Notes
24. Overshoot: V
< V + 1.5 V (Pulse width less than t
/2), undershoot: V
> –2 V (Pulse width less than t
/2).
CYC
IH(AC)
DD
CYC
IL(AC)
25. T
: Assumes a linear ramp from 0 V to V
within 200 ms. During this time V < V and V
< V
.
Power-up
DD(min)
IH
DD
DDQ
DD
26. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05558 Rev. *P
Page 21 of 34
CY7C1370DV25
CY7C1372DV25
Capacitance
100-pin TQFP 165-ball FBGA
Parameter [27]
Description
Input capacitance
Test Conditions
Unit
Package
Package
CIN
TA = 25 C, f = 1 MHz,
DD = 2.5 V, VDDQ = 2.5 V
5
5
5
9
9
9
pF
pF
pF
V
CCLK
CI/O
Clock icitance
Iitance
Therma
100-pin TQFP 165-ball FBGA
Paramet
Descr
Test Conditions
Unit
Package
Package
JA
Thermal re
(junction
Test conditions follow standard test
and procedures for
28.66
20.7
C/W
measurthermal impedance, per
EIA/JES1.
JC
Ther
(juncti
4.08
4.0
C/W
AC Test Loads and Waverms
Fig4. AWaveforms
2.5 V I/O Test Load
2.5 V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
R = 50
90%
10%
Z = 50
0
10
L
GND
5 pF
= 1538
1 ns
s
V = 1.25 V
T
INCLUDING
JIG AND
SCOPE
(c
(a)
(b)
Note
27. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05558 Rev. *P
Page 22 of 34
CY7C1370DV25
CY7C1372DV25
Switching Characteristics
Over the Operating Range
-200
-167
Unit
Parameter [28, 29]
Description
Min
Max
Min
Max
[30]
tPower
Clock
tCYC
o the first access read or write
1
–
1
–
ms
ime
operauency
HIGH
5
–
200
–
6
–
167
–
ns
MHz
ns
FMAX
tCH
–
–
2.0
2.0
2.2
2.2
tCL
lock LO
–
–
ns
Output Times
tCO
Dafter CLise
Out valid
–
–
3.0
3.0
–
–
–
3.4
3.4
–
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
Data hold fter CLe
Clock to high Z , 32, 33]
Clock to low Z , 32, 33]
OE HIGH to ou31, 32
OE LOW to output low Z [31, 3
1.3
–
1.3
–
tCHZ
3.0
–
3.4
–
tCLZ
1.3
–
1.3
–
tEOHZ
tEOLZ
Set-up Times
tAS
3.0
–
3.4
–
0
Address set-up before CLK
Data input set-up before CLK ri
CEN set-up before CLK rise
WE, BWx set-up before CLK rise
ADV/LD set-up before CLK rise
Chip select set-up
1.4
1.4
1.4
1.4
4
1.4
–
–
–
–
–
1.5
1.5
1.5
1.5
1
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDS
tCENS
tWES
tALS
tCES
Hold Times
tAH
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
4
0.4
0.4
0.4
0.4
–
–
–
–
–
0.5
0.5
0.5
5
0.5
0.5
–
–
–
–
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
WE, BWx hold after CLK rise
ADV/LD hold after CLK rise
Chip select hold after CLK rise
tALH
tCEH
Notes
28. Timing reference 1.25 V when V
= 2.5 V.
DDQ
29. Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted.
30. This part has a voltage regulator internally; t is the time power needs to be supplied above V
initially, before a read or write operation can be initiated.
Power
DD(minimum)
31. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of Figure 4 on page 22. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ EOLZ
EOHZ
32. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
EOHZ
EOLZ
CHZ
CLZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
33. This parameter is sampled and not 100% tested.
Document Number: 38-05558 Rev. *P
Page 23 of 34
CY7C1370DV25
CY7C1372DV25
Switching Waveforms
Figure 5. Read/Write Cycle Timing [34, 35, 36]
1
2
3
4
5
6
7
8
9
10
t
CYC
CLK
t
t
CE
CL
CH
CE
A
BW
x
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
D
t
t
t
DOH
OEV
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
)
BT
AD
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
(A4+1)
DON’T CARE
UNDEFINED
Notes
34. For this waveform ZZ is tied LOW.
35. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
36. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 38-05558 Rev. *P
Page 24 of 34
CY7C1370DV25
CY7C1372DV25
Switching Waveforms (continued)
Figure 6. NOP, STALL and DESELECT Cycles [37, 38, 39]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
B
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
REA
Q
ALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
CARE
UNDEFINED
Figude Timg [40, 41]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
DEST or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes
37. For this waveform ZZ is tied LOW.
38. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
39. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
40. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
41. I/Os are in high Z when exiting ZZ sleep mode.
Document Number: 38-05558 Rev. *P
Page 25 of 34
CY7C1370DV25
CY7C1372DV25
Ordering Information
Cypress offers other versions of this type of product in different configurations and features. The following table contains only the
list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/procts, or contact your local sales representative.
Cypress maintains a work of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, v.cypress.com/go/datasheet/offices.
Speed
(MHz)
ackage
gram
Operating
Range
Part and Package Type
de
167 67AX
C25-167
050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1370DV25
51-8518ball FBGA (13 × 15 × 1.4 mm)
51-850 100n TQFP (14 × 20 × 1.4 mm) Pb-free
51180 165all FBGA (13 × 15 × 1.4 mm)
200 CY7C1370D
CY7C1370DV
Commercial
Ordering Code Definitions
CY
7
C 137X D V25 - XXXX
X
C
T
C to +7C
ent = ded
XX = r BZ
TQFP
-ball FBA
Speed GradeXX = 167 MHz or 0 M
V25 = 2.5 VDD
Process Tology: D 9
Part IdentifierX = 10 or 13
1370 = PL, 512Kb × (18Mb)
1372 = PL, 1Mb × 8Mb)
Technology Code: C = OS
Marketing Code: 7 = SRA
Company ID: CY = Cypress
Document Number: 38-05558 Rev. *P
Page 26 of 34
CY7C1370DV25
CY7C1372DV25
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 38-05558 Rev. *P
Page 27 of 34
CY7C1370DV25
CY7C1372DV25
Package Diagrams (continued)
Figure 9. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
585180 *F
Document Number: 38-05558 Rev. *P
Page 28 of 34
CY7C1370DV25
CY7C1372DV25
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
Chip Enable
Clock Enable
Symbol
°C
Unit of Measure
CEN
CMOS
EIA
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
millivolt
Complementary Metal Oxide Semiconductor
Electrolliance
Finray
MHz
µA
mA
mm
ms
mV
ns
FBGA
I/O
JEDEC
JTAG
LSB
ces Enng Council
Grou
ficant
Most Significa
nanosecond
ohm
MSB
NoBL
OE
No Bus La
%
percent
Output E
pF
V
picofarad
volt
SRAM
TAP
Static Randos Memory
Test Access Port
watt
TCK
TDI
Test Clock
Test Data-In
TDO
TMS
TQFP
TTL
Test Data-Out
Test Mode Select
Thin Quad Flat Pack
Transistor-Transistor Logic
Write Enable
WE
Document Number: 38-05558 Rev. *P
Page 29 of 34
CY7C1370DV25
CY7C1372DV25
Errata
This section describes the Ram9 NoBL ZZ pin and JTAG issues. Details include trigger conditions, the devices affected, proposed
workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
& Revision
Package Type
100-pin TQFP
165-ball FBGA
Operating Range
18MbAMs: CY7C137*DV25
Commercial
Product
All of the 9 18Mare qualified and available in production quantities.
Ram9 NoBin & JTta Summary
The following table defineplicable to Ram9 18Mb NoBL family devices.
Item
Issues
Descrin
Device
Fix Status
1. ZZ Pin
When asserted GH, thpin places
deviceina“sle”conditiothdataint
preserved.ThZ pin curry does
an internal pown resir and
cannot be left ting ernally
during normal moperat
18M-Ram9 (90nm)
For the 18M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
2. JTAG
During JTAG test mode, the
18M-R9 (90nm)
This issue will be fixed in the
new revision, which use the
65 nm technology. Please
contact your local sales rep for
availability.
Functionality circuitry does not perform a
datasheet.However, it is p
the JTAG test with these deS
mode”.
Document Number: 38-05558 Rev. *P
Page 30 of 34
CY7C1370DV25
CY7C1372DV25
1. ZZ Pin Issue
■ PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■ TRIGGER CONDI
Device operaleft floating.
■ SCOP
Wheting, the evice delivers incorrect data.
■ WO
Tie nally t
■ FIX STATUS
For the 18M Rames, there no plfix this issue.
2. JTAG Functionality
■ PROBLEM DEFINITION
The problem occurs only whehe device peratt mode.During this mode, the JTAG circuitry can perform
incorrectly by delivering the inrect datr the length.
■ TRIGGER CONDITIONS
Several conditions can trigger this failure m
1. The device can deliver an incorrect lengoperg in JTAG mode.
2. Some Byte Write inputs only recognize a el when JTAG mode.
3. Incorrect JTAG data can be read from the hen the input is tied HIGH g JTAG operation.
■ SCOPE OF IMPACT
The device fails for JTAG test. This does not impact thmal functionalithe device.
■ WORKAROUND
1.Perform JTAG testing with these devices in “BYPASS mode”.
2.Do not use JTAG test.
■ FIX STATUS
This issue will be fixed in the new revision, which use the 65 nm technology. Please conct your local ss rep foilability
Document Number: 38-05558 Rev. *P
Page 31 of 34
CY7C1370DV25
CY7C1372DV25
Document History Page
Document Title: CY7C1370DV25/CY7C1372DV25, 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05558
Orig. of
Change
Rev.
ECN No.
Issue Date
Description of Change
**
25450
2
CN
N
RKF
New data sheet.
*A
SYT
Updated Selection Guide (Removed 225 MHz frequency related information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [18]) (Edited description
for non-compliance with 1149.1).
Updated Electrical Characteristics (Removed 225 MHz frequency related
information).
Updated Switching Characteristics (Removed 225 MHz frequency related
information).
Updated Ordering Information (Added Pb-free information for 100-pin TQFP,
ball BGA and 165-ball FBGA package) and added comment for ‘Pb-free
BG kages availability’ below the Ordering Information.
*B
32607
P
UpdaPin Configurations (Address expansion pins/balls in the pinouts for
all pages are modified as per JEDEC standard).
Updted IEEE 1149.1 Serial Boundary Scan (JTAG [18]) (Updated TAP
Instruction Sdated OVERVIEW (description), updated EXTEST
(descriEXTEST Output Bus Tri-State)).
Updaracteristics (Modified Test Conditions for VOL, VOH
p
sistance (Changed JA and JC for 100-pin TQFP
d 6 Cto 28.66 and 4.08 C/W respectively, changed
19-balGA Package from 45 and 7 C/W to 23.8 and
ctivelyhanged JA and JC for FBGA Package from 46 and
.7 and 0 C/W respectively).
Orderinnformation (Updateart numbers) and removed comment
for ‘Pb-free Backages availabilibthe Ordering Information
*C
418125
See ECN
NXR
Changed tus from Preliminao Final.
Changedress of Cypress miconductoorporation from “3901 North
First Stre“198 Chamurt”.
Updated Eleal Charteristihanged the diption of IX parameter
from Input LoaCurreto Input Lge Current, cd the minimum and
maximum values oparameter (corresponding tnpurrent of MODE)
from –5 A and 30 –30A and 5 A, changehe minium and maximum
values of IX parameter responding to Inpurrent of ZZ) fr–30 A and
5 A to –5 A and 30 Adated Note 25
Updated Ordering Informaton (Updated rt numbers).
*D
475677
See ECN
VKN
Updated TAP AC Switching Charactetics (Changed nimum valuef tTH
and tTL parameters from 25 ns to ns, and maximlue of tTDOV
parameter from 5 ns to 10 ns).
,
Updated Maximum Ratings (Added the Maximm Rating fupply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated pambers).
*E
*F
2897278
3031731
03/22/2010
09/16/2010
NJY
NJY
Updated Ordering Information (Removed obsopart numbers).
Updated Package Diagrams.
Updated Ordering Information (Updated part numbers) and added Ordering
Code Definitions.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
*G
*H
3050869
3067198
10/07/2010
10/20/2010
NJY
NJY
Updated Ordering Information (Removed CY7C1370DV25-167BZI,
CY7C1370DV25-250AXC, and CY7C1370DV25-167AXI).
Updated Ordering Information (Updated part numbers).
Document Number: 38-05558 Rev. *P
Page 32 of 34
CY7C1370DV25
CY7C1372DV25
Document History Page (continued)
Document Title: CY7C1370DV25/CY7C1372DV25, 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05558
Orig. of
Rev.
ECN No.
Issue Date
Description of Change
Updated Package Diagrams.
Change
*I
3378887
357576
09/21/2011
PRIT
*J
012 NJY / PRIT Updated Features(Removed250MHzfrequencyrelatedinformation, removed
119-ball BGA package related information).
Updated Selection Guide (Removed 250 MHz frequency related information).
Updated Pin Configurations (Removed 119-ball BGA package related
information).
Updated Scan Register Sizes (Removed 119-ball BGA package related
information).
Removed Boundary Scan Order (Corresponding to 119-ball BGA package).
Updated Operating Range (Removed Industrial Temperature Range).
Updated Electrical Characteristics (Removed 250 MHz frequency related
ation).
Updd Capacitance (Removed 119-ball BGA package related information).
UpdaThermal Resistance (Removed 119-ball BGA package related
infortion).
Updted Switching Characteristics (Removed 250 MHz frequency related
information).
Updateagrams (Removed 119-ball BGA package related
infor
*K
3753130
09/24/201
P
grams (spec 51-85180 (Changed revision from *E to
*L
3981545
4070450
04/25/2013
07/20/2013
PRIT
PRIT
*M
otnot(Note 1, 2, 3, 4, 5, 18).
Confirations:
ote 1 areferred the same e in Figure 1.
Added Note 2and referred the se e in Figure 2.
Updated PiDefinitions:
Added N4 and referred thame note in O, TDI, TMS, TCK pins.
Added Nand referred me note in ZZ pi.
Updated IE149.1 Sel Bary Scan (JTA8]):
Added Note 1nd rered the snote in JTAG e heading.
Updated to new temate.
*N
*O
4151890
4572829
10/09/2013
11/18/2014
PRIT
PRIT
Updated Errata.
Updated Functional Detion:
Added “For a complete lisrelated docuentation, click re.he end.
Updated Package Diagrams:
spec 51-85050 – Changed revision f*D to *E.
*P
5508335
11/03/2016
PRIT
Obsolete document.
Completing Sunset Review.
Document Number: 38-05558 Rev. *P
Page 33 of 34
CY7C1370DV25
CY7C1372DV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Automotive
ypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
ypress.m/go/powerpsoc
ss.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Lighting & P
Community | Forums | Blogs | Video | Training
Technical Support
Memory
go/memory
com/go/psoc
cypress.com/go/support
PSoC
Touch Sensing
USB Controllers
Wireless/RF
ss.com/goch
cypress.cm/go/U
press.cogo/wirele
© Cypress Semiconductor Corporation, 2004-2016. The information contained herein is subject to change without notice. Cypress Smiconductor Corporaasso responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress productnot warror intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, ss does not aits products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The sion of Cypress procts in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license , use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product ed only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code excas specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05558 Rev. *P
Revised November 3, 2016
Page 34 of 34
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this
document may be the trademarks of their respective holders.
相关型号：
CY7C1370DV25-200BZIT
ZBT SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CYPRESS
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