CY7C1372DV25-200AXI [CYPRESS]
18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL⑩ Architecture; 18兆位（ 512K ×36 / 1M ×18 ）流水线式SRAM与NoBL⑩架构
| 型号： | CY7C1372DV25-200AXI |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL⑩ Architecture |
| 文件： | 总30页 (文件大小：422K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
with NoBL™ Architecture
Features
Functional Description
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200, and 167 MHz
The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x
36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1370DV25 and
CY7C1372DV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1370DV25
and CY7C1372DV25 are pin-compatible and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1370DV25 and BWa–BWb for
CY7C1372DV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V power supply
• 2.5V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in lead-free 100 TQFP, 119 BGA, and 165 fBGA
packages
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Logic Block Diagram-CY7C1370DV25 (512K x 36)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
WRITE
DRIVERS
BW
BW
a
a
b
c
d
A
M
P
b
BW
BW
c
S
T
E
R
S
F
d
E
R
S
S
WE
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05558 Rev. *A
Revised November 9, 2004
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Logic Block Diagram-CY7C1372DV25 (1M x 18)
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
A0'
D1
D0
Q1
Q0
A0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
S
T
E
R
S
MEMORY
ARRAY
E
B
DQs
U
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
F
F
E
R
S
DQP
DQP
a
b
b
S
N
G
WE
E
E
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Selection Guide
CY7C1370DV25-250
CY7C1372DV25-250
CY7C1370DV25-200
CY7C1372DV25-200
CY7C1370DV25-167
CY7C1372DV25-167
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.6
350
70
3.0
300
70
3.4
275
70
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05558 Rev. *A
Page 2 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Pin Configurations
100-pin TQFP Packages
DQPc
DQc
1
NC
NC
NC
DDQ
1
A
DQPb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
2
2
NC
79
DQc
3
DQb
3
NC
78
V
V
4
DDQ
4
V
V
DDQ
SS
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
5
V
V
5
SS
V
SS
DQc
6
NC
6
NC
DQb
DQc
7
DQb
NC
7
DQPa
DQa
DQa
DQc
DQc
8
DQb
DQb
DQb
DQb
8
9
9
V
V
SS
DDQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
SS
SS
V
V
DDQ
V
DDQ
DDQ
DQc
DQc
NC
DQb
DQb
DQb
DQa
DQa
DQb
NC
V
V
SS
CY7C1370DV25
(512K × 36)
SS
V
V
DD
NC
DD
NC
CY7C1372DV25
(1M × 18)
NC
NC
V
V
DD
DD
V
V
SS
SS
ZZ
ZZ
DQd
DQd
DQb
DQb
DQa
DQa
DQa
DQa
V
V
V
V
DDQ
DDQ
V
V
DQa
DQa
DDQ
SS
DDQ
SS
V
V
SS
SS
DQd
DQd
DQd
DQd
DQb
DQb
DQa
DQa
NC
DQa DQPb
DQa
NC
NC
V
SS
V
V
V
SS
DDQ
SS
SS
DDQ
V
V
DDQ
DDQ
V
V
DQd
DQa
NC
NC
NC
NC
NC
NC
DQd
DQa
DQPd
DQPa
Document #: 38-05558 Rev. *A
Page 3 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Pin Configurations (continued)
119-ball BGA Pinout
CY7C1370DV25 (512K × 36) – BGA
1
VDDQ
2
A
3
A
4
A
5
A
6
A
7
VDDQ
A
NC
NC
DQc
DQc
VDDQ
DQc
CE2
A
DQPc
A
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
BWd
VSS
VSS
VSS
MODE
A
ADV/LD
VDD
NC
A
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
CE3
A
DQPb
NC
NC
DQb
B
C
D
E
F
G
H
J
K
L
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
CE1
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
OE
A
WE
VDD
CLK
NC
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
NC
VDDQ
M
N
P
CEN
A1
A0
VDD
A
TCK
A
E(72)
TMS
A
E(36)
NC
NC
ZZ
VDDQ
R
NC
A
TDO
T
TDI
U
CY7C1372DV25 (1M x 18) – BGA
1
2
3
4
5
6
7
VDDQ
A
A
A
A
A
VDDQ
A
B
C
D
E
F
G
H
J
NC
NC
DQb
NC
VDDQ
NC
DQb
VDDQ
NC
DQb
VDDQ
DQb
NC
CE2
A
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
A
A
VSS
VSS
VSS
A
A
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
CE3
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
ADV/LD
VDD
NC
VSS
VSS
VSS
NC
VSS
NC
CE1
OE
A
BWb
VSS
NC
VSS
NC
VSS
VSS
VSS
MODE
A
WE
VDD
CLK
NC
VSS
K
L
BWa
VSS
VSS
VSS
NC
A
M
N
P
R
T
CEN
A1
A0
VDD
E(36)
TCK
DQa
NC
ZZ
VDDQ
NC
E(72)
VDDQ
A
TMS
A
NC
TDI
TDO
U
Document #: 38-05558 Rev. *A
Page 4 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Pin Configurations (continued)
165-Ball fBGA Pinout
CY7C1370DV25 (512K × 36) – fBGA
1
2
3
4
5
BWb
6
7
8
9
10
11
NC
E(144)
DQPb
DQb
E(288)
NC
A
ADV/LD
A
A
A
B
C
D
E
F
G
H
J
K
L
CE1
BWc
CE3
CLK
VSS
VSS
CEN
WE
VSS
VSS
A
NC
DQc
CE2
VDDQ
VDDQ
OE
VSS
VDD
A
VDDQ
VDDQ
A
NC
DQb
BWd
VSS
VDD
BWa
VSS
VSS
DQPc
DQc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQb
DQc
DQc
NC
DQd
DQd
DQd
VSS
VSS
VSS
VSS
VSS
VSS
DQb
DQb
ZZ
DQa
DQa
DQa
DQd
DQPd
NC
DQd
NC
E(72)
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
NC
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
DQa
DQPa
NC
M
N
P
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
R
CY7C1372DV25 (1M × 18) – fBGA
1
E(288)
NC
NC
NC
NC
NC
NC
2
3
4
BWb
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
5
6
7
CEN
WE
VSS
VSS
8
9
10
11
A
E(144)
DQPa
DQa
A
NC
CE3
A
A
A
B
C
D
E
F
G
H
J
K
L
CE1
ADV/LD
A
NC
DQb
DQb
DQb
DQb
NC
NC
NC
NC
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
NC
NC
NC
NC
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
DQa
VSS
VSS
VSS
VSS
VSS
VSS
DQa
DQa
ZZ
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQa
DQa
DQa
DQb
DQPb
NC
NC
NC
E(72)
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
NC
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
NC
NC
NC
M
N
P
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05558 Rev. *A
Page 5 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
Input-
Address Inputs used to select one of the address locations. Sampled at the rising edge of
Synchronous
the CLK.
BWa
BWb
BWc
BWd
Input-
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd.
Synchronous
Input-
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
WE
Synchronous
signal must be asserted LOW to initiate a write sequence.
Input-
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
ADV/LD
Synchronous
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1
CE2
Synchronous
CE2 and CE3 to select/deselect the device.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous
CE1 and CE3 to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE3
OE
Synchronous
CE1 and CE2 to select/deselect the device.
Input-
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the first clock when emerging from a
deselected state and when the device has been deselected.
Input-
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
CEN
DQS
Synchronous
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are
automatically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state of
OE.
Synchronous
DQPX
I/O-
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQs. During write
sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
and DQPd is controlled by BWd.
Synchronous
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
TDI
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
VDD
VDDQ
JTAG-Clock
Clock input to the JTAG circuitry.
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Document #: 38-05558 Rev. *A
Page 6 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
VSS
NC
Ground
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
–
–
E(36,72,
These pins are not connected. They will be used for expansion to the 36M, 72M, 144M and
144, 288)
288M densities.
ZZ
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. During normal operation, this pin can be connected to VSS or left
floating.
of the chip enable signals, its output will three-state following
Introduction
Functional Overview
the next clock rise.
Burst Read Accesses
The
CY7C1370DV25
and
CY7C1372DV25
are
The CY7C1370DV25 and CY7C1372DV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
synchronous-pipelined Burst NoBL SRAMs designed specifi-
cally to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 2.6 ns (250-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented is loaded into the
Address Register. The write signals are latched into the
Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b
for CY7C1372DV25). In addition, the address for the subse-
quent access (Read/Write/Deselect) is latched into the
Address Register (provided the appropriate control signals are
asserted).
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(250-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 & DQa,b/DQPa,b for
CY7C1372DV25) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1370DV25 and BWa,b for CY7C1372DV25)
signals. The CY7C1370DV25/CY7C1372DV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Write Enable input (WE) with the selected
Byte Write Select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered.
A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly
Document #: 38-05558 Rev. *A
Page 7 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
simplify Read/Modify/Write sequences, which can be reduced
Sleep Mode
to simple byte write operations.
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Because the CY7C1370DV25 and CY7C1372DV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b
for CY7C1372DV25) inputs. Doing so will three-state the
output drivers. As a safety precaution, DQand DQP (DQa,b,c,d
/
DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b for
CY7C1372DV25) are automatically three-stated during the
data portion of a write cycle, regardless of the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
Burst Write Accesses
First
Second
Third
Fourth
The CY7C1370DV25/CY7C1372DV25 has an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four WRITE operations without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load the initial address, as described in the Single
Write Access section above. When ADV/LD is driven HIGH on
the subsequent clock rise, the chip enables (CE1, CE2, and
CE3) and WE inputs are ignored and the burst counter is incre-
mented. The correct BW (BWa,b,c,d for CY7C1370DV25 and
BWa,b for CY7C1372DV25) inputs must be driven in each
cycle of the burst write in order to write the correct bytes of
data.
Address
Address
Address
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Second
Third
Fourth
Address
Address
Address
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
80
2tCYC
Unit
mA
ns
ns
ns
tZZS
tZZREC
tZZI
tRZZI
2tCYC
0
2tCYC
ns
Document #: 38-05558 Rev. *A
Page 8 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Truth Table[1, 2, 3, 4, 5, 6, 7]
Address
Used
None
None
External
Next
External
Next
External
Next
None
Next
Operation
Deselect Cycle
CE
H
X
L
X
L
X
L
X
L
ZZ
L
L
L
L
L
L
L
L
L
L
L
H
ADV/LD WE BWx
OE
X
X
L
L
H
H
X
X
X
X
X
X
CEN CLK
L-H
DQ
L
H
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
Three-State
Three-State
Data Out (Q)
Data Out (Q)
Three-State
Three-State
Data In (D)
Data In (D)
Three-State
Three-State
–
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/Write Abort (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
H
L
H
L
H
X
X
X
L
X
X
X
L
H
H
X
X
X
X
X
L-H
Current
None
H
X
L-H
X
Sleep Mode
Three-State
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BW = Valid
x
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW . See Write Cycle Description table for details.
X
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ and DQP = Three-state when OE
s
X
is inactive or when the device is deselected, and DQ = data when OE is active.
s
8. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05558 Rev. *A
Page 9 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1370DV25)
BWd
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
BWc
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
BWb
X
H
H
L
BWa
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Read
Write – No bytes written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Bytes b, a
Write Byte c – (DQc and DQPc)
Write Bytes c, a
Write Bytes c, b
Write Bytes c, b, a
Write Byte d – (DQd and DQPd)
Write Bytes d, a
Write Bytes d, b
L
H
H
L
L
H
H
L
Write Bytes d, b, a
Write Bytes d, c
Write Bytes d, c, a
Write Bytes d, c, b
L
H
H
L
Write All Bytes
L
L
Function (CY7C1372DV25)
WE
BWb
BWa
Read
H
L
L
L
L
x
H
H
L
x
H
L
H
L
Write – No Bytes Written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
L
The CY7C1370DV25/CY7C1372DV25 contains
a
TAP
IEEE 1149.1 Serial Boundary Scan (JTAG)
controller, instruction register, boundary scan register, bypass
register, and ID register.
The CY7C1370DV25/CY7C1372DV25 incorporates a serial
boundary scan test access port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
part operates in accordance with IEEE Standard 1149.1-1900,
but doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
Document #: 38-05558 Rev. *A
Page 10 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
TAP Controller State Diagram
TAP Controller Block Diagram
TEST-LOGIC
1
0
RESET
0
Bypass Register
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
2
1
0
0
0
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
Selection
1
1
TDI
TDO
CAPTURE-DR
CAPTURE-IR
Circuitr
y
.
.
.
2
1
0
0
0
SHIFT-DR
0
SHIFT-IR
0
x
.
.
.
.
. 2 1 0
1
1
1
1
Boundary Scan Register
TAP CONTROLLER
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
0
TCK
TMS
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
Performing a TAP Reset
1
0
1
0
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
Test Access Port (TAP)
TAP Registers
Test Clock (TCK)
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see figure. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
Document #: 38-05558 Rev. *A
Page 11 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri-
or to the selection of another boundary scan test operation.
EXTEST
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
IDCODE
Reserved
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05558 Rev. *A
Page 12 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Clock
tTCYC
tTF
tTH
tTL
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
25
25
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
5
ns
ns
0
5
5
5
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Notes:
9. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document #: 38-05558 Rev. *A
Page 13 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
2.5V TAP AC Test Conditions
2.5V TAP AC Output Load Equivalent
1.25V
Input pulse levels ............................................... .VSS to 2.5V
Input rise and fall time..................................................... 1 ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[11]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
Description
Test Conditions
Min.
2.0
2.1
Max.
Unit
V
V
V
V
V
V
µA
Output HIGH Voltage IOH = –1.0 mA, VDDQ = 2.5V
Output HIGH Voltage IOH = –100 µA, VDDQ = 2.5V
Output LOW Voltage IOL = 8.0 mA, VDDQ = 2.5V
Output LOW Voltage IOL = 100 µA
Input HIGH Voltage
0.4
0.2
VDD + 0.3
0.7
VDDQ = 2.5V
VDDQ = 2.5V
VDDQ = 2.5V
1.7
–0.3
–5
VIL
IX
Input LOW Voltage
Input Load Current
GND < VIN < VDDQ
5
Note:
11.All voltages referenced to V (GND).
SS
Document #: 38-05558 Rev. *A
Page 14 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Identification Register Definitions
Instruction Field
CY7C1370DV25
CY7C1372DV25
Description
Revision Number (31:29)
000
000
Reserved for version number.
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
01011001000100101
00000110100
01011001000010101 Reserved for future use.
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence (0)
1
1
Indicate the presence of an ID
register.
Scan Register Sizes
Bit Size (x18)
Register Name
Bit Size (x36)
Instruction
3
3
Bypass
1
1
ID
32
85
89
32
85
89
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
001
010
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
SAMPLE Z
011
100
RESERVED
SAMPLE/PRELOAD
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05558 Rev. *A
Page 15 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
119-ball BGA Boundary Scan[12, 13]
CY7C1370DV25 (1M x 36)
CY7C1370DV25 (1M x 36)
Bit #
1
2
3
4
5
6
7
8
Ball ID
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
B6
D4
B4
F4
Bit #
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
N2
P2
R3
T1
R1
T2
L3
R2
T3
L4
N4
P4
H4
T4
T5
T6
R5
L5
R6
U6
R7
T7
P6
N7
M6
L7
K6
P7
N6
L6
K7
J5
H6
G7
F6
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
M4
A5
K4
E4
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Internal
G1
H2
D1
E2
G2
H1
J3
2K
L1
M2
N1
P1
K1
L2
Notes:
12. Balls which are NC (No Connect) are pre-set LOW
13. Bit# 85 is pre-set HIGH
Document #: 38-05558 Rev. *A
Page 16 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
119-ball BGA Boundary Scan Order[12, 13]
CY7C1372DV25 (2M x 18)
CY7C1372DV25 (2M x 18)
Bit #
1
2
3
4
5
6
7
8
Ball ID
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
B6
D4
B4
F4
Bit #
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
N2
P2
R3
T1
R1
T2
L3
R2
T3
L4
N4
P4
H4
T4
T5
T6
R5
L5
R6
U6
R7
T7
P6
N7
M6
L7
K6
P7
N6
L6
K7
J5
H6
G7
F6
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
M4
A5
K4
E4
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Internal
G1
H2
D1
E2
G2
H1
J3
2K
L1
M2
N1
P1
K1
L2
Document #: 38-05558 Rev. *A
Page 17 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
165-ball fBGA Boundary Scan Order[12, 14]
CY7C1370DV25 (1M x 36)
CY7C1370DV25 (1M x 36)
Bit #
1
2
3
4
5
6
7
8
Ball ID
N6
N7
10N
P11
P8
R8
R9
P9
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
A9
B9
C10
A8
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H3
J1
K1
L1
M1
J2
Bit #
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
K2
L2
M2
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
Internal
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Note:
14. Bit# 89 is Pre-Set HIGH
Document #: 38-05558 Rev. *A
Page 18 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
165-ball fBGA Boundary Scan Order[12, 14]
CY7C1372DV25 (2M x 18)
CY7C1372DV25 (2M x 18)
Bit #
1
2
3
4
5
6
7
8
Ball ID
N6
N7
10N
P11
P8
R8
R9
P9
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
A9
B9
C10
A8
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H3
J1
K1
L1
M1
J2
Bit #
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
K2
L2
M2
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
Internal
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Document #: 38-05558 Rev. *A
Page 19 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Operating Range
Power Applied.............................................–55°C to +125°C
Ambient
VDD/VDDQ
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
DC to Outputs in Tri-State................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
2.5V +_ 5%
Electrical Characteristics Over the Operating Range[15, 16]
Parameter
VDD
Description
Test Conditions
Min.
2.375
2.375
2.0
Max.
2.625
VDD
Unit
V
V
V
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
VDDQ
VOH
VOL
VIH
VIL
VDD = Min., IOH = −1.0 mA
VDD = Min., IOL= 1.0 mA
0.4
VDD + 0.3V
Input HIGH Voltage[17] VDDQ = 2.5V
1.7
–0.3
–5
V
V
Input LOW Voltage[17] VDDQ = 2.5V
0.7
5
IX
Input Load
Input Current of MODE Input = VSS
Input = VDD
GND ≤ VI ≤ VDDQ
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
–5
30
Input Current of ZZ
Input = VSS
Input = VDD
–30
–5
5
5
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
350
300
275
160
150
140
70
f = fMAX = 1/tCYC
ISB1
Automatic CE
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
Power-down
V
IN ≥ VIH or VIN ≤ VIL, f = fMAX
=
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
Current—TTL Inputs
1/tCYC
ISB2
Automatic CE
Power-down
Max. VDD, Device Deselected, All speed grades
V
IN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = 0
ISB3
Automatic CE
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
135
130
125
80
mA
mA
mA
mA
Power-down
V
IN ≤ 0.3V or VIN > VDDQ − 0.3V,
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
ISB4
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Shaded areas contain advance information.
Notes:
15. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
.
16. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
Power-up
DD
IH
DD
DDQ DD
17. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05558 Rev. *A
Page 20 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Capacitance[17]
TQFP
BGA
fBGA
Parameter
CIN
CCLK
CI/O
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
Package
Package
Package
Unit
pF
pF
TA = 25°C, f = 1 MHz,
5
5
5
8
8
8
9
9
9
V
DD = 2.5V.
DDQ = 2.5V
V
pF
Thermal Resistance[17]
TQFP
BGA
fBGA
Parameter
Description
Test Conditions
Package
Package
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard
test methods and procedures
for measuring thermal
31
45
46
°C/W
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
6
7
3
°C/W
impedance, per EIA / JESD51.
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document #: 38-05558 Rev. *A
Page 21 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
[22, 23]
Switching Characteristics Over the Operating Range
-250
-200
-167
Parameter
tPower
Clock
tCYC
FMAX
tCH
Description
VCC (typical) to the first access read or write
Min. Max. Min.
Max. Min. Max.
Unit
ms
[18]
1
1
5
1
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
4.0
6
ns
MHz
ns
250
200
167
1.7
1.7
2.0
2.0
2.2
2.2
tCL
Clock LOW
ns
Output Times
tCO
tEOV
tDOH
tCHZ
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High-Z[19, 20, 21]
Clock to Low-Z[19, 20, 21]
OE HIGH to Output High-Z[19, 20, 21]
OE LOW to Output Low-Z[19, 20, 21]
2.6
2.6
3.0
3.0
3.4
3.4
ns
ns
ns
ns
ns
ns
ns
1.0
1.0
0
1.3
1.3
0
1.3
1.3
0
2.6
2.6
3.0
3.0
3.4
3.4
tCLZ
tEOHZ
tEOLZ
Set-up Times
tAS
tDS
tCENS
tWES
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
CEN Set-up Before CLK Rise
WE, BWx Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tALS
tCES
Hold Times
tAH
tDH
tCENH
tWEH
tALH
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
WE, BWx Hold After CLK Rise
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tCEH
Shaded areas contain advance information.
Notes:
18. This part has a voltage regulator internally; t
be initiated.
is the time power needs to be supplied above V minimum initially, before a Read or Write operation can
DD
Power
19. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
EOHZ
CHZ CLZ EOLZ
20. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
EOHZ
EOLZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
22. Timing reference 1.25V when V
= 2.5V.
DDQ
23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05558 Rev. *A
Page 22 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Switching Waveforms
Read/Write/Timing[24, 25, 26]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
x
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
24. For this waveform ZZ is tied LOW.
25. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05558 Rev. *A
Page 23 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Switching Waveforms (continued)
NOP,STALL and DESELECT Cycles[24, 25, 27]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
ZZ Mode Timing[28, 29]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
27. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
29. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05558 Rev. *A
Page 24 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Ordering Information
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
Package Type
250 CY7C1370DV25-250AXC
CY7C1372DV25-250AXC
CY7C1370DV25-250BGC
CY7C1372DV25-250BGC
CY7C1370DV25-250BZC
CY7C1372DV25-250BZC
CY7C1370DV25-250BGXC
CY7C1372DV25-250BGXC
CY7C1370DV25-250BZXC
CY7C1372DV25-250BZXC
200 CY7C1370DV25-200AXC
CY7C1372DV25-200AXC
CY7C1370DV25-200BGC
CY7C1372DV25-200BGC
CY7C1370DV25-200BZC
CY7C1372DV25-200BZC
CY7C1370DV25-200BGXC
CY7C1372DV25-200BGXC
CY7C1370DV25-200BZXC
CY7C1372DV25-200BZXC
167 CY7C1370DV25-167AXC
CY7C1372DV25-167AXC
CY7C1370DV25-167BGC
CY7C1372DV25-167BGC
CY7C1370DV25-167BZC
CY7C1372DV25-167BZC
CY7C1370DV25-167BGXC
CY7C1372DV25-167BGXC
CY7C1370DV25-167BZXC
CY7C1372DV25-167BZXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4
mm)
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4
mm)
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4
mm)
Document #: 38-05558 Rev. *A
Page 25 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Ordering Information (continued)
Speed
Package
Operating
Range
Industrial
(MHz)
Ordering Code
Name
Package Type
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
250 CY7C1370DV25-250AXI
CY7C1372DV25-250AXI
CY7C1370DV25-250BGI
CY7C1372DV25-250BGI
CY7C1370DV25-250BZI
CY7C1372DV25-250BZI
CY7C1370DV25-250BGXI
CY7C1372DV25-250BGXI
CY7C1370DV25-250BZXI
CY7C1372DV25-250BZXI
200 CY7C1370DV25-200AXI
CY7C1372DV25-200AXI
CY7C1370DV25-200BGI
CY7C1372DV25-200BGI
CY7C1370DV25-200BZI
CY7C1372DV25-200BZI
CY7C1370DV25-200BGXI
CY7C1372DV25-200BGXI
CY7C1370DV25-200BZXI
CY7C1372DV25-200BZXI
167 CY7C1370DV25-167AXI
CY7C1372DV25-167AXI
CY7C1370DV25-167BGI
CY7C1372DV25-167BGI
CY7C1370DV25-167BZI
CY7C1372DV25-167BZI
CY7C1370DV25-167BGXI
CY7C1372DV25-167BGXI
CY7C1370DV25-167BZXI
CY7C1372DV25-167BZXI
A101
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4
mm)
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4
mm)
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4
mm)
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Lead-free BG packages(Ordering Code: BGX) will be available in 2005.
Document #: 38-05558 Rev. *A
Page 26 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
(ꢀX)
SEE DETAIL
A
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
51-85050-*A
0°-7°
0.60 0.ꢁ5
0.20 MIN.
ꢁ.00 REF.
DETAIL
A
Document #: 38-05558 Rev. *A
Page 27 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05558 Rev. *A
Page 28 of 30
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 MM BB165D
51-85180-**
Document #: 38-05558 Rev. *A
Page 29 of 30
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Document History Page
DocumentTitle:CY7C1370DV25/CY7C1372DV2518-Mbit(512Kx36/1Mx18)PipelinedSRAMwithNoBL™Architecture
(Preliminary)
Document Number: 38-05558
Orig. of
REV.
**
ECN No. Issue Date Change
Description of Change
254509
See ECN
RKF
New data sheet
*A
288531
See ECN
SYT
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 225 Mhz Speed Bin
Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA
package
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
Document #: 38-05558 Rev. *A
Page 30 of 30
相关型号：
CY7C1372DV25-200BGXIT
ZBT SRAM, 1MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
CYPRESS
CY7C1372DV25-200BZCT
ZBT SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CYPRESS
CY7C1372DV25-250AI
ZBT SRAM, 1MX18, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
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