CY7C1373KV33-133AXI [CYPRESS]
18-Mbit (512K à 36/1M à 18) Flow-Through SRAM with NoBL⢠Architecture (With ECC);
| 型号： | CY7C1373KV33-133AXI |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit (512K à 36/1M à 18) Flow-Through SRAM with NoBL⢠Architecture (With ECC) 静态存储器 内存集成电路 |
| 文件： | 总24页 (文件大小：682K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
18-Mbit (512K × 36/1M × 18)
Flow-Through SRAM
with NoBL™ Architecture (With ECC)
18-Mbit (512K
× 36/1M × 18) Flow-through SRAM with NoBL™ Architecture (With ECC)
Features
Functional Description
■ No Bus Latency (NoBL) architecture eliminates dead cycles
The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 are
3.3 V, 512K × 36/1M × 18 synchronous flow through burst SRAM
designed specifically to support unlimited true back-to-back
read/write operations with no wait state insertion. The
between write and read cycles
■ Supports up to 133 MHz bus operations with zero wait states
❐ Data is transferred on every clock
CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33
are
equipped with the advanced No Bus Latency (NoBL) logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
■ Pin-compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte write capability
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
■ 3.3 V/2.5 V I/O power supply (VDDQ
)
■ Fast clock-to-output times
❐ 6.5 ns (for 133 MHz device)
Write operations are controlled by the two or four byte write
select (BWX) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Clock enable (CEN) pin to enable clock and suspend operation
■ Synchronous self-timed writes
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
■ Asynchronous output enable
■ Available in JEDEC-standard Pb-free 100-pin TQFP packages
■ Three chip enables for simple depth expansion
■ Automatic power-down feature available using ZZ mode or CE
deselect
■ Burst capability – linear or interleaved burst order
■ Low standby power
■ On chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
Selection Guide
Description
Maximum access time
133 MHz
6.5
100 MHz Unit
8.5
114
134
ns
Maximum operating current
× 18
× 36
129
mA
mA
149
Cypress Semiconductor Corporation
Document Number: 001-97852 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 8, 2018
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Logic Block Diagram – CY7C1371KV33
ADDRESS
REGISTER
A0, A1,
A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
MODE
BURST
LOGIC
CE
ADV/LD
CLK
CEN
C
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
E
ADV/LD
A
B
U
F
F
E
R
S
MEMORY
ARRAY
BW
BW
BW
BW
A
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
B
A
B
A
M
P
C
C
D
D
S
WE
E
N
G
INPUT
REGISTER
E
OE
CE1
CE2
CE3
READ LOGIC
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1371KVE33
ADDRESS
REGISTER
A0, A1, A
MODE
A1
A0
A1'
Q0 A0'
D1
D0
Q1
BURST LOGIC
/CE
C
CLK
ADV or /LD
C
/CEN
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
E
A
DQS
DQPA
DQPB
DQPC
DQPD
ECC
DECODER
S
T
E
E
R
I
ADV or /LD
/BWA
WRITE
DRIVERS
MEMORY
ARRAY
B
U
F
A
M
P
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
/BWB
F
/BWC
/BWD
/WE
E
R
S
N
G
S
E
ECC
ENCODER
INPUT
REGISTER
E
READ
LOGIC
/OE
/CE1
CE2
/CE1
SLEEP
CONTROL
ZZ
Document Number: 001-97852 Rev. *F
Page 2 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Logic Block Diagram – CY7C1373KV33
ADDRESS
REGISTER
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
MODE
C
BURST
LOGIC
CE
ADV/LD
CLK
CEN
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
E
ADV/LD
A
B
U
F
F
E
R
S
MEMORY
ARRAY
BW
BW
A
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
B
A
B
A
M
P
S
WE
E
N
G
INPUT
REGISTER
E
OE
CE1
CE2
CE3
READ LOGIC
SLEEP
ZZ
CONTROL
Document Number: 001-97852 Rev. *F
Page 3 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Contents
Pin Configurations ...........................................................5
Pin Definitions ..................................................................7
Functional Overview ........................................................9
Single Read Accesses ................................................9
Burst Read Accesses ..................................................9
Single Write Accesses .................................................9
Burst Write Accesses ..................................................9
Sleep Mode ...............................................................10
Interleaved Burst Address Table ...............................10
Linear Burst Address Table .......................................10
ZZ Mode Electrical Characteristics ............................10
Truth Table ......................................................................11
Partial Truth Table for Read/Write ................................12
Partial Truth Table for Read/Write ................................12
Maximum Ratings ...........................................................13
Operating Range .............................................................13
Neutron Soft Error Immunity .........................................13
Electrical Characteristics ...............................................13
Capacitance ....................................................................15
Thermal Resistance ........................................................15
AC Test Loads and Waveforms .....................................15
Switching Characteristics ..............................................16
Switching Waveforms ....................................................17
Ordering Information ......................................................20
Ordering Code Definitions .........................................20
Package Diagrams ..........................................................21
Acronyms ........................................................................22
Document Conventions .................................................22
Units of Measure .......................................................22
Document History Page .................................................23
Sales, Solutions, and Legal Information ......................24
Worldwide Sales and Design Support .......................24
Products ....................................................................24
PSoC® Solutions ......................................................24
Cypress Developer Community .................................24
Technical Support .....................................................24
Document Number: 001-97852 Rev. *F
Page 4 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
CY7C1371KV33/CY7C1371KVE33
DQPC
DQC
DQC
VDDQ
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
DQPB
DQB
DQB
VDDQ
VSS
2
3
4
5
DQC
6
DQB
BYTE C
BYTE B
DQB
DQC
DQC
DQC
VSS
7
8
DQB
DQB
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQC
DQC
NC
VDDQ
DQB
DQB
VSS
VDD
NC
NC
VDD
ZZ
VSS
DQD
DQD
VDDQ
VSS
DQA
DQA
VDDQ
VSS
DQD
DQA
DQD
DQA
BYTE D
BYTE A
DQA
DQD
DQD
VSS
DQA
VSS
VDDQ
DQD
DQD
DQPD
VDDQ
DQA
DQA
DQPA
Document Number: 001-97852 Rev. *F
Page 5 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Pin Configurations (continued)
Figure 2. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
CY7C1373KV33
NC
1
NC
2
NC
3
VDDQ
4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
VSS
NC
5
6
NC
7
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
BYTE A
NC
VDD
NC
BYTE B
VDD
ZZ
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
VSS
VDDQ
NC
NC
NC
NC
NC
Document Number: 001-97852 Rev. *F
Page 6 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Pin Definitions
Name
I/O
Description
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
A0, A1, A
Input-
synchronous A[1:0] are fed to the two-bit burst counter.
Input-
Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
BWA, BWB,
BWC, BWD
synchronous edge of CLK.
WE
Input-
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
Input-
Advance/load input. Used to advance the on-chip address counter or load a new address. When HIGH
ADV/LD
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a
new address.
CLK
Input-clock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
Input-
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
CE1
CE2
synchronous and CE3 to select/deselect the device.
Input-
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
Input-
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
CE3
OE
synchronous and CE2 to select/deselect the device.
Input-
Output enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
Input-
Clock enable input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
CEN
ZZ
synchronous When deasserted HIGH the Clock signal is masked. While deasserting CEN does not deselect the
device, use CEN to extend the previous cycle when required.
Input-
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Document Number: 001-97852 Rev. *F
Page 7 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Pin Definitions (continued)
Name
DQs
I/O
Description
I/O-
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and
DQP[A:D] are placed in a tristate condition.The outputs are automatically tristated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the device
is deselected, regardless of the state of OE.
I/O-
synchronous
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs.
DQPX
MODE
Input strap pin Mode input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved
burst sequence.
VDD
Power supply Power supply inputs to the core of the device.
VDDQ
I/O power Power supply for the I/O circuitry.
supply
VSS
NC
Ground
–
Ground for the device.
No connects. Not internally connected to the die. NC/(36M, 72M, 144M, 288M, 576M, 1G) are address
expansion pins and are not internally connected to the die.
Document Number: 001-97852 Rev. *F
Page 8 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Read Accesses section above. The sequence of the burst
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and A1
in the burst sequence, and wraps around when incremented
sufficiently. A HIGH input on ADV/LD increments the internal
burst counter regardless of the state of chip enable inputs or WE.
WE is latched at the beginning of a burst cycle. Therefore, the
type of access (read or write) is maintained throughout the burst
sequence.
Functional Overview
The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 is a
synchronous flow through burst SRAM designed specifically to
eliminate wait states during write-read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133 MHz
device).
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tristated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and DQPX.
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BWX can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
On the next clock rise the data presented to DQs and DQPX (or
a subset for byte write operations, see truth table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device has been deselected to
load a new address for the next operation.
The data written during the write operation is controlled by BWX
signals. The CY7C1371KV33/CY7C1371KVE33/
CY7C1373KV33 provides byte write capability that is described
in the truth table. Asserting the write enable input (WE) with the
selected byte write select input selectively writes to only the
desired bytes. Bytes not selected during a byte write operation
remains unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write
operations.
Single Read Accesses
A read access is initiated when these conditions are satisfied at
clock rise:
■ CEN is asserted LOW
■ CE1, CE2, and CE3 are all asserted active
■ The write enable input signal WE is deasserted HIGH
■ ADV/LD is asserted LOW.
Because the CY7C1371KV33/CY7C1371KVE33/
The address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output is tristated immediately.
CY7C1373KV33 is a common I/O device, data must not be
driven into the device while the outputs are active. The output
enable (OE) can be deasserted HIGH before presenting data to
the DQs and DQPX inputs. Doing so tristates the output drivers.
As a safety precaution, DQs and DQPX are automatically
tristated during the data portion of a write cycle, regardless of the
state of OE.
Burst Write Accesses
The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 has
an on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in the Single Write
Accesses section above. When ADV/LD is driven HIGH on the
subsequent clock rise, the chip enables (CE1, CE2, and CE3)
and WE inputs are ignored and the burst counter is incremented.
The correct BWX inputs must be driven in each cycle of the burst
write, to write the correct bytes of data.
Burst Read Accesses
The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 has
an on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four reads without
reasserting the address inputs. ADV/LD must be driven LOW to
load a new address into the SRAM, as described in the Single
Document Number: 001-97852 Rev. *F
Page 9 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
65
Unit
mA
ns
ZZ > VDD– 0.2 V
–
tZZS
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
2tCYC
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ Inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 001-97852 Rev. *F
Page 10 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Truth Table
The truth table for CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 are as follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Deselect cycle
Address Used CE1 CE2
ZZ ADV/LD WE BWX OE CEN CLK
DQ
CE3
X
H
X
X
L
None
None
H
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L->H
L->H
L->H
L->H
Tristate
Tristate
Tristate
Tristate
Deselect cycle
Deselect cycle
None
L
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
NOP/write abort (begin burst)
Write abort (continue burst)
Ignore clock edge (stall)
Sleep mode
None
X
H
X
H
X
H
X
H
X
X
X
H
L
External
Next
L->H Data out (Q)
L->H Data out (Q)
X
L
X
L
H
L
L
External
Next
H
H
X
X
X
X
X
X
L->H
L->H
Tristate
Tristate
X
L
X
L
H
L
External
Next
L->H Data in (D)
L->H Data in (D)
X
L
X
L
H
L
X
L
L
None
H
H
X
X
L->H
L->H
L->H
X
Tristate
Tristate
–
Next
X
X
X
X
X
X
H
X
X
X
X
X
Current
None
Tristate
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW = 0 signifies at least one byte write select is active, BW = valid signifies that the desired byte write selects
X
X
are asserted, see truth table for details.
2. Write is defined by BW , and WE. See Truth Table for read/write.
X
3. When a write cycle is detected, all I/Os are tristated, even during byte writes.
4. The DQs and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
X
5. CEN = H, inserts wait states.
6. Device powers up deselected and the I/Os in a tristate condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = tristate when OE is inactive
X
or when the device is deselected, and DQs and DQP = data when OE is active.
X
Document Number: 001-97852 Rev. *F
Page 11 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1371KV33/CY7C1371KVE33 follows. [8, 9, 10]
Function (CY7C1371KV33/CY7C1371KVE33)
WE
H
L
BWA
X
BWB
X
BWC
X
BWD
X
Read
Write no bytes written
H
H
H
H
Write byte A – (DQA and DQPA)
Write byte B – (DQB and DQPB)
Write byte C – (DQC and DQPC)
Write byte D – (DQD and DQPD)
Write all Bytes
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1373KV33 follows. [8, 9, 10]
Function (CY7C1373KV33)
WE
H
L
BWA
X
BWB
Read
X
H
H
L
Write - no bytes written
H
Write byte A – (DQA and DQPA)
Write byte B – (DQB and DQPB)
Write all bytes
L
L
L
H
L
L
L
Notes
8. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW = 0 signifies at least one byte write select is active, BW = valid signifies that the desired byte write selects
X
X
are asserted, see Truth Table on page 11 for details.
9. Write is defined by BW , and WE. See Truth Table on page 11 for read/write.
X
10. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write is based on which byte write is active.
X
Document Number: 001-97852 Rev. *F
Page 12 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Maximum Ratings
Operating Range
Ambient
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Range
VDD
VDDQ
Temperature
0 °C to +70 °C
–40 °C to +85 °C
Commercial
Industrial
3.3 V– 5% / 2.5 V – 5% to
Storage temperature ................................ –65 °C to +150 °C
+ 10%
VDD
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
Neutron Soft Error Immunity
Test
Parameter Description
Conditions
Typ Max* Unit
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
LSBU
Logical
Single-Bit
Upsets
25 °C
<5
5
FIT/
Mb
DC input voltage .................................–0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
(Device
without
ECC)
Static discharge voltage
(MIL-STD-883, method 3015) .................................> 2001 V
LSBU
(Device with
ECC)
0
0
0
0.01 FIT/
Mb
Latch up current .....................................................> 200 mA
LMBU
SEL
Logical
Multi-Bit
Upsets
25 °C
85 °C
0.01 FIT/
Mb
Single Event
Latch up
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [11, 12]
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
3.6
Unit
V
VDD
VDDQ
for 3.3 V I/O
for 2.5 V I/O
VDD
2.625
–
V
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage [11]
Input LOW Voltage [11]
for 3.3 V I/O, IOH = –4.0 mA
for 2.5 V I/O, IOH = –1.0 mA
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 3.3 V I/O
V
2.0
–
V
–
0.4
V
–
0.4
V
2.0
VDD + 0.3
V
for 2.5 V I/O
1.7
V
DD + 0.3
V
for 3.3 V I/O
–0.3
–0.3
–5
0.8
0.7
5
V
for 2.5 V I/O
V
Input Leakage Current except ZZ GND VI VDDQ
and MODE
A
Input Current of MODE
Input = VSS
Input = VDD
Input = VSS
Input = VDD
–30
–
–
5
A
A
A
A
Input Current of ZZ
–5
–
–
30
Notes
11. Overshoot: V
< V + 1.5 V (Pulse width less than t
/2), undershoot: V
> –2 V (Pulse width less than t
/2).
IH(AC)
DD
CYC
IL(AC)
CYC
12. T
: Assumes a linear ramp from 0 V to V
of at least 200 ms. During this time V < V and V
<V
.
Power-up
DD(min.)
IH
DD
DDQ
DD
Document Number: 001-97852 Rev. *F
Page 13 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [11, 12]
Description
Output Leakage Current
VDD Operating Supply
Test Conditions
Min
–5
–
Max
5
Unit
A
IOZ
IDD
GND VI VDDQ, Output Disabled
VDD = Max.,
100 MHz
133 MHz
100 MHz
133 MHz
× 18
× 36
× 18
× 36
× 18
× 36
× 18
× 36
× 18
× 36
114
134
129
149
75
mA
IOUT = 0 mA,
f = fMAX = 1/tCYC
–
–
–
ISB1
Automatic CE Power-down
Current – TTL Inputs
Max. VDD
,
–
mA
Device Deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
–
80
–
75
–
80
ISB2
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD
,
All speed
grades
–
65
mA
mA
Device Deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f = 0
–
70
ISB3
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD
,
100 MHz
133 MHz
× 18
× 36
× 18
× 36
× 18
× 36
–
–
–
–
–
–
75
80
75
80
65
70
Device Deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f = fMAX = 1/tCYC
ISB4
Automatic CE Power-down
Current – TTL Inputs
Max. VDD
,
All speed
grades
mA
Device Deselected,
VIN VIH or VIN VIL,
f = 0
Document Number: 001-97852 Rev. *F
Page 14 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Capacitance
100-pin TQFP
Unit
Parameter
Description
Input capacitance
Test Conditions
Package
CIN
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
5
5
5
pF
pF
pF
CCLK
CIO
Clock input capacitance
Input/output capacitance
Thermal Resistance
100-pin TQFP
Package
Parameter
JA
Description
Test Conditions
Unit
Thermal resistance
(junction to ambient)
Test conditions follow standard test With Still Air (0 m/s)
37.95
33.19
30.44
24.07
C/W
C/W
C/W
C/W
methods and procedures for
measuring thermal impedance, per
With Air Flow (1 m/s)
EIA/JESD51.
With Air Flow (3 m/s)
--
JB
JC
Thermal resistance
(junction to board)
Thermal resistance
(junction to case)
8.36
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
VDDQ
90%
10%
Z = 50
90%
10%
0
L
GND
5 pF
R = 351
1ns
1ns
V = 1.5 V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
2.5 V I/O Test Load
(b)
R = 1667
2.5 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
10%
L
GND
5 pF
R = 1538
1ns
1ns
V = 1.25 V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document Number: 001-97852 Rev. *F
Page 15 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Switching Characteristics
Over the Operating Range
133 MHz
Max
100 MHz
Unit
Parameter [13, 14]
Description
Min
Min
Max
tPOWER
Clock
tCYC
VDD(typical) to the first access [15]
1
–
1
–
ms
Clock cycle time
Clock HIGH
7.5
2.1
2.1
–
–
–
10
2.5
2.5
–
–
–
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z [16, 17, 18]
–
2.0
2.0
–
6.5
–
–
2.0
2.0
–
8.5
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
–
tCHZ
Clock to high Z [16, 17, 18]
4.0
3.2
–
5.0
3.8
–
tOEV
OE LOW to output valid
–
–
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to output low Z [16, 17, 18]
OE HIGH to output high Z [16, 17, 18]
0
0
–
4.0
–
5.0
Address setup before CLK rise
ADV/LD setup before CLK rise
WE, BWX setup before CLK rise
CEN setup before CLK rise
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tALS
tWES
tCENS
tDS
Data input setup before CLK rise
Chip enable setup before CLK rise
tCES
Hold Times
tAH
Address hold after CLK rise
ADV/LD hold after CLK rise
WE, BWX hold after CLK rise
CEN hold after CLK rise
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tALH
tWEH
tCENH
tDH
Data input hold after CLK rise
Chip enable hold after CLK rise
tCEH
Notes
13. Timing reference level is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
14. Test conditions shown in (a) of Figure 3 on page 15 unless otherwise noted.
15. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V
initially, before a read or write operation can
POWER
DD(minimum)
be initiated.
16. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of Figure 3 on page 15. Transition is measured ±200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
17. At any voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data bus.
CLZ
OEHZ
OELZ
CHZ
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z
prior to low Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document Number: 001-97852 Rev. *F
Page 16 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Switching Waveforms
Figure 4. Read/Write Waveforms [19, 20, 21]
t
1
2
3
4
5
6
7
8
9
10
CYC
t
CLK
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CEN
CE
ADV/LD
W E
BW
X
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COM M AND
W RITE
D(A1)
W RITE
D(A2)
BURST
W RITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
W RITE
D(A5)
READ
Q(A6)
W RITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes
For this waveform ZZ is tied LOW.
19.
20. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
21. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 001-97852 Rev. *F
Page 17 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Switching Waveforms (continued)
Figure 5. NOP, STALL AND DESELECT Cycles [22, 23, 24]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A1
A2
A3
A4
A5
t
CHZ
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
DQ
t
DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
Notes
For this waveform ZZ is tied LOW.
22.
23. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
24. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 001-97852 Rev. *F
Page 18 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [25, 26]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
25. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
26. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-97852 Rev. *F
Page 19 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a
worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit
us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
133 CY7C1371KV33-133AXC
CY7C1373KV33-133AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
Industrial
CY7C1371KVE33-133AXI
100 CY7C1371KV33-100AXC
CY7C1373KV33-100AXC
CY7C1371KV33-100AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
Industrial
CY7C1371KVE33-100AXI
Ordering Code Definitions
-
XXX XX
X X
33
CY
7
C
13XX
KV
E
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C
X = Pb-free; X Absent = Leaded
Package Type: XX = A
A = 100-pin TQFP
Speed Grade: XXX = 100 or 133 MHz
33 = 3.3 V VDD
E = Device with ECC; blank = Device without ECC
Process Technology: K =65 nm
Part Identifier: 13XX = 1371 or 1373
1371 = FT, 512Kb × 36 (18Mb)
1373 = FT, 1Mb × 18 (18Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-97852 Rev. *F
Page 20 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș 2
ș
1
ș
DIMENSIONS
MIN. NOM. MAX.
1.60
NOTE:
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
MOLD PROTRUSION/END FLASH SHALL
A
0.05
0.15
A1
A2
D
1.35 1.40 1.45
15.80 16.00 16.20
13.90 14.00 14.10
21.80 22.00 22.20
19.90 20.00 20.10
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
D1
E
E1
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
0.08
0.08
0°
R
R
ș
0.20
0.20
7°
1
2
ș 1
ș 2
c
0°
11° 12° 13°
0.20
0.22 0.30 0.38
0.45 0.60 0.75
1.00 REF
b
L
L1
L 2
L 3
e
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 001-97852 Rev. *F
Page 21 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CMOS
CE
Complementary Metal Oxide Semiconductor
Chip Enable
Symbol
°C
Unit of Measure
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
millivolt
MHz
µA
mA
mm
ms
mV
nm
ns
CEN
EIA
Clock Enable
Electronic Industries Alliance
Input/Output
I/O
JEDEC
JTAG
LSB
Joint Electron Devices Engineering Council
Joint Test Action Group
Least Significant Bit
Most Significant Bit
No Bus Latency
nanometer
nanosecond
ohm
MSB
NoBL
OE
Output Enable
%
percent
SRAM
TAP
Static Random Access Memory
Test Access Port
pF
V
picofarad
volt
TCK
TDI
Test Clock
W
watt
Test Data Input
TMS
TDO
TQFP
TTL
Test Mode Select
Test Data Output
Thin Quad Flat Pack
Transistor-Transistor Logic
Write Enable
WE
Document Number: 001-97852 Rev. *F
Page 22 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Document History Page
Document Title: CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33, 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with
NoBL™ Architecture (With ECC)
Document Number: 001-97852
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*C
*D
*E
4983482
5085569
5333298
DEVM
DEVM
PRIT
10/23/2015 Changed status from Preliminary to Final.
01/14/2016 Post to external web.
07/01/2016 Updated Neutron Soft Error Immunity:
Updated values in “Typ” and “Max” columns corresponding to LSBU (Device
without ECC) parameter.
Updated to new template.
*F
6063409
CNX
02/08/2018 Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
Document Number: 001-97852 Rev. *F
Page 23 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Memory
cypress.com/support
cypress.com/memory
cypress.com/mcu
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-97852 Rev. *F
Revised February 8, 2018
Page 24 of 24
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明