CY7C1379C-100BZXC_技术文档

CY7C1379C

9-Mbit (256K x 32) Flow-through SRAM

with NoBL™ Architecture

Functional Description^[1]

Features

• Can support up to 133-MHz bus operations with zero

wait states

The CY7C1379C is a 3.3V, 256K x 32 Synchronous

Flow-through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1379C is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to

enable consecutive Read/Write operations with data being

transferred on every clock cycle. This feature dramatically

improves the throughput of data through the SRAM, especially

in systems that require frequent Write-Read transitions.

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use

OE

• Registered inputs for flow-through operation

• Byte Write capability

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

• 256K x 32 common I/O architecture

• Single 3.3V power supply (V_DD

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

)

Write operations are controlled by the two Byte Write Select

(BW_[A:D]) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

• Asynchronous Output Enable

• Available in JEDEC-standard lead-free 100-Pin TQFP,

lead-free and non lead-free 165-Ball FBGA package

• Burst Capability—linear or interleaved burst order

• Low standby power

Logic Block Diagram–CY7C1379C (256K x 36)

ADDRESS

A0, A1, A

A1

A1'

Q1

REGISTER

D1

A0

A0'

Q0

D0

MODE

BURST

LOGIC

CE

ADV/LD

C

CLK

CEN

C

WRITE ADDRESS

REGISTER

O

U

T

P

U

T

D

A

T

S

E

N

S

ADV/LD

A

B

U

F

MEMORY

ARRAY

BWA

BWB

BWC

BWD

WRITE

DRIVERS

E

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

S

T

E

R

I

DQs

A

M

P

F

E

R

S

WE

E

N

G

INPUT

REGISTER

E

OE

READ LOGIC

CE1

CE2

CE3

SLEEP

Control

ZZ

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05688 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

CY7C1379C

Selection Guide

133 MHz

6.5

100 MHz

7.5

Unit

ns

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

250

180

mA

40

Pin Configurations

100-Pin TQFP Pinout

NC

1

DQ_C

2

DQ_C

3

V_DDQ

4

V_SS

5

DQ_C

6

DQ_C

7

DQ_C

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

DQ_B

V_DDQ

V_SS

DQ_B

V_SS

BYTE B

BYTE C

DQ_C

V_SS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V_DDQ

DQ_C

V_SS/DNU

V_DD

V_DDQ

DQ_B

V_SS

CY7C1379C

NC

V_DD

ZZ

V_SS

DQ_D

V_DDQ

V_SS

DQ_A

V_DDQ

V_SS

DQ_D

V_SS

DQ_A

V_SS

BYTE A

BYTE D

V_DDQ

DQ_D

NC

V_DDQ

DQ_A

NC

Document #: 38-05688 Rev. *D

Page 2 of 15

CY7C1379C

Pin Configurations (continued)

165-Ball FBGA Pinout

CY7C1379C (256K x 32)

1

NC/576M

NC/1G

NC

2

A

3

CE₁

4

BW_C

5

BW_B

6

CE₃

7

8

9

A

10

A

11

NC

CEN

WE

V_SS

ADV/LD

A

B

C

D

A

CE2

V_DDQ

BW_D

V_SS

BW_A

V_SS

CLK

V_SS

OE

V_SS

V_DD

NC/18M

V_DDQ

A

NC

DQ_C

NC

DQ_C

V_DD

V_DDQ

DQ_B

DQ_C

V_DD

V_DDQ

NC

V_DD

V_SS

V_DD

V_DDQ

NC

DQ_B

NC

DQ_B

E

F

DQ_C

NC

V_SS

DQ_B

ZZ

G

H

J

DQ_D

V_DDQ

DQ_A

K

L

DQ_D

NC

DQ_D

NC

V_DDQ

A

V_DD

V_SS

A

V_SS

NC

V_SS

NC

A1

V_SS

NC

V_DD

V_SS

A

V_DDQ

A

DQ_A

NC

A

DQ_A

NC

M

N

P

NC/144M NC/72M

NC/288M

A0

MODE

NC/36M

A

NC

A

R

Pin Definitions

Name

TQFP

FBGA

I/O

Input-

Description

Address Inputs used to select one of the 256K address

A₀, A₁, A

37,36,32,33,34,3

5,44,45,46,

R6,P6,A2,

A9,A10,B2

Synchronous locations. Sampled at the rising edge of the CLK. A_[1:0]are fed

47,48,49,50,81,8 B10,P3,P4,

to the two-bit burst counter.

2,83,99,100

P8,P9,P10,

R3,R4,R8,

R9,R10,R11

BW_A, BW_B,

BW_C, BW_D

93,94,95,96

88

B5,A5,A4,

B4

Input-

Byte Write Inputs, active LOW. Qualified with WE to conduct

Synchronous writes to the SRAM. Sampled on the rising edge of CLK.

WE

B7

Input- Write Enable Input, active LOW. Sampled on the rising edge

Synchronous of CLK if CEN is active LOW. This signal must be asserted LOW

to initiate a write sequence.

ADV/LD

85

A8

Input-

Advance/Load Input. Used to advance the on-chip address

Synchronous counter or load a new address. When HIGH (and CEN is

asserted LOW) the internal burst counter is advanced. When

LOW, a new address can be loaded into the device for anaccess.

After being deselected, ADV/LD should be driven LOW in order

to load a new address.

CLK

CE₁

CE₂

CE₃

89

98

97

92

B6

A3

B3

A6

Input-Clock Clock Input. Used to capture all synchronous inputs to the

device. CLK is qualified with CEN. CLK is only recognized if CEN

is active LOW.

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge

Synchronous of CLK. Used in conjunction with CE₂, and CE₃to select/deselect

the device.

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge

Synchronous of CLK. Used in conjunction with CE₁and CE₃to select/deselect

the device.

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge

Synchronous of CLK. Used in conjunction with CE₁andCE₂to select/deselect

the device.

Document #: 38-05688 Rev. *D

Page 3 of 15

CY7C1379C

Pin Definitions (continued)

Name

OE

TQFP

FBGA

I/O

Description

Output Enable, asynchronous input, active LOW. Combined

86

B8

Input-

Asynchronous with the synchronous logic block inside the device to control the

direction of the I/O pins. When LOW, the I/O pins are allowed to

behave as outputs. When deasserted HIGH, I/O pins are

tri-stated, and act as input data pins. OE is masked during the

data portion of a write sequence, during the first clock when

emerging from a deselected state, when the device has been

deselected.

CEN

87

64

A7

Input-

Clock Enable Input, active LOW. When asserted LOW the

Synchronous Clock signal is recognized by the SRAM. When deasserted

HIGH the Clock signal is masked. Since deasserting CEN does

not deselect the device, CEN can be used to extend the previous

cycle when required.

ZZ

H11

Input-

ZZ “sleep” Input. This active HIGH input places the device in a

Asynchronous non-time critical “sleep” condition with data integrity preserved.

For normal operation, this pin has to be LOW or left floating. ZZ

pin has an internal pull-down.

DQ_s

52,53,56,57,

58,59,62,63,

68,69,72,73,

74,75,78,79,

2,3,6,7,

8,9,12,13,

18,19,22,23,

24,25,28,29

M11,L11,

K11,J11,

J10,K10,

L10,M10,

D10,E10,

F10,G10,

D11,E11,

F11,G11,

D1,E1,F1,

G1,D2,E2,

F2,G2,J1,

K1,L1,M1,

J2,K2,L2

M2

I/O-

Bidirectional Data I/O Lines. As inputs, they feed into an

Synchronous on-chip data register that is triggered by the rising edge of CLK.

As outputs, they deliver the data contained in the memory

location specified by address during the clock rise of the Read

cycle. The direction of the pins is controlled by OE and the

internal control logic. When OE is asserted LOW, the pins can

behave as outputs. When HIGH, DQ_sare placed in a tri-state

condition. The outputs are automatically tri-stated during the

data portion of a write sequence, during the first clock when

emerging from a deselected state, and when the device is

deselected, regardless of the state of OE.

Mode

V_DD

31

R1

Input

Strap Pin

Mode Input. Selects the burst order of the device.

When tied to GND selects linear burst sequence. When tied to

V_DDor left floating selects interleaved burst sequence.

15,41,65,91

D4,D8,E4,

E8,F4,F8,

G4,G8,H2,

H4,H8,J4,

J8,K4,K8,

L4,L8,M4,

M8

Power Supply Power supply inputs to the core of the device.

V_DDQ

4,11,20,27,54,

61,70,77

C3,C9,D3,

D9,E3,E9,

F3,F9,G3,

G9,J3,J9,

K3,K9,L3,

L9,M3,M9,

N3,N9

I/O Power

Supply

Power supply for the I/O circuitry.

Document #: 38-05688 Rev. *D

Page 4 of 15

CY7C1379C

Pin Definitions (continued)

Name

V_SS

TQFP

FBGA

I/O

Description

5,10,17,21,

26,40,55,60,

67,71,76,90,

C4,C5,C6,

C7,C8,D5,

D6,D7,E5,

E6,E7,F5,

F6,F7,G5,

G6,G7,H5,

H6,H7,J5,

J6,J7,K5,K6,K

7,L5,L6,L7,M5

,M6,M7,

Ground

Ground for the device.

N4,N8

NC

1,16,30,38,39,

42,43,51,66,80,8 B9,B11,C1,

A1,A11,B1,

–

No Connects. Not Internally connected to the die.

18M, 36M, 72M, 144M, 288M, 576M, and 1G are address

expansion pins and are not internally connected to the die.

4,95,96

C2,C10,C11,H

1,H3,H9,

H10,N1,N2,

N5,N6,N7

N10,N11,P1,P

2,P5,P7,

P11,R2,R5,

R7

V_SS/DNU

14

-

Ground/DNU This pin can be connected to Ground or should be left floating.

access is in progress and allows the requested data to

propagate to the output buffers. The data is available within 6.5

Functional Overview

The CY7C1379C is a synchronous flow-through burst SRAM

designed specifically to eliminate wait states during

Write-Read transitions. All synchronous inputs pass through

input registers controlled by the rising edge of the clock. The

clock signal is qualified with the Clock Enable input signal

(CEN). If CEN is HIGH, the clock signal is not recognized and

all internal states are maintained. All synchronous operations

are qualified with CEN. Maximum access delay from the clock

rise (t_CDV) is 6.5 ns (133-MHz device).

ns (133-MHz device) provided OE is active LOW. After the first

clock of the read access, the output buffers are controlled by

OE and the internal control logic. OE must be driven LOW in

order for the device to drive out the requested data. On the

subsequent clock, another operation (Read/Write/Deselect)

can be initiated. When the SRAM is deselected at clock rise

by one of the chip enable signals, its output will be tri-stated

immediately.

Burst Read Accesses

Accesses can be initiated by asserting all three Chip Enables

(CE₁, CE₂, CE₃) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a read or write operation, depending on

the status of the Write Enable (WE). BW_[A:D]can be used to

conduct byte write operations.

The CY7C1379C has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address into the

SRAM, as described in the Single Read Access section above.

The sequence of the burst counter is determined by the MODE

input signal. A LOW input on MODE selects a linear burst

mode, a HIGH selects an interleaved burst sequence. Both

burst counters use A0 and A1 in the burst sequence, and will

wrap around when incremented sufficiently. A HIGH input on

ADV/LD will increment the internal burst counter regardless of

the state of chip enable inputs or WE. WE is latched at the

beginning of a burst cycle. Therefore, the type of access (Read

or Write) is maintained throughout the burst sequence.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Write Accesses

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE₁, CE₂,

and CE₃are ALL asserted active, and (3) the Write signal WE

is asserted LOW. The address presented to the address bus

is loaded into the Address Register. The write signals are

latched into the Control Logic block. The data lines are

automatically tri-stated regardless of the state of the OE input

signal. This allows the external logic to present the data on

DQs.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE₁, CE₂,

and CE₃are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and 4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory array

and control logic. The control logic determines that a read

Document #: 38-05688 Rev. *D

Page 5 of 15

CY7C1379C

On the next clock rise the data presented to DQs (or a subset

for Byte Write operations, see Truth Table for details) inputs is

latched into the device and the write is complete. Additional

accesses (Read/Write/Deselect) can be initiated on this cycle.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE₁, CE₂, and CE₃, must remain inactive for

the duration of t_ZZRECafter the ZZ input returns LOW.

The data written during the Write operation is controlled by

BW_[A:D]signals. The CY7C1379C provides Byte Write

capability that is described in the truth table. Asserting the

Write Enable input (WE) with the selected Byte Write Select

input will selectively write to only the desired bytes. Bytes not

selected during a Byte Write operation will remain unaltered.

A synchronous self-timed write mechanism has been provided

to simplify the Write operations. Byte Write capability has been

included in order to greatly simplify Read/Modify/Write

sequences, which can be reduced to simple Byte Write opera-

tions.

Linear Burst Address Table

(MODE = GND)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

Because the CY7C1379C is a common I/O device, data

should not be driven into the device while the outputs are

active. The Output Enable (OE) can be deasserted HIGH

before presenting data to the DQ inputs. Doing so will tri-state

the output drivers. As a safety precaution, DQs and DQP_X.are

automatically tri-stated during the data portion of a write cycle,

regardless of the state of OE.

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

Burst Write Accesses

Interleaved Burst Sequence

The CY7C1379C has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Write operations without reasserting the address inputs.

ADV/LD must be driven LOW in order to load the initial

address, as described in the Single Write Access section

above. When ADV/LD is driven HIGH on the subsequent clock

rise, the Chip Enables (CE₁, CE₂, and CE₃) and WE inputs are

ignored and the burst counter is incremented. The correct

BW_[A:D]inputs must be driven in each cycle of the burst write,

in order to write the correct bytes of data.

First

Second

Third

Fourth

Address

A1, A0

00

A1, A0

01

A1, A0

10

A1, A0

11

01

00

11

10

11

00

01

11

10

01

00

ZZ Mode Electrical Characteristics

Parameter

I_DDZZ

Description

Sleep mode standby current

Device operation to ZZ

Test Conditions

Min.

Max.

50

Unit

mA

ns

ZZ > V_DD− 0.2V

t_ZZS

ZZ > V_DD− 0.2V

2t_CYC

t_ZZREC

t_ZZI

ZZ recovery time

ZZ < 0.2V

2t_CYC

0

ns

ZZ Active to Sleep current

ZZ inactive to exit Sleep current

This parameter is sampled

2t_CYC

ns

t_RZZI

ns

Document #: 38-05688 Rev. *D

Page 6 of 15

CY7C1379C

Truth Table^{[2, 3, 4, 5, 6, 7, 8]}

ADRESS

Used

/

Operation

Deselect Cycle

CE₁CE₂CE₃ZZ ADV

WE BW_XOE CEN CLK

DQ

LD

None

H

X

L

X

L

X

H

X

L

H

L

X

H

X

H

X

L

X

L

X

L

H

X

L->H

Tri-State

Deselect Cycle

L

Deselect Cycle

None

Continue Deselect Cycle

READ Cycle (Begin Burst)

READ Cycle (Continue Burst)

None

X

H

X

H

X

H

X

H

X

H

L

External

L->H Data Out (Q)

X

L

X

L

H

L

NOP/DUMMY READ (Begin Burst) External

H

X

L->H

Tri-State

DUMMY READ (Continue Burst)

WRITE Cycle (Begin Burst)

L

X

L

H

L

L->H Data In (D)

WRITE Cycle (Continue Burst)

X

L

X

L

H

L

X

L

NOP/WRITE ABORT (Begin Burst) None

H

X

L->H

X

Tri-State

–

WRITE ABORT (Continue Burst)

IGNORE CLOCK EDGE (Stall)

Sleep MODE

None

X

H

X

Tri-State

Truth Table for Read/Write^{[2, 3]}

Function (CY7C1379C)

Read

WE

BW_A

BW_B

BW_C

BW_D

X

H

L

X

H

L

X

H

L

X

H

L

Write No Bytes Written

Write Byte A – (DQ_A)

Write Byte B – (DQ_B)

Write Byte C – (DQ_C)

Write Byte D – (DQ_D)

Write All Bytes

H

L

H

L

H

L

Notes:

2. X =”Don't Care.” H = HIGH, L = LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are

asserted, see Truth Table for details.

3. Write is defined by BW , and WE. See Truth Table for Read/Write.

X

4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.

5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. CEN = H, inserts wait states.

7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs = Three-state when OE is inactive

or when the device is deselected, and DQs = data when OE is active.

Document #: 38-05688 Rev. *D

Page 7 of 15

CY7C1379C

DC Input Voltage ................................... –0.5V to V_DD+ 0.5V

Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Storage Temperature .................................–65°C to +150°C

Latch-up Current.................................................... > 200 mA

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Operating Range

Supply Voltage on V_DDRelative to GND........ –0.5V to +4.6V

Supply Voltage on V_DDQRelative to GND ......–0.5V to +V_DD

Ambient

Range

Com’l

Ind’l

Temperature (T_A)

V_DD/V_DDQ

DC Voltage Applied to Outputs

in High-Z State .................................... –0.5V to V_DDQ+ 0.5V

0°C to +70°C

3.3V – 5%/+10%

–40°C to +85°C

Electrical Characteristics Over the Operating Range ^{[9, 10]}

Parameter

V_DD

Description

Test Conditions

Min.

Max.

3.6

Unit

Power Supply Voltage

I/O Supply Voltage

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage^[9]

3.135

2.4

V

V_DDQ

V_OH

for 3.3V I/O

V_DD

for 3.3V I/O, I_OH= –4.0 mA

for 3.3V I/O, I_OL= 8.0 mA

for 3.3V I/O

V

V_OL

0.4

V

V_IH

2.0

–0.3

−5

V_DD+ 0.3V

V

V_IL

for 3.3V I/O

0.8

5

V

I_X

Input Leakage Current GND ≤ V_I≤ V_DDQ

except ZZ and MODE

µA

Input Current of MODE Input = V_SS

Input = V_DDQ

–30

–5

µA

mA

5

Input Current of ZZ

Input = V_SS

Input = V_DDQ

30

5

I_OZ

I_DD

Output Leakage Current GND ≤ V_I≤ V_DDQ, Output Disabled

–5

V_DDOperating Supply

Current

V_DD= Max., I_OUT= 0 mA,

f = f_MAX= 1/t_CYC

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

250

180

110

I_SB1

I_SB2

I_SB3

I_SB4

Automatic CE

V_DD= Max, Device Deselected, All speeds

Power-down

Current—TTL Inputs

V_IN≥ V_IHor V_IN≤ V_IL, f = f_MAX,

inputs switching

Automatic CE

Power-down

Current—CMOS Inputs f = 0, inputs static

V_DD= Max, Device Deselected, All speeds

V_IN≥ V_DD– 0.3V or V_IN≤ 0.3V,

40

100

40

mA

Automatic CE

Power-down

Current—CMOS Inputs f = f_MAX, inputs switching

V

_DD= Max, Device Deselected, All speeds

V_IN≥ V_DDQ– 0.3V or V_IN≤ 0.3V,

Automatic CE

Power-down

Current—TTL Inputs

V_DD= Max, Device Deselected, All speeds

V_IN≥ V_IHor V_IN≤ V_IL, f = 0,

inputs static

Notes:

9. Overshoot: V (AC) < V +1.5V (Pulse width less than t

/2), undershoot: V (AC)> –2V (Pulse width less than t

/2).

IH

DD

CYC

IL

10. T

: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V

< V

.

Power-up

DD

IH

DD

DDQ

DD

Document #: 38-05688 Rev. *D

Page 8 of 15

CY7C1379C

Capacitance^[11]

100 TQFP

Max.

165 FBGA

Parameter

Description

Test Conditions

Max.

Unit

pF

C_IN

Input Capacitance

Clock Input Capacitance

I/O Capacitance

T_A= 25°C, f = 1 MHz,

5

7

V_DD= 3.3V

C_CLOCK

C_I/O

pF

V_DDQ=3.3V

pF

Thermal Resistance^[11]

100 TQFP

Package

165 FBGA

Parameters

Θ_JA

Description

Test Conditions

Package

Unit

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA/JESD51

29.41

16.8

°C/W

Θ_JC

Thermal Resistance

(Junction to Case)

6.13

3.0

°C/W

AC Test Loads and Waveforms

3.3V I/O Test Load

R = 317Ω

3.3V

OUTPUT

ALL INPUT PULSES

90%

V_DD

90%

10%

Z = 50Ω

0

R = 50Ω

10%

L

GND

5 pF

R = 351Ω

≤ 1 ns

INCLUDING

JIG AND

SCOPE

V = 1.5V

L

(a)

(b)

(c)

Switching Characteristics Over the Operating Range^{[12, 13, 14, 15, 16, 17]}

–133

Min. Max.

–100

Parameter

t_POWER

Description

V_DD(Typical) to the First Access^[14]

Min.

Max.

Unit

1

ms

Clock

t_CYC

Clock Cycle Time

Clock HIGH

7.5

3.0

10.0

4.0

ns

t_CH

t_CL

Clock LOW

4.0

Output Times

t_CDV

Data Output Valid after CLK Rise

Data Output Hold after CLK Rise

Clock to Low-Z^{[15, 16, 17]}

6.5

7.5

ns

t_DOH

2.0

0

2.0

0

t_CLZ

t_CHZ

Clock to High-Z^{[15, 16, 17]}

3.5

t_OEV

OE LOW to Output Valid

t_OELZ

t_OEHZ

OE LOW to Output Low-Z^{[15, 16, 17]}

OE HIGH to Output High-Z^{[15, 16, 17]}

0

3.5

Notes:

11. Tested initially and after any design or process changes that may affect these parameters.

12. Timing reference level is 1.5V when V =3.3V.

DDQ

13. Test conditions shown in (a) of AC Test Loads, unless otherwise noted.

14. This part has a voltage regulator internally; t

is the time that the power needs to be supplied above V (minimum) initially, before a read or write operation

POWER

DD

can be initiated.

15. t

, t

,t

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

OEHZ

CHZ CLZ OELZ

16. At any given voltage and temperature, t

is less than t

and t

is less than t

to eliminate bus contention between SRAMs when sharing the same

OEHZ

OELZ

CHZ

CLZ

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

17. This parameter is sampled and not 100% tested.

Document #: 38-05688 Rev. *D

Page 9 of 15

CY7C1379C

Switching Characteristics Over the Operating Range^{[12, 13, 14, 15, 16, 17]}(continued)

–133

Min. Max.

–100

Parameter

Description

Min.

Max.

Unit

Set-up Times

t_AS

Address Set-up before CLK Rise

1.5

ns

t_ALS

ADV/LD Set-up before CLK Rise

WE, BW_[A:D]Set-up before CLK Rise

CEN Set-up before CLK Rise

t_WES

t_CENS

t_DS

Data Input Set-up before CLK Rise

Chip Enable Set-up before CLK Rise

t_CES

Hold Times

t_AH

Address Hold after CLK Rise

ADV/LD Hold after CLK Rise

WE, BW_XHold after CLK Rise

CEN Hold after CLK Rise

0.5

ns

t_ALH

t_WEH

t_CENH

t_DH

Data Input Hold after CLK Rise

Chip Enable Hold after CLK Rise

t_CEH

Document #: 38-05688 Rev. *D

Page 10 of 15

CY7C1379C

Switching Waveforms

Read/Write Waveforms^{[18, 19, 20]}

t

1

2

3

4

5

6

7

8

9

10

CYC

t

CLK

CEN

t

CENS

CES

CENH

CEH

CL

CH

CE

ADV/LD

WE

BW[A:D]

A1

A2

A4

A3

A5

A6

A7

ADDRESS

DQ

t

CDV

t

AS

AH

t

CHZ

DOH

OEV

CLZ

D(A1)

t

D(A2)

D(A2+1)

Q(A3)

Q(A4)

Q(A4+1)

D(A5)

Q(A6)

D(A7)

t

OEHZ

t

DS

DH

t

DOH

t

OELZ

OE

COMMAND

WRITE

D(A1)

WRITE

D(A2)

BURST

WRITE

READ

Q(A3)

READ

Q(A4)

BURST

READ

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

D(A2+1)

Q(A4+1)

DON’T CARE

UNDEFINED

Notes:

For this waveform ZZ is tied LOW.

18.

19. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.

1

2

3

1

2

3

20. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

Document #: 38-05688 Rev. *D

Page 11 of 15

CY7C1379C

Switching Waveforms (continued)

NOP, STALL and Deselect Cycles^{[18, 19, 21]}

1

2

3

4

5

6

7

8

9

10

CLK

CEN

CE

ADV/LD

WE

BW^[A:D]

ADDRESS

A1

A2

A3

A4

A5

t

CHZ

D(A1)

Q(A2)

Q(A3)

D(A4)

Q(A5)

DQ

t

DOH

COMMAND

WRITE

D(A1)

READ

Q(A2)

STALL

READ

Q(A3)

WRITE

D(A4)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

ZZ Mode Timing^{[22, 23]}

CLK

t

ZZ

ZZREC

ZZ

t

ZZI

I

SUPPLY

I

DDZZ

t

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes:

21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

22. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.

23. I/Os are in High-Z when exiting ZZ sleep mode.

Document #: 38-05688 Rev. *D

Page 12 of 15

CY7C1379C

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Part and Package Type

133 CY7C1355C-133AXC

CY7C1355C-133BZC

CY7C1355C-133BZXC

CY7C1355C-133AXI

CY7C1355C-133BZI

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

51-85122 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2 mm)

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2 mm) Lead-Free