CY7C1380CV25-225AI [CYPRESS]
512K x 36/1M x 18 Pipelined SRAM; 512K ×36 / 1M ×18的SRAM流水线
| 型号： | CY7C1380CV25-225AI |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 36/1M x 18 Pipelined SRAM |
| 文件： | 总33页 (文件大小：520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
380CV25
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
512K x 36/1M x 18 Pipelined SRAM
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE), burst control in-
puts (ADSC, ADSP, and ADV), write enables (BWa, BWb,
BWc, BWd and BWE), and global write (GW).
Features
• Fast clock speed: 250, 225, 200, 167 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns
• Optimal for depth expansion
Asynchronous inputs include the output enable (OE) and burst
mode control (MODE). The data (DQa,b,c,d) and the data par-
ity (DQPa,b,c,d) outputs, enabled by OE, are also asynchro-
nous.
• Single 2.5V ±5% power supply
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data, and control registers
• Internally self-timed Write cycle
DQa,b,c,d and DPa,b,c,d apply to CY7C1380CV25 and
DQa,b and DPa,b apply to CY7C1382CV25. a, b, c, d each
are of 8 bits wide in the case of DQ and 1 bit wide in the case
of DP.
Addresses and chip enables are registered with either address
status processor (ADSP) or address status controller (ADSC)
input pins. Subsequent burst addresses can be internally gen-
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down available using ZZ mode or CE
deselect
erated as controlled by the burst advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. BWa con-
trols DQa and DPa. BWb controls DQb and DPb. BWc controls
DQc and DPd. BWd controls DQd and DPd. BWa, BWb BWc,
and BWd can be active only with BWE being LOW. GW being
LOW causes all bytes to be written. Write pass-through capa-
bility allows written data available at the output for the next
Read cycle. This device also incorporates pipelined enable
circuit for easy depth expansion without penalizing system
performance.
• Available in 119-ball bump BGA, 165-ball FBGA and
100-pin TQFP packages
• JTAG boundary scan for BGA packaging version
Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced single-layer
polysilicon, triple-layer metal technology. Each memory cell
consists of six transistors.
The CY7C1382CV25 and CY7C1380CV25 SRAMs integrate
1,048,576x18 and 524,288x36 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
isters controlled by a positive-edge-triggered clock input
All inputs and outputs of the CY7C1380CV25 and the
CY7C1382CV25 are JEDEC standard JESD8-5 compatible.
Selection Guide
250 MHz
225 MHz
2.8
200 MHz
3.0
167 MHz
3.4
Unit
ns
Maximum Access Time
2.6
350
70
Maximum Operating Current
325
300
275
mA
mA
Maximum CMOS Standby Current
70
70
70
Shaded areas contain advance information.
Cypress Semiconductor Corporation
Document #: 38-05240 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 20, 2002
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
CY7C1380CV25 - 512K x 36
MODE
2
(A
)
[1;0]
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
17
19
ADDRESS
REGISTER
CE
D
512KX36
MEMORY
ARRAY
A
[18:0]
19
17
GW
DQd, DPd
BYTEWRITE
REGISTERS
D
Q
BWE
BW
d
DQc, DPc
BYTEWRITE
REGISTERS
D
D
D
Q
Q
Q
BW
c
DQb, DPb
BYTEWRITE
REGISTERS
BW
b
DQa, DPa
BYTEWRITE
REGISTERS
BW
a
36
36
CE
2
1
CE
D
D
Q
ENABLE CE
REGISTER
CE
3
Q
OUTPUT
REGISTERS
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
CLK
OE
ZZ
SLEEP
CONTROL
DQ
a,b,c,d
DP
a,b
CY7C1382CV25 - 1M X 18
MODE
2
(A
)
[1;0]
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
18
20
ADDRESS
REGISTER
CE
D
1M X 18
A
[19:0]
20
18
MEMORY
ARRAY
GW
DQb, DPb
BYTEWRITE
REGISTERS
D
Q
BWE
BW
b
DQa, DPa
BYTEWRITE
REGISTERS
D
Q
BW
a
18
18
CE
2
1
CE
D
CE
Q
ENABLE CE
REGISTER
CE
3
D
Q
OUTPUT
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
a,b
a,b
DP
Document #: 38-05240 Rev. *A
Page 2 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Pin Configurations
100-Pin TQFP
Top View
NC,DQPc
1
NC,DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DPa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
2
DQc
3
4
5
6
7
8
9
V
DDQ
V
DDQ
V
SSQ
V
SSQ
DQc
DQc
DQc
DQc
DQb
DQb
DQb
DQb
NC
DQb
DQb
VSSQ
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DPb
NC
V
SSQ
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSQ
9
V
DDQ
V
DDQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQc
DQc
NC
DQb
DQb
V
SS
CY7C1380CV25
(512K X 36)
V
DD
NC
NC
CY7C1382CV25
(1M x 18)
V
DD
V
SS
ZZ
DQa
DQa
DQd
DQd
VDD
ZZ
V
V
DDQ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
DDQ
V
DQd
DQd
DQd
DQd
SSQ
V
SSQ
DQa
DQa
DQa
DQa
V
SSQ
V
SSQ
V
DDQ
V
DDQ
NC
DQd
DQd
NC,DQPd
DQa
DQa
NC,DQPa
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
Document #: 38-05240 Rev. *A
Page 3 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Pin Configurations (continued)
119-Ball BGA
CY7C1380CV25 (512K x 36)
1
2
3
4
5
6
7
A
A
A
VDDQ
NC
A
A
VDDQ
A
A
ADSP
ADSC
VDD
A
A
B
C
D
E
F
NC
NC
NC
A
A
A
A
DQPb
DQb
DQb
VSS
VSS
VSS
VSS
DQPc
DQc
NC
DQb
DQb
DQc
DQc
CE1
OE
VSS
VSS
BWb
VSS
VDDQ
DQc
VDDQ
DQb
DQb
VDDQ
DQa
DQb
ADV
GW
VDD
G
H
J
DQc
DQc
DQc
DQc
VDD
DQd
DQd
BWc
VSS
NC
DQb
VDD
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
NC
K
L
VSS
VSS
DQa
DQa
DQa
DQa
DQPa
A
CLK
NC
BWd
VSS
VSS
BWa
VSS
VSS
VSS
DQa
VDDQ
DQa
M
DQd
DQd
BWE
A1
N
P
R
T
DQPd
DQa
VSS
MODE
A
A0
VDD
A
NC
A
A
NC
ZZ
72M
36M
NC
NC
U
VDDQ
TMS
TDI
TCK
TDO
VDDQ
CY7C1382CV25 (1M x 18)
1
2
3
4
5
6
7
A
B
C
D
E
F
A
A
VDDQ
NC
A
A
A
A
VDDQ
NC
A
A
ADSP
ADSC
VDD
NC
NC
A
A
A
A
VSS
VSS
VSS
VSS
DQb
NC
NC
NC
DQPa
NC
NC
DQa
VDDQ
DQa
NC
DQb
CE1
OE
VSS
DQa
VDDQ
NC
VSS
VSS
VSS
NC
NC
ADV
GW
VDD
G
H
J
DQb
NC
BWb
VSS
NC
NC
DQb
DQa
VDD
VDDQ
DQa
VDDQ
NC
VDD
DQb
NC
K
L
VSS
NC
DQa
NC
DQa
NC
A
VSS
VSS
CLK
NC
DQb
VDDQ
DQb
NC
BWa
VSS
VSS
NC
VDDQ
NC
M
DQb
NC
BWE
A1
VSS
VSS
N
P
R
T
DQPb
DQa
VSS
MODE
A
A0
VSS
NC
A
NC
VDD
36M
TCK
A
A
NC
ZZ
A
72M
VDDQ
U
TMS
TDI
TDO
NC
VDDQ
Document #: 38-05240 Rev. *A
Page 4 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Pin Configurations (continued)
165-Ball Bump FBGA
CY7C1380CV25 (512K x 36) - 11 x 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWc
BWb
CE
BWE
A
ADSC
ADV
A
NC
1
2
3
NC
DPc
DQc
A
CE
BWd
BWa
CLK
GW
B
C
D
OE
ADSP
A
144M
DPb
NC
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DQc
V
V
V
V
V
V
DQb
DQb
DD
SS
SS
SS
DD
DDQ
DQc
DQc
DQc
NC
DQc
DQc
DQc
V
V
V
V
E
F
V
V
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
G
H
J
V
V
DD
SS
SS
SS
DD
DDQ
V
NC
V
V
V
V
V
NC
SS
DD
SS
SS
SS
DD
DQd
DQd
DQd
DQd
DPd
NC
DQd
DQd
DQd
DQd
NC
V
V
V
V
V
V
V
DQa
DQa
DQa
DQa
NC
DQa
DQa
DQa
DQa
DPa
A
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
V
V
K
L
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
M
N
P
V
V
DDQ
DD
SS
SS
SS
DD
DDQ
V
NC
TDI
A
V
V
V
DDQ
SS
SS
SS
DDQ
72M
A
A
A
A1
A0
TDO
TCK
A
A
A
A
A
MODE
36M
A
TMS
R
A
A
CY7C1382CV25 (1M x 18) - 11 x 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWb
NC
CE
BWE
A
ADSC
ADV
A
A
1
2
3
NC
NC
NC
A
CE
NC
BWa
CLK
GW
B
C
D
E
F
OE
ADSP
A
144M
DPa
NC
V
V
V
V
V
V
V
V
V
V
V
NC
NC
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DQb
V
V
V
V
V
V
DQa
DD
SS
SS
SS
DD
DDQ
NC
NC
DQb
DQb
DQb
V
V
V
V
V
V
NC
NC
DQa
DQa
DQa
ZZ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
NC
V
V
V
V
G
H
J
V
V
NC
DD
SS
SS
SS
DD
DDQ
NC
V
NC
V
V
V
V
V
NC
NC
SS
DD
SS
SS
SS
DD
DQb
DQb
DQb
DQb
DPb
NC
NC
NC
NC
NC
NC
72M
V
V
V
V
V
V
V
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
NC
A
DDQ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
V
V
K
L
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
M
N
P
V
V
DD
SS
SS
SS
DD
DDQ
V
NC
TDI
A
V
V
V
DDQ
SS
SS
SS
DDQ
A
A
A
A1
A0
TDO
TCK
A
A
A
A
A
MODE
36M
A
TMS
R
A
A
Document #: 38-05240 Rev. *A
Page 5 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Pin Definitions
Name
I/O
Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2,
and CE3 are sampled active. A[1:0] feed the 2-bit counter.
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless of
the values on BWa,b,c,d and BWE).
BWE
CLK
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte write.
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ig-
nored if CE1 is HIGH.
CE2
CE3
OE
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE3 to select/deselect the device. (TQFP Only)
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE2 to select/deselect the device. (TQFP Only)
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of
the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK. When asserted,
Synchronous
it automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK.
When asserted LOW, A is captured in the address registers. A[1:0] are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK.
When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
MODE
ZZ
Input-Pin
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to VDDQ or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation.
Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time
critical “sleep” condition with data integrity preserved.
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A[X] during the previous clock
rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are
placed in a three-state condition. DQ a,b,c, and d are 8 bits wide and the DP
a,b,c, and d are 1 bit wide.
TDO
TDI
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of
TCK. (BGA Only)
JTAG serial input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.(BGA
Only)
Document #: 38-05240 Rev. *A
Page 6 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Pin Definitions
Name
I/O
Description
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the
rising edge of TCK. (BGA Only)
TCK
VDD
JTAG serial clock
Power Supply
Serial clock to the JTAG circuit. (BGA Only)
Power supply inputs to the core of the device. Should be connectedto2.5V
± 5% power supply.
VSS
Ground
Ground for the core of the device. Should be connected to ground of the
system.
VDDQ
VSSQ
NC
I/O Power Supply
Power supply for the I/O circuitry.
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
No Connects.Pins are not internally connected.
No Connects. Reserved for address expansion.
-
-
36M
72M
144M
Document #: 38-05240 Rev. *A
Page 7 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
(GW, BWE, and BWx) and ADV inputs are ignored during this
first cycle.
Introduction
Functional Overview
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx sig-
nals. The CY7C1380CV25/CY7C1382CV25 provides byte
write capability that is described in the write cycle description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write (BWa,b,c,d for CY7C1380CV25 and
BWa,b for CY7C1382CV25) input will selectively write to only
the desired bytes. Bytes not selected during a byte write oper-
ation will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise (tCO) is 2.6 ns (250-MHz
device).
The CY7C1380CV25/CY7C1382CV25 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium® and
i486 processors. The linear burst sequence is suited for pro-
cessors that utilize a linear burst sequence. The burst order is
user selectable, and is determined by sampling the MODE in-
put. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Because the CY7C1380CV25/CY7C1382CV25 is a common
I/O device, the output enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will three-
state the output drivers. As a safety precaution, DQ are auto-
matically three-stated whenever a write cycle is detected, re-
gardless of the state of OE.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for CY7C1380V25 and
BWa,b for CY7C1382V25) inputs. A Global Write Enable (GW)
overrides all byte write inputs and writes data to all four bytes.
All writes are simplified with on-chip synchronous self-timed
write circuitry.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BWx) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented to A[17:0] is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is ig-
nored during this cycle. If a global write is conducted, the data
presented to the DQ[x:0] is written into the corresponding ad-
dress location in the RAM core. If a byte write is conducted,
only the selected bytes are written. Bytes not selected during
a byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for
BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. ADSP is
ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Because the CY7C1380CV25/CY7C1382CV25 is a common
I/O device, the output enable (OE) must be deasserted HIGH
before presenting data to the DQ[x:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[x:0]
are automatically three-stated whenever a write cycle is de-
tected, regardless of the state of OE.
Burst Sequences
The CY7C1380CV25/CY7C1382CV25 provides a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst se-
quence is designed specifically to support Intel® Pentium ap-
plications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst se-
quence is user selectable through the MODE input.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is load-
ed into the address register and the address advancement
logic while being delivered to the RAM core. The write signals
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Document #: 38-05240 Rev. *A
Page 8 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Sleep Mode
Interleaved Burst Sequence
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CEs, ADSP, and ADSC must remain inactive for the duration
of tZZREC after the ZZ input returns LOW.
First
Second
Third
Address
Fourth
Address
Address
Address
A[1:0]]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Test Conditions
Min.
Max.
Unit
Sleep mode stand-
by current
ZZ > VDD − 0.2V
60
mA
tZZS
Deviceoperationto
ZZ
ZZ > VDD − 0.2V
ZZ < 0.2V
2tCYC
ns
ns
tZZREC
ZZ recovery time
2tCYC
Document #: 38-05240 Rev. *A
Page 9 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Cycle Descriptions[1, 2, 3, 4]
Next Cycle
Unselected
Add. Used
None
ZZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
CE3
X
1
CE2
X
X
0
CE1
1
ADSP
X
0
ADSC
ADV
X
X
X
X
X
X
X
0
OE
X
X
X
X
X
X
X
1
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Write
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
X
Unselected
None
0
X
Unselected
None
X
1
0
0
X
Unselected
None
X
0
0
1
X
Unselected
None
X
0
0
1
X
Begin Read
External
External
Next
1
0
0
X
Begin Read
0
1
0
1
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
1
X
X
1
1
Next
1
0
0
Next
X
X
1
0
1
Hi-Z
DQ
Next
1
0
0
Current
Current
Current
Current
Current
Current
External
Next
X
X
1
1
1
Hi-Z
DQ
1
1
0
X
X
1
1
1
Hi-Z
DQ
1
1
0
X
1
1
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Begin Write
X
1
1
Begin Write
0
X
0
Continue Write
Continue Write
Suspend Write
Suspend Write
X
X
X
X
X
X
X
X
X
X
X
1
1
Next
X
1
0
Current
Current
None
X
1
1
X
X
1
ZZ “sleep”
X
X
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. CE1, CE2 and CE3 are available only in the TQFP package. The BGA package has a single chip select, CE1.
Document #: 38-05240 Rev. *A
Page 10 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Write Cycle Descriptions[1, 5, 6]
Function (1380CV25)
Read
GW
1
BWE
1
BWd
X
1
BWc
X
1
BWb
X
1
BWa
X
1
Read
1
0
Write Byte 0 – DQa
Write Byte 1 – DQb
Write Bytes 1, 0
Write Byte 2 – DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 – DQd
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
1
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Function (1382CV25)
GW
1
BWE
BWb
BWa
Read
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
Read
1
Write Byte 0 – DQ[7:0] and DP0
Write Byte 1 – DQ[15:8] and DP1
Write All Bytes
1
1
1
Write All Bytes
0
Notes:
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a
“don't care” for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ = High-Z when OE is inactive or
when the device is deselected, and DQ = data when OE is active.
Document #: 38-05240 Rev. *A
Page 11 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
ry. Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1380CV25/CY7C1382CV25 incorporates a serial
boundary scan Test Access Port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1-1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as de-
scribed in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are in-
ternally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the oper-
ation of the device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port (TAP)—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 70-bit-long reg-
ister, and the x18 configuration has a 51-bit-long register.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the regis-
ters and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruc-
tion that is loaded into the TAP instruction register. For infor-
mation on loading the instruction register, see the TAP Con-
troller State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Defi-
nitions table.
The TDO output pin is used to serially clock data-out from the
registers. The e output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is operat-
ing. At power-up, the TAP is reset internally to ensure that TDO
comes up in a high-Z state.
Eight different instructions are possible with the three-bit in-
struction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RE-
SERVED and should not be used. The other five instructions
are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller can-
not be used to load address, data or control signals into the
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuit-
Document #: 38-05240 Rev. *A
Page 12 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
Instructions are loaded into the TAP controller during the Shift-
IR state when the instruction register is placed between TDI
and TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction once it is shifted in, the TAP controller needs to
be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be ex-
ecuted whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in the TAP controller, and there-
fore this device is not compliant to the 1149.1 standard.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction, EX-
TEST places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or when-
ever the TAP controller is given a test logic reset state.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the Update-
DR state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
Bypass
When the BYPASS instruction is loaded in the instruction reg-
ister and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The advan-
tage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a
board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Reserved
SAMPLE/PRELOAD
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
Document #: 38-05240 Rev. *A
Page 13 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
TAP Controller State Diagram
TEST-LOGIC
1
RESET
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05240 Rev. *A
Page 14 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
TDO
2
1
0
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[7, 8]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
Description
Test Conditions
Min.
1.7
Max.
Unit
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOH = −1.0 mA
IOH = −100 µA
IOL = 1.0 mA
IOL = 100 µA
2.1
V
0.4
0.2
V
V
1.7
−0.3
−5
V
DD + 0.3
V
VIL
0.7
V
IX
GND < VI < VDDQ
5
µA
Notes:
7. All Voltage referenced to Ground.
8. Overshoot: VIH(AC) < VDD+1.5V for t < tTCYC/2, Undershoot: VIL(AC) > −0.5V for t < tTCYC/2.
Document #: 38-05240 Rev. *A
Page 15 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameters
tTCYC
Description
Min.
Max
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
tTF
10
MHz
ns
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
tTDOX
0
Notes:
9.
tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 V/ns.
Document #: 38-05240 Rev. *A
Page 16 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
TAP Timing and Test Conditions
1.25V
50Ω
ALL INPUT PULSES
TDO
2.5V
Z = 50Ω
0
1.25V
C = 20 pF
L
0V
GND
(a)
tTL
tTH
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Document #: 38-05240 Rev. *A
Page 17 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Identification Register Definitions
Instruction Field
512K x 36
1M x 18
Description
Revision Number
(31:28)
0100
0100
Reserved for version number
Cypress Device ID
(27:24)
1011
000000
1011
000000
Reserved for internal use
Device Type
(23:18)
Defines memory type and architecture
Defines width and density
Device Width and Density
(17:12)
100101
010101
Cypress JEDEC ID
(11:0)
000001101001
000001101001
Allows unique identification of SRAM
vendor
Scan Register Sizes
Register Name
Instruction
Bit Size (x18)
Bit Size (x36)
3
1
3
1
Bypass
ID
32
51
32
70
Boundary Scan
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register be-
tween TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
Captures the Input/Output contents. Places the boundary scan register be-
tween TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction
does not implement 1149.1 preload function and is therefore not 1149.1
compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
Document #: 38-05240 Rev. *A
Page 18 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Boundary Scan Order (512K x 36)
Boundary Scan Order (1M x 18)
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Bit #
Bit #
36
Bit #
Bit #
36
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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TBD
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TBD
TBD
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TBD
TBD
TBD
TBD
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TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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TBD
TBD
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TBD
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TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
2
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Document #: 38-05240 Rev. *A
Page 19 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Operating Range
Storage Temperature .................................–55°C to +150°C
Ambient Temperature with
Ambient
Power Applied.............................................–55°C to +125°C
Range
Com’l
Temp.[12]
0°C to 70°C
VDD/VDDQ
Supply Voltage on VDD Relative to GND ....... –0.3V to +3.6V
2.5V ± 5%
DC Voltage Applied to Outputs
in High Z State[11]................................ –0.5V to VDDQ + 0.5V
Ind’l
–40°C to +85°C
DC Input Voltage[11] ............................ –0.5V to VDDQ + 0.5V
Current into Outputs (LOW).........................................20 mA
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max. Unit
VDD/VDDQ Power Supply Voltage
2.375 2.625
V
V
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VDD = Min., IOH = −1.0 mA
VDD = Min., IOL = 1.0 mA
2.0
0.4
1.7
VDD
0.3
+
VIL
IX
Input LOW Voltage[11]
–0.3
–5
0.7
5
Input Load Current
except ZZ and MODE
GND < VI < VDDQ
µA
IZZ
Input Current of MODE
Input Current of ZZ
−30
−30
–5
30
30
5
µA
µA
Input = VSS
IOZ
IDD
Output Leakage Current
VDD Operating Supply
GND < VI < VDDQ, Output Disabled
µA
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speed grades
350
325
300
275
120
110
100
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
Automatic CE Power-
Down Current—TTL Inputs
Max. VDD, Device Deselected,
VIN > VIH or VIN < VIL
f = fMAX = 1/tCYC
ISB2
Automatic CE Power-
Down Current—CMOS
Inputs
Max. VDD, Device Deselected,
VIN < 0.3V or VIN > VDDQ – 0.3V,
f = 0
70
ISB3
Automatic CE Power-
Down Current—CMOS
Inputs
Max. VDD, Device Deselected, or 4.0-ns cycle, 250 MHz
105
100
95
mA
mA
mA
mA
mA
VIN < 0.3V or VIN > VDDQ – 0.3V
4.4-ns cycle, 225 MHz
f = fMAX = 1/tCYC
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
85
ISB4
Automatic CE Power-
Max. VDD, Device Deselected,
All Speeds
80
Down Current—TTL Inputs VIN > VIH or VIN < VIL, f = 0
Shaded areas contain advance information.
Notes:
11. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
12.
TA is the temperature.
Document #: 38-05240 Rev. *A
Page 20 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Capacitance[13]
Max.
100-TQFP 119-BGA
Parameter
CIN
Description
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz
165-FBGA
TBD
Unit
pF
TBD
TBD
TBD
TBD
TBD
TBD
CCLK
Clock Input Capacitance
Input/Output Capacitance
TBD
pF
CI/O
TBD
pF
AC Test Loads and Waveforms[14]
R = 1667Ω
V
DDQ
[10]
ALL INPUT PULSES
90%
OUTPUT
OUTPUT
2.5V
90%
10%
Z = 50Ω
0
10%
R = 50Ω
t
5 pF
GND
R = 1538Ω
30 pF
≤ 1 ns
≤ 1 ns
V = 1.25
t
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
V - Termination Voltage
t
R - Termination Resistance
t
Thermal Resistance[13]
Description
Test Conditions
Symbol
TQFP
119 BGA
165 FBGA
Unit
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3
x 4.5 inch2, 2-layer
printed circuit board
ΘJA
31
45
46
°C/W
Thermal Resistance
(Junction to Case)
ΘJC
6
7
3
°C/W
Notes:
13. Tested initially and after any design or process changes that may affect these parameters.
14. Input waveform should have a slew rate of < 1 ns.
Document #: 38-05240 Rev. *A
Page 21 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Switching Characteristics Over the Operating Range[15, 16, 17]
-250
-225
-200
-167
Parameter
tCYC
tCH
Description
Clock Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit
4.0
1.7
1.7
1.2
0.3
4.4
2.0
2.0
1.4
0.4
5
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock HIGH
2.0
2.0
1.4
0.4
2.2
2.2
1.5
0.5
tCL
Clock LOW
tAS
Address Set-up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWE, GW, BWx Set-up Before CLK Rise
BWE, GW, BWx Hold After CLK Rise
ADV Set-up Before CLK Rise
ADV Hold After CLK Rise
tAH
tCO
2.6
2.8
3.0
3.4
tDOH
tADS
tADH
tWES
tWEH
tADVS
tADVH
tDS
1.0
1.2
0.3
1.2
0.3
1.2
0.3
1.2
0.3
1.2
0.3
1.0
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.3
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
Data Input Set-up Before CLK Rise
Data Input Hold After CLK Rise
Chip Enable Set-up
tDH
tCES
tCEH
tCHZ
tCLZ
Chip Enable Hold After CLK Rise
Clock to High-Z[16]
Clock to Low-Z[16]
OE HIGH to Output High-Z[16, 17]
OE LOW to Output Low-Z[16, 17]
OE LOW to Output Valid[16]
2.6
2.6
2.6
2.8
2.8
2.8
3.0
3.0
3.0
3.4
3.4
3.4
1.0
0
1.0
0
1.3
0
1.3
0
tEOHZ
tEOLZ
tEOV
Shaded areas contain preliminary information.
Notes:
15. Unless otherwise noted, test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
16. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-
state voltage.
17. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ
.
Document #: 38-05240 Rev. *A
Page 22 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
1
Switching Waveforms
Write Cycle Timing[4, 18, 19, 20]
Single Write
tCYC
tADH
Burst Write
tCH
Pipelined Write
Unselected
CLK
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADH
tADS
ADSC initiated write
tADVH
tADVS
tAS
ADV Must Be Inactive for ADSP Write
WD3
ADD
GW
WE
CE1
WD1
WD2
tAH
tWH
tWH
tWS
tWS
tCES
tCEH
CE1 masks ADSP
tCEH
tCES
Unselected with CE2
CE2
CE3
OE
tCES
tCEH
tDH
tDS
High-Z
High-Z
Data
In
3a
2a
1a
2b
2c
2d
= DON’T CARE
= UNDEFINED
Notes:
18. WE is the combination of BWE and BWx to define a write cycle (see Write Cycle Descriptions table).
19. WDx stands for Write Data to Address X.
20. Device originally deselected.
Document #: 38-05240 Rev. *A
Page 23 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Switching Waveforms (continued)
Read Cycle Timing[4, 18, 20, 21]
Burst Read
Single Read
tCYC
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
ADSP
tCL
ADSP ignored with CE1 inactive
tADS
ADSC initiated read
ADSC
ADV
tADVS
tADH
Suspend Burst
tADVH
tAS
ADD
GW
RD1
RD3
RD2
tAH
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
OE
tCES
tEOV
tCEH
tOEHZ
tDOH
tCO
Data Out
2c
1a
2d
3a
2a
2b
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
21. RDx stands for Read Data from Address X.
Document #: 38-05240 Rev. *A
Page 24 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[4, 18, 19, 20, 21]
Single cycle
deselect
Single Write
Single Read
tCYC
Single Write
tCH
Burst Read
Pipelined Read
CLK
tADS
tADH
tCL
ADSP
ADSC
ADV
tADVS
tAS
tADVH
WD2
ADD
RD1
RD4
WD3
RD5
tAH
GW
WE
tWS
tWS
tWH
tCES
tWH
tCEH
CE1 Unselected
CE1
CE2
CE3
tCES
tCEH
tEOV
tCES
tCEH
OE
tEOHZ
tDS
tDH
tDOH
tEOLZ
tCO
4b
Out
4c
Out
4a
Out
4d
Out
Data In/Out
1a
2a
In
3a
In
Out
tCHZ
= UNDEFINED
= DON’T CARE
I/O Disabled within one clock
cycle after deselect
Document #: 38-05240 Rev. *A
Page 25 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read/Write Timing[4, 18, 19, 20, 21]
Selected
Unselected
ADSC read
ADSP read
ADSC write
ADSP write
CLK
ADSP
ADSC
ADV
ADD
GW
RD1
RD2
RD3
RD4
WD6
WD8
WD5
WD7
WE
CE1
CE2
CE3
OE
4a
Out
6a
In
3a
Out
5a
In
7a
In
Data In/Out
1a
2a
Out
Out
= UNDEFINED
= DON’T CARE
Document #: 38-05240 Rev. *A
Page 26 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Switching Waveforms (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
Three-State
tEOLZ
I/Os
Document #: 38-05240 Rev. *A
Page 27 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Switching Waveforms (continued)
ZZ Mode Timing [4, 22, 23]
CLK
ADSP
HIGH
ADSC
CE1
LOW
HIGH
CE2
CE3
ZZ
tZZS
IDD
IDD(active)
tZZREC
IDDZZ
I/Os
Three-state
Notes:
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
23. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05240 Rev. *A
Page 28 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
250
CY7C1382CV25-250AC
CY7C1380CV25-250AC
A101
BG119
BB165A
A101
100-Lead Thin Quad Flat Pack
Commercial
CY7C1382CV25-250BGC
CY7C1380CV25-250BGC
119 PBGA
CY7C1382CV25-250BZC
CY7C1380CV25-250BZC
165 FBGA
225
200
167
225
200
167
CY7C1382CV25-225AC
CY7C1380CV25-225AC
100-Lead Thin Quad Flat Pack
119 PBGA
CY7C1382CV25-225BGC
CY7C1380CV25-225BGC
BG119
BB165A
A101
CY7C1382CV25-225BZC
CY7C1380CV25-225BZC
165 FBGA
CY7C1382CV25-200AC
CY7C1380CV25-200AC
100-Lead Thin Quad Flat Pack
119 PBGA
CY7C1382CV25-200BGC
CY7C1380CV25-200BGC
BG119
BB165A
A101
CY7C1382CV25-200BZC
CY7C1380CV25-200BZC
165 FBGA
CY7C1382CV25-167AC
CY7C1380CV25-167AC
100-Lead Thin Quad Flat Pack
119 PBGA
CY7C1382CV25-167BGC
CY7C1380CV25-167BGC
BG119
BB165A
A101
CY7C1382CV25-167BZC
CY7C1380CV25-167BZC
165 FBGA
CY7C1382CV25-225AI
CY7C1380CV25-225AI
100-Lead Thin Quad Flat Pack
119 PBGA
Industrial
CY7C1382CV25-225BGI
CY7C1380CV25-225BGI
BG119
BB165A
A101
CY7C1382CV25-225BZI
CY7C1380CV25-225BZC
165 FBGA
CY7C1382CV25-200AI
CY7C1380CV25-200AI
100-Lead Thin Quad Flat Pack
119 PBGA
CY7C1382CV25-200BGI
CY7C1380CV25-200BGI
BG119
BB165A
A101
CY7C1382CV25-200BZI
CY7C1380CV25-200BZI
165 FBGA
CY7C1382CV25-167AI
CY7C1380CV25-167AI
100-Lead Thin Quad Flat Pack
119 PBGA
CY7C1382CV25-167BGI
CY7C1380CV25-167BGI
BG119
BB165A
CY7C1382CV25-167BZI
CY7C1380CV25-167BZI
165 FBGA
Shaded areas contain advance information and parts that may not be offered.
Document #: 38-05240 Rev. *A
Page 29 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05240 Rev. *A
Page 30 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
Document #: 38-05240 Rev. *A
Page 31 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
may be trademarks of their respective holders.
Document #: 38-05240 Rev. *A
Page 32 of 33
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Document History Page
Document Title: CY7C1380CV25/CY7C1382CV25 512K x 36/1M x 18 Pipelined SRAM
Document Number: 38-05240
Issue
Date
Orig. of
Change
Rev.
**
ECN No.
116280
121543
Description of Change
08/29/02
11/21/02
SKX
DSG
New Data Sheet
*A
Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122
(BB165A) to rev. *C
Document #: 38-05240 Rev. *A
Page 33 of 33
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