CY7C1381B-83BZC [CYPRESS]
512 】 36/1M 】 18 Flow-Thru SRAM; 512 × 36 / 1M × 18流流通SRAM
| 型号： | CY7C1381B-83BZC |
| 厂家： | 
CYPRESS |
| 描述： | 512 】 36/1M 】 18 Flow-Thru SRAM |
| 文件： | 总31页 (文件大小：599K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
381B
CY7C1381B
CY7C1383B
512 × 36/1M × 18 Flow-Thru SRAM
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), Burst Control
Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
BWc, BWd, and BWe), and Global Write (GW).
Features
• Fast access times: 7.5, 8.5, 10.0 ns
• Fast clock speed: 117, 100, 83 MHz
• Provide high-performance 3-1-1-1 access rate
• Optimal for depth expansion
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
• 3.3V (–5% / +10%) power supply
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data and control registers
• Internally self-timed Write Cycle
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or address status controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
• Burst control pins (interleaved or linear burst
Address, data inputs, and Write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
sequence)
• Automatic power down available using ZZ mode or CE
deselect
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
four bytes wide as controlled by the Write control inputs.
Individual byte Write allows individual byte to be written. BWa
controls DQ1-DQ8 and DP1. BWb controls DQ9-DQ16 and
DP2. BWc controls DQ17-DQ24and DP3. BWd controls
DQ25-DQ32 and DP4. BWa, BWb BWc, and BWd can be
active only with BWe being LOW. GW being LOW causes all
bytes to be written. Write pass-through capability allows
written data available at the output for the immediately next
Read cycle. This device also incorporates pipelined enable
circuit for easy depth expansion without penalizing system
performance.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced
single-layer polysilicon, triple-layer metal technology. Each
memory cell consists of six transistors.
The CY7C1381B and CY7C1383B SRAMs integrate
524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for
All inputs and outputs of the CY7C1381B and the CY7C1383B
are JEDEC-standard JESD8-5-compatible.
Selection Guide
117 MHz
100 MHz
8.5
83 MHz
10.0
185
Unit
ns
Maximum Access Time
7.5
250
20
Maximum Operating Current
Maximum CMOS Standby Current
225
mA
mA
20
20
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05196 Rev. **
Revised December 3, 2001
CY7C1381B
CY7C1383B
Functional Block Diagram
Logic Block Diagram ×18
MODE
2
(A ,A )
0
1
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
Q1
Q
CLR
ADSP
18
20
ADDRESS
REGISTER
CE
D
1M × 18
A
[19:0]
20
18
MEMORY
ARRAY
GW
DQb[15:8],DP1
D
Q
Q
BYTEWRITE
BWE
REGISTERS
BWS
b
D DQa[7:0],DP0
BYTEWRITE
REGISTERS
BWS
a
18
18
CE
CE
CE
1
2
3
D
CE
ENABLE
Q
REGISTER
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
DP
[15:0]
[1:0]
Logic Block Diagram ×36
MODE
2
(A ,A )
0
1
Q
CLK
ADV
ADSC
0
Q1
Q
BURST
COUNTER
CE
CLR
ADSP
17
19
ADDRESS
REGISTER
CE
D
512K × 36
A
[18:0]
19
17
MEMORY
ARRAY
GW
DQd[31:24],DP3
D
D
Q
BYTEWRITE
REGISTERS
BWE
BWS
d
DQc[23:16],DP2
Q
BYTEWRITE
REGISTERS
BWS
BWS
c
D
D
DQb[15:8],DP1
Q
BYTEWRITE
REGISTERS
b
DQa[7:0],DP0Q
BWS
BYTEWRITE
a
REGISTERS
36
36
CE
CE
CE
1
2
3
D
ENABLE
Q
CE REGISTER
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
DP
[31:0]
[3:0]
Document #: 38-05196 Rev. **
Page 2 of 31
CY7C1381B
CY7C1383B
Pin Configurations
100-pin TQFP
NC
NC
NC
VDDQ
VSSQ
NC
DPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DPd
A
NC
NC
VDDQ
VSSQ
NC
DPa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
NC
VSSQ
VDDQ
NC
NC
NC
1
80
DPb
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
79
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
2
3
78
3
4
77
4
5
76
5
6
75
6
NC
7
74
7
DQb
DQb
VSSQ
VDDQ
DQb
DQb
NC
8
73
8
9
72
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
71
10
70
11
69
12
68
13
67
14
CY7C1383B
(1M × 18)
CY7C1381B
(512K × 36)
VDD
NC
66
NC
VDD
ZZ
15
65
16
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DPb
NC
VSSQ
VDDQ
NC
NC
NC
64
17
63
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
DPa
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
Document #: 38-05196 Rev. **
Page 3 of 31
CY7C1381B
CY7C1383B
Pin Configurations (continued)
119-ball BGA
CY7C1381B (512K × 36)
2
A
1
3
A
4
5
A
6
A
7
A
B
C
D
E
F
VDDQ
VDDQ
NC
ADSP
NC
NC
A
A
A
A
ADSC
VDD
A
A
A
A
NC
DQc
DQc
VDDQ
DQPc
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPb
DQb
DQb
DQb
DQb
VDDQ
CE1
OE
G
H
J
DQc
DQc
VDDQ
DQc
DQc
VDD
DQb
DQb
VDD
DQb
DQb
VDDQ
BWc
VSS
NC
ADV
BWb
VSS
NC
GW
VDD
K
L
DQd
DQd
DQd
DQd
DQd
VSS
CLK
NC
VSS
DQa
DQa
DQa
DQa
DQa
BWd
VSS
BWa
VSS
M
VDDQ
VDDQ
BWE
A1
N
P
R
T
DQd
DQd
NC
DQd
VSS
VSS
MODE
A
VSS
VSS
NC
A
DQa
DQPa
A
DQa
DQa
NC
DQPd
A0
VDD
A
A
NC
64M
32M
NC
ZZ
VDDQ
TMS
TDI
TCK
TDO
VDDQ
U
CY7C1383B (1M × 18)
2
A
1
3
A
4
5
A
6
A
7
VDDQ
NC
VDDQ
NC
A
B
C
D
E
F
ADSP
ADSC
VDD
A
A
A
A
NC
A
A
A
A
NC
DQb
NC
NC
DQb
NC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPa
NC
DQa
NC
DQa
VDDQ
CE1
OE
VDDQ
G
H
J
NC
DQb
VDDQ
NC
DQb
NC
VSS
VSS
NC
NC
DQb
VDD
NC
DQa
NC
BWb
VSS
NC
ADV
GW
VDD
VDD
DQb
NC
VDDQ
DQa
NC
VSS
VSS
VSS
VSS
VSS
CLK
NC
VSS
K
L
DQb
DQa
BWa
VSS
M
VDDQ
DQb
NC
DQb
NC
NC
DQa
NC
VDDQ
NC
BWE
A1
N
P
VSS
VSS
DQPb
A0
DQa
R
T
NC
64M
VDDQ
A
A
MODE
A
VDD
32M
TCK
NC
A
A
A
NC
ZZ
TMS
TDI
TDO
NC
VDDQ
U
Document #: 38-05196 Rev. **
Page 4 of 31
CY7C1381B
CY7C1383B
Pin Configurations (continued)
165-ball Bump FBGA
CY7C1381B (512K × 36) – 11 × 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWc
BWb
CE
BWE
A
ADSC
ADV
A
NC
1
2
3
NC
DPc
DQc
A
CE
BWd
BWa
CLK
GW
B
C
D
E
F
OE
ADSP
A
128M
DPb
NC
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DQc
V
V
V
V
V
V
DQb
DQb
DD
SS
SS
SS
DD
DDQ
DQc
DQc
DQc
NC
DQc
DQc
DQc
V
V
V
V
V
V
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
G
H
J
V
V
DD
SS
SS
SS
DD
DDQ
V
NC
V
V
V
V
V
NC
SS
DD
SS
SS
SS
DD
DQd
DQd
DQd
DQd
DPd
NC
DQd
DQd
DQd
DQd
NC
V
V
V
V
V
V
V
DQa
DQa
DQa
DQa
NC
DQa
DQa
DQa
DQa
DPa
A
DDQ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
V
V
K
L
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
M
N
P
V
V
DD
SS
SS
SS
DD
DDQ
V
NC
TDI
A
NC
V
V
DDQ
SS
SS
DDQ
64M
A
A
A
A1
A0
TDO
TCK
A
A
A
A
A
MODE
32M
A
TMS
R
A
A
CY7C1383B (1M × 18) – 11 × 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWb
NC
CE
BWE
A
ADSC
ADV
A
A
1
2
3
NC
NC
NC
A
CE
NC
BWa
CLK
GW
B
C
D
E
F
OE
ADSP
A
128M
DPa
NC
V
V
V
V
V
V
V
V
V
V
V
NC
NC
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DQb
DQb
DQb
DQb
V
V
V
V
V
V
DQa
DD
SS
SS
SS
DD
DDQ
NC
NC
V
V
V
V
V
V
NC
NC
DQa
DQa
DQa
ZZ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
NC
V
V
V
V
G
H
J
V
V
NC
DD
SS
SS
SS
DD
DDQ
NC
V
NC
V
V
V
V
V
NC
NC
SS
DD
SS
SS
SS
DD
DQb
DQb
DQb
DQb
DPb
NC
NC
NC
NC
NC
NC
64M
V
V
V
V
V
V
V
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
NC
A
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
V
V
K
L
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
M
N
P
V
V
DDQ
DD
SS
SS
SS
DD
DDQ
V
NC
TDI
A
NC
V
V
DDQ
SS
SS
DDQ
A
A
A
A1
A0
TDO
TCK
A
A
A
A
A
MODE
32M
A
TMS
R
A
A
Document #: 38-05196 Rev. **
Page 5 of 31
CY7C1381B
CY7C1383B
Pin Definitions
Name
I/O
Description
A0
A1
A
Input-
Synchronous
Address inputs used to select one of the address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2,
and CE3 are sampled active. A[1:0] feed the two-bit counter.
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write Select inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable input, active LOW. When asserted LOW on the rising
edge of CLK, a global Write is conducted (ALL bytes are written, regardless
of the values on BWa,b,c,d and BWE).
BWE
CLK
Input-
Synchronous
Byte Write Enable input, active LOW. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte Write.
Input-Clock
Clock input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
CE1
Input-
Synchronous
Chip Enable 1 input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE2 and CE3 to select/deselect the device. ADSP is
ignored if CE1 is HIGH.
CE2
CE3
OE
Input-
Synchronous
Chip Enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE3 to select/deselect the device (TQFP only).
Input-
Synchronous
Chip Enable 3 input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE2 to select/deselect the device (TQFP only) .
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of
the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the first clock of a Read cycle when emerging from a deselected state.
ADV
Input-
Advance input signal, sampled on the rising edge of CLK. When asserted,
Synchronous
it automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK.
When asserted LOW, A is captured in the address registers. A[1:0] are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK.
When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
MODE
ZZ
Input-
Static
Selects burst order. When tied to GND selects linear burst sequence. When
tied to VDDQ or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation.
Input-
Asynchronous
ZZ “sleep” input. This active HIGH input places the device in a
non-time-critical “sleep” condition with data integrity preserved.
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
I/O-
Synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A[X]during the previous clock
rise of the Read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQa–DQd and
DPa–DPd are placed in a three-state condition. DQ a,b,c and d are eight-bits
wide. DP a,b,c and d are one-bit wide.
TDO
TDI
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of
TCK (BGA only).
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA
only).
Document #: 38-05196 Rev. **
Page 6 of 31
CY7C1381B
CY7C1383B
Pin Definitions (continued)
Name
I/O
Description
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port (TAP) state machine. Sampled on the
rising edge of TCK (BGA only).
TCK
VDD
JTAG Serial Clock
Power Supply
Serial clock to the JTAG circuit (BGA only).
Power supply inputs to thecore of the device. Should be connected to3.3V
–5% +10% power supply.
VSS
Ground
Ground for the core of the device. Should be connected to ground of the
system.
VDDQ
VSSQ
NC
I/O Power Supply
Power supply for the I/O circuitry.
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
No connects. Pins are not internally connected.
–
–
32M
64M
128M
No connects. Reserved for address expansion. Pins are not internally
connected.
Document #: 38-05196 Rev. **
Page 7 of 31
CY7C1381B
CY7C1383B
bytes are written. Bytes not selected during a byte Write
operation will remain unaltered. All I/Os are three-stated
during a byte Write because the CY7C1381B/CY7C1383B is
a common I/O device, the OE must be deasserted HIGH
before presenting data to the DQx inputs. Doing so will
three-state the output drivers. As a safety precaution, DQx are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
Functional Description
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
and (2) Chip Enable (CE1, CE2, CE3 on TQFP, CE1 on BGA)
is asserted active, and (3) the Write signals (GW, BWE) are all
deasserted HIGH. ADSP is ignored if CE1 is HIGH. The
address presented to the address inputs is stored into the
address advancement logic and the Address Register while
being presented to the memory core. If the OE input is
asserted LOW, the requested data will be available at the data
outputs a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
Burst Sequences
The CY7C1381B/CY7C1383B provides a two-bit wraparound
counter fed by A[1:0] that implements either an interleaved or
linear burst sequence to support processors that follow a linear
burst sequence. The burst sequence is user-selectable
through MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) Chip Enable is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
Write signals (GW, BWE, and BWx) and ADV inputs are
ignored during this first clock cycle. If the Write inputs are
asserted active (see Write Cycle Descriptions table on page
10 for appropriate states that indicate a Write) on the next
clock rise, the appropriate data will be latched and written into
the device. The CY7C1381B/CY7C1383B provides byte Write
capability that is described in the Write Cycle Description
table. Asserting the Byte Write Enable (BWE) input with the
selected Byte Write (BWa,b,c,d for CY7C1381B and BWa,b for
CY7C1383B) input will selectively Write to only the desired
bytes. Bytes not selected during a byte Write operation will
remain unaltered. All I/Os are three-stated during a byte Write.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Because the CY7C1381B/CY7C1383B is a common I/O
device, the OE must be deasserted HIGH before presenting
data to the DQx inputs. Doing so will three-state the output
drivers. As a safety precaution, DQx are automatically
three-stated whenever a Write cycle is detected, regardless of
the state of OE.
A[1:0]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
01
10
11
00
10
11
00
01
Single Write Accesses Initiated by ADSC
11
00
01
10
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) Chip Enable (CE1, CE2, CE3 on TQFP,
CE1 on BGA) is asserted active, and (4) the appropriate
combination of the Write inputs (GW, BWE, and BWx) is
asserted active to conduct a Write to the desired byte(s).
ADSC is ignored if ADSP is active LOW.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. Chip Enable (CE1, CE2, CE3, on TQFP, CE1
on BGA), ADSP and ADSC must remain inactive for the
duration of tZZREC after the ZZ input returns LOW. Leaving ZZ
unconnected defaults the device into an active state.
The address presented to A[17:0] is loaded into the address
register and the address advancement logic while being
delivered to the RAM core. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
the DQx is written into the corresponding address location in
the RAM core. If a byte Write is conducted, only the selected
Document #: 38-05196 Rev. **
Page 8 of 31
CY7C1381B
CY7C1383B
ZZ Mode Electrical Characteristics
Parameter
ICCZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ < VDD – 0.2V
ZZ < VDD – 0.2V
ZZ ≤ 0.2V
Min.
Max.
20
Unit
mA
ns
tZZS
2tCYC
tZZREC
2tCYC
ns
Cycle Descriptions[1, 2, 3]
Next Cycle
Unselected
Add. Used
None
ZZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
CE3
X
1
CE2
CE1
1
ADSP
ADSC
ADV
X
X
X
X
X
X
X
0
OE
X
X
X
X
X
X
X
1
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Write
X
X
X
0
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
X
1
1
X
1
X
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
X
Unselected
None
0
X
Unselected
None
X
1
0
X
Unselected
None
X
0
0
X
Unselected
None
X
0
0
X
Begin Read
External
External
Next
1
0
X
Begin Read
0
1
0
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
1
X
X
1
Next
0
0
Next
0
1
Hi-Z
DQ
Next
1
0
0
Current
Current
Current
Current
Current
Current
External
Next
X
X
1
1
1
Hi-Z
DQ
1
0
1
1
Hi-Z
DQ
1
1
0
X
1
1
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Begin Write
1
Begin Write
0
X
0
Continue Write
Continue Write
Suspend Write
Suspend Write
X
X
X
X
X
X
X
X
X
X
X
1
Next
0
Current
Current
None
X
1
1
1
ZZ “sleep”
X
X
Note:
1. X = ”Don't Care”, 1 = HIGH, 0 = LOW.
2. The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state.
OE is a “Don't Care” for the remainder of the Write cycle.
3. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle, DQ = High-Z when OE is inactive
or when the device is deselected, and DQ = data when OE is active.
Document #: 38-05196 Rev. **
Page 9 of 31
CY7C1381B
CY7C1383B
Write Cycle Description[1, 2, 3]
Function (CY7C1381B)
Read
GW
1
BWE
1
BWd
X
1
BWc
X
1
BWb
BWa
X
1
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
Read
1
0
Write Byte 0 – DQa
Write Byte 1 – DQb
Write Bytes 1, 0
Write Byte 2 – DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 – DQd
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
1
0
1
1
0
1
0
1
1
1
1
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
0
0
0
1
1
0
0
0
0
1
0
0
0
1
1
0
0
0
0
Write All Bytes
0
X
X
X
X
Function (CY7C1383B)
Read
GW
BWE
BWb
BWa
1
1
1
1
1
0
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
Read
Write Byte 0 – DQa and DPa
Write Byte 1 – DQb and DPb
Write All Bytes
Write All Bytes
Document #: 38-05196 Rev. **
Page 10 of 31
CY7C1381B
CY7C1383B
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1381B/CY7C1383B incorporates a serial boundary
scan TAP in the FBGA package only. The TQFP package does
not offer this functionality. This port operates in accordance
with IEEE Standard 1149.1–1900, but does not have the set
of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because
their inclusion places an added delay in the critical speed path
of the SRAM. Note that the TAP controller functions in a
manner that does not conflict with the operation of other
devices using 1149.1 fully compliant TAPs. The TAP operates
using JEDEC standard 3.3V I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01" pattern to
allow for fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller , TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port – Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The ×36 configuration has a 70-bit-long
register, and the ×18 configuration has a 51-bit-long register.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the I/O ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The e output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the least significant bit (LSB) of any
register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data or control signals into the
SRAM and cannot preload the I/O buffers. The SRAM does
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
Document #: 38-05196 Rev. **
Page 11 of 31
CY7C1381B
CY7C1383B
not implement the 1149.1 commands EXTEST or INTEST or
the PRELOAD portion of SAMPLE/PRELOAD; rather it
performs a capture of the I/O ring when these instructions are
executed.
When the SAMPLE/PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (TCS and TCH). The SRAM clock input might not
be captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
Bypass
SAMPLE Z
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05196 Rev. **
Page 12 of 31
CY7C1381B
CY7C1383B
TAP Controller State Diagram
TEST-LOGIC
1
RESET
1
1
1
TEST-LOGIC/
IDLE
SELECT
SELECT
IR-SCAN
0
DR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
1
UPDATE-IR
1
0
0
Note:
4. Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05196 Rev. **
Page 13 of 31
CY7C1381B
CY7C1383B
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
0
TDO
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
2
1
1
0
0
.
x
.
.
.
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[5, 6]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
Description
Test Conditions
Min.
2.4
Max.
Unit
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOH = −4.0 mA
IOH = −100 µA
IOL = 8.0 mA
IOL = 100 µA
VDD – 0.2
V
0.4
0.2
V
V
1.7
−0.5
−5
V
DD + 0.3
V
VIL
0.7
V
IX
GND ≤ VI ≤ VDDQ
5
µA
5. All voltage referenced to Ground.
6. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC / 2; undershoot: VIL (AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t <
200 ms.
Document #: 38-05196 Rev. **
Page 14 of 31
CY7C1381B
CY7C1383B
TAP AC Switching Characteristics Over the Operating Range[7, 8]
Parameters
tTCYC
Description
Min.
Max
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
tTF
10
MHz
ns
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock HIGH to TDO Invalid
20
ns
ns
tTDOX
0
Notes:
7. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
8. Test conditions are specified using the load in TAP AC test conditions. Tr / Tf = 1 ns.
Document #: 38-05196 Rev. **
Page 15 of 31
CY7C1381B
CY7C1383B
TAP Timing and Test Conditions
1.25V
50Ω
ALL INPUT PULSES
1.50V
TDO
3.3V
Z = 50Ω
0
C = 20 pF
L
0V
GND
(a)
t
TL
t
TH
Test Clock
TCK
t
TCYC
t
TMSS
t
TMSH
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data-In
TDI
Test Data-Out
TDO
t
t
TDOV
TDOX
Document #: 38-05196 Rev. **
Page 16 of 31
CY7C1381B
CY7C1383B
Identification Register Definitions
Instruction Field
Revision Number (31:28)
Device Depth (27:23)
512K × 36
1M × 18
xxxx
Description
xxxx
00111
Reserved for version number.
01000
00011
Defines depth of SRAM. 512K or 1M
Defines with of the SRAM. ×36 or ×18
Reserved for future use.
Device Width (22:18)
00100
Cypress Device ID (17:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
xxxxx
xxxxx
00011100100
1
00011100100
1
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bit Size (×18)
Bit Size (×36)
3
1
3
1
Bypass
ID
32
51
32
70
Boundary Scan
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the I/O ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1-compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
Captures the I/O contents. Placesthe boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the I/O ring contents. Places the boundary scan register be-
tween TDI and TDO. Does not affect the SRAM operation. This instruction
does not implement 1149.1 preload function and is therefore not
1149.1-compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use. This instruction is reserved for future use.
Do Not Use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does
not affect SRAM operation.
Document #: 38-05196 Rev. **
Page 17 of 31
CY7C1381B
CY7C1383B
Boundary Scan Order (512K × 18)
Boundary Scan Order (1M × 18)
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Bit #
Bit #
36
Bit #
Bit #
36
1
A
2R
A
6B
1
A
2R
DQb
2E
2
A
3T
4T
5T
6R
3B
5B
6P
7N
6M
7L
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
BWa#
BWb#
BWc#
BWd#
A
5L
2
A
2T
3T
5T
6R
3B
5B
7P
6N
6L
7K
7T
6H
7G
6F
7E
6D
6T
6A
5A
4G
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
DQb
DQb
NC
2G
1H
5R
2K
1L
3
A
5G
3G
3L
3
A
4
A
4
A
5
A
5
A
DQb
DQb
DQb
DQb
DQb
MODE
A
6
A
2B
4E
3A
2A
2D
1E
2F
1G
1D
1D
2E
2G
1H
5R
2K
1L
6
A
7
A
CE#
A
7
A
2M
1N
2P
3R
2C
3C
5C
6C
4N
4P
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
8
DQa
DQa
DQa
DQa
ZZ
9
A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
6K
7P
6N
6L
A
DQa
DQa
DQa
DQa
DQa
A
A
A
A1
7K
7T
6H
7G
6F
7E
6D
7H
6G
6E
7D
6A
5A
4G
A0
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
A
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
A
ADV#
2M
1N
2P
1K
2L
ADSP# 4A
ADSC# 4B
OE#
BWE#
GW#
CLK
A
4F
4M
4H
4K
6B
5L
2N
1P
3R
2C
3C
5C
6C
4N
4P
A
ADV#
BWa#
BWb#
A
ADSP# 4A
ADSC# 4B
3G
2B
4E
3A
2A
1D
A
OE#
4F
4M
4H
4K
A
CE#
A
BWE#
GW#
CLK
A
A1
A
A0
DQb
Document #: 38-05196 Rev. **
Page 18 of 31
CY7C1381B
CY7C1383B
Static Discharge Voltage .......................................... >1500V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Operating Range
Storage Temperature ..................................... −55°C to +150°C
Ambient Temperature with
Ambient
Power Applied.................................................. −55°C to +125°C
Range
Commercial
Industrial
Temp[10]
VDD
VDDQ
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
0°C to +70°C
–40°C to +85°C
3.3V
2.5V – 5%
DC Voltage Applied to Outputs
in High Z State[9])................................ −0.5V to VDDQ + 0.5V
–5% / +10% 3.3V + 10%
DC Input Voltage[9]..................................−0.5V to VDDQ + 0.5V
Current into Outputs (LOW).........................................20 mA
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Test Conditions
Min.
3.135
2.375
2.0
Max.
3.63
3.63
Unit
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
VDDQ
V
VOH
VDD = Min., IOH = –1.0 mA
VDDQ = 2.5V
V
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 1.0 mA
VDD = Min., IOL = 8.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 3.3 V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
2.4
V
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
0.4
0.4
V
V
2
V
1.7
V
–0.3
–0.3
0.8
0.7
5
V
V
Input Load Current
Input Current of MODE
Input Current of ZZ
GND < VI < VDDQ
Input = VSS
µA
µA
µA
µA
–30
–30
30
30
5
IOZ
IDD
Output Leakage
Current
GND < VI < VDDQ, Output Disabled
VDD Operating Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
8.5-ns cycle, 117 MHz
250
225
185
100
90
mA
mA
mA
mA
mA
mA
mA
10-ns cycle, 100 MHz
12-ns cycle, 83 MHz
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
12-ns cycle, 83 MHz
All speed grades
ISB1
ISB2
ISB3
Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device
Deselected,
VIN > VIH or VIN < VIL
f = fMAX = 1/tCYC
75
Automatic CE
Power-Down
Max. VDD, Device
Deselected, VIN < 0.3V or VIN
Current—CMOS Inputs > VDDQ – 0.3V,
20
f = 0
Automatic CE
Power-Down
Max. VDD, Device
Deselected, or VIN < 0.3V or
Current—CMOS Inputs VIN > VDDQ – 0.3V
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
12-ns cycle, 83 MHz
All speeds
90
75
60
50
mA
mA
mA
mA
f = fMAX = 1/tCYC
ISB4
Automatic CS
Power-Down
Max. VDD, Device
Deselected,
Current—TTL Inputs
VIN > VIH or VIN < VIL, f = 0
Notes:
9. Minimum Voltage equals -2.0V for pulse duration of less than 20ns.
10. TA is the case temperature.
Document #: 38-05196 Rev. **
Page 19 of 31
CY7C1381B
CY7C1383B
Capacitance[11]
Parameter
Description
Input Capacitance
Test Conditions
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
DD = 3.3V,
DDQ = 3.3V
3
3
3
V
V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
AC Test Loads and Waveforms
R = 1667Ω
V
[12]
DDQ
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
V
DD
90%
10%
Z = 50Ω
0
R = 50Ω
L
10%
5 pF
GND
R = 1538Ω
< 1 V/ns
< 1V/ns
= 1.25V
VTH
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Thermal Resistance[11]
QJA
QJC
Description
Test Conditions
Units
°C/W
°C/W
°C/W
(Junction to Ambient)
(Junction to Case)
119 BGA
Still Air, soldered on a 114.3 × 101.6 × 1.57 mm3,
41.54
44.51
25
6.33
2.38
9
2-layer board
165 FBGA
100-pin TQFP
Still Air, soldered on a 4.25 × 1.125 inch, 4-layer
printed circuit board
Notes:
11. Tested initially and after any design or process changes that may affect these parameters.
12. Input waveform should have a slew rate of 1 V/ns.
Document #: 38-05196 Rev. **
Page 20 of 31
CY7C1381B
CY7C1383B
Switching Characteristics Over the Operating Range[13, 14, 15]
–117
–100
–83
Max.
Parameter
tCYC
Description
Min.
Max.
Min.
Max.
Min.
12.0
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
Clock HIGH
8.5
2.3
2.3
1.5
0.5
10.0
2.5
2.5
1.5
0.5
tCH
tCL
Clock LOW
3.0
tAS
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWE, GW, BWx Set-Up Before CLK Rise
BWE, GW, BWx Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
1.5
tAH
0.5
tCO
7.5
8.5
10.0
tDOH
tADS
tADH
tWES
tWEH
tADVS
tADVH
tDS
1.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip enable Set-Up
tDH
tCES
tCEH
tCHZ
tCLZ
tEOHZ
tEOLZ
Chip enable Hold After CLK Rise
Clock to High-Z[13]
Clock to Low-Z[13]
OE HIGH to Output High-Z[13, 14]
OE LOW to Output Low-Z[13, 14]
OE LOW to Output Valid[13]
3.0
4.0
3.4
3.0
4.0
3.8
3.0
4.0
4.2
1.3
0
1.3
0
1.3
0
tEOV
Notes:
13. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
14.
tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
15. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ
.
Document #: 38-05196 Rev. **
Page 21 of 31
CY7C1381B
CY7C1383B
1
Switching Waveforms
Write Cycle Timing[16, 17]
Single Write
Burst Write
Pipelined Write
Unselected
t
CH
t
CYC
CLK
t
ADH
t
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
ADSC
ADV
t
ADH
t
ADSC initiated Write
ADS
t
t
ADVH
ADVS
t
ADV must be inactive for ADSP Write
WD2
AS
WD3
ADD
GW
WD1
t
AH
t
WH
t
WH
t
WS
t
WS
BWE
t
t
CES
CEH
CE masks ADSP
1
CE
1
t
t
CEH
CES
Unselected with CE
2
CE
2
3
CE
t
CES
t
CEH
OE
t
DH
t
DS
High-Z
3a
High-Z
Data-In
2a
= Undefined
2d
1a
2b
2c
Don’t Care
Notes:
16. WE is the combination of BWE, BWx, and GW to define a Write cycle (see Write Cycle Descriptions table).
17. WDx stands for Write Data to Address X.
Document #: 38-05196 Rev. **
Page 22 of 31
CY7C1381B
CY7C1383B
Switching Waveforms (continued)
Read Cycle Timing[16, 18]
Burst Read
Single Read
Unselected
t
CH
t
CYC
Pipelined Read
CLK
t
t
ADH
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
t
ADS
ADSC initiated Read
ADSC
ADV
t
ADVS
t
ADH
Suspend Burst
t
t
ADVH
AS
ADD
GW
RD1
RD3
RD2
t
AH
t
WS
t
WS
t
WH
BWE
t
t
CEH
CES
t
CE masks ADSP
WH
1
CE
1
2
Unselected with CE
2
CE
t
CES
t
CEH
CE
3
t
t
CEH
CES
OE
t
EOV
t
OEHZ
t
DOH
t
CDV
3a
Data Out
2d
2a
2b
2c
1a
t
CLZ
t
CHZ
= Don’t Care
= Undefined
Note:
18. RDx stands for Read Data from Address X.
Document #: 38-05196 Rev. **
Page 23 of 31
CY7C1381B
CY7C1383B
Switching Waveforms (continued)
Read/Write Cycle Timing[16, 17, 18]
Read/Write Timing
t
t
t
CYC
CL
CH
CLK
t
AH
t
t
AS
A
D
B
C
ADD
t
ADH
ADS
ADSP
ADSC
ADV
t
t
ADH
ADS
t
t
ADVH
ADVS
t
CEH
t
CES
CE
1
t
t
CEH
CES
CE
t
t
WEH
WES
BWE
ADSP ignored
with CE HIGH
1
OE
t
EOHZ
tCLZ
Data
Q
(B+3)
D
D
D
Q
(B+2)
Q
(B+1)
Q(B)
Q(B)
D(C)
Q(D)
Q(A)
(C+1) (C+2) (C+3)
In/Out
t
CDV
tDOH
tCHZ
Device originally
deselected
WE is the combination of BWE, BWx, and GW to define a Write cycle (see Write cycle description table).
CE is the combination of CE and CE . All chip selects need to be active in order to select
2
3
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= Undefined
= Don’t Care
Document #: 38-05196 Rev. **
Page 24 of 31
CY7C1381B
CY7C1383B
Switching Waveforms (continued)
Back to Back Read/Write Timing[19, 20]
t
t
t
CYC
CL
CH
CLK
t
AS
WD1 WD2 WD3 WD4
RD1
RD2 RD3 RD4
ADD
t
t
ADS
ADH
ADSC initiated Reads
ADSC
ADSP
ADV
ADSP initiated Reads
t
t
CEH
CES
CE1
CE
t
t
WEH
WES
BWE
OE
ADSP ignored
with CE HIGH
1
t
CLZ
Data In/Out
1a
In
1a
Out
2a
Out
3a
Out
4a
Out
2a
In
3a
In
4a
In
t
CDV
t
DOH
Back-to-Back Reads
t
CHZ
Back-to-Back Writes
= Undefined
= Don’t Care
Notes:
19. Device originally deselected.
20. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
Document #: 38-05196 Rev. **
Page 25 of 31
CY7C1381B
CY7C1383B
Switching Waveforms (continued)
OE Switching Waveforms
OE
t
EOV
t
EOHZ
Three-State
I/Os
t
EOLZ
[19, 21]
ZZ Mode Timing
CLK
ADSP
ADSC
HIGH
CE
1
LOW
CE
CE
2
HIGH
3
ZZ
t
ZZS
I
CC
I
(active)
CC
t
ZZREC
I
CCZZ
I/Os
Three-state
Note:
21. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05196 Rev. **
Page 26 of 31
CY7C1381B
CY7C1383B
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
117
CY7C1381B-117AC
CY7C1383B-117AC
A101
BG119
BA165A
A101
100-Lead Thin Quad Flat Pack
Commercial
CY7C1381B-117BGC
CY7C1383B-117BGC
119 BGA
CY7C1381B-117BZC
CY7C1383B-117BZC
165 FBGA
100
CY7C1381B-100AC
CY7C1383B-100AC
100-Lead Thin Quad Flat Pack
119 BGA
CY7C1381B-100BGC
CY7C1383B-100BGC
BG119
BA165A
A101
CY7C1381B-100BZC
CY7C1383B-100BZC
165 FBGA
83
CY7C1381B-83AC
CY7C1383B-83AC
100-Lead Thin Quad Flat Pack
119 BGA
CY7C1381B-83BGC
CY7C1383B-83BGC
BG119
BA165A
A101
CY7C1381B-83BZC
CY7C1383B-83BZC
165 FBGA
100
CY7C1381B-100AI
CY7C1383B-100AI
100-Lead Thin Quad Flat Pack
119 BGA
Industrial
CY7C1381B-100BGI
CY7C1383B-100BGI
BG119
BA165A
A101
CY7C1381B-100BZI
CY7C1383B-100BZI
165 FBGA
83
CY7C1381B-83AI
CY7C1383B-83AI
100-Lead Thin Quad Flat Pack
119 BGA
CY7C1381B-83BGI
CY7C1383B-83BGI
BG119
BA165A
CY7C1381B-83BZI
CY7C1383B-83BZI
165 FBGA
Shaded areas contain advance information.
Document #: 38-05196 Rev. **
Page 27 of 31
CY7C1381B
CY7C1383B
Pin Configurations
100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101
Document #: 38-05196 Rev. **
Page 28 of 31
CY7C1381B
CY7C1383B
Pin Configurations (continued)
119-lead FBGA (14 × 22 × 2.4 mm) BG119
Document #: 38-05196 Rev. **
Page 29 of 31
CY7C1381B
CY7C1383B
Pin Configurations (continued)
165-ball FBGA (13 × 15 × 1.2 mm) BB165A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05196 Rev. **
Page 30 of 31
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1381B
CY7C1383B
Revision History
Document Title: CY7C1381B/CY7C1383B 512K x36/1M x18 Flow-Thru SRAM
Document Number: 38-05196
ISSUE
DATE
ORIG. OF
CHANGE
REV.
ECN NO.
DESCRIPTION OF CHANGE
**
112032
12/09/01
DSG
Change from Spec number: 38-01077 to 38-05196
Document #: 38-05196 Rev. **
Page 31 of 31
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