CY7C1381D-100BZIT [CYPRESS]
Standard SRAM, 512KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165;
| 型号： | CY7C1381D-100BZIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 512KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 静态存储器 |
| 文件： | 总37页 (文件大小：1103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1381D
CY7C1383D
CY7C1383F
18-Mbit (512 K × 36/1 M × 18)
Flow-Through SRAM
18-Mbit (512
K × 36/1 M × 18) Flow Through SRAM
Features
Functional Description
■ Supports 133 MHz bus operations
The CY7C1381D/CY7C1383D/CY7C1383F is
a
3.3 V,
512 K × 36 and 1 M × 18 synchronous flow through SRAMs,
designed to interface with high speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWx, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
■ 512 K × 36 and 1 M × 18 common I/O
■ 3.3 V core power supply (VDD
)
■ 2.5 V or 3.3 V I/O supply (VDDQ
)
■ Fast clock-to-output time
❐ 6.5 ns (133 MHz version)
■ Provides high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
The CY7C1381D/CY7C1383D/CY7C1383F allows interleaved
or linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be initiated
with the processor address strobe (ADSP) or the cache
controller address strobe (ADSC) inputs. Address advancement
is controlled by the address advancement (ADV) input.
■ Asynchronous output enable
■ CY7C1381D available in JEDEC-standard Pb-free 100-pin
TQFP, Pb-free and non Pb-free 165-ball FBGA package.
CY7C1383D available in JEDEC-standard Pb-free 100-pin
TQFP. CY7C1383F available in non Pb-free 165-ball FBGA
package.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as controlled by the advance pin (ADV).
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ ZZ sleep mode option
CY7C1381D/CY7C1383D/CY7C1383F operates from a +3.3 V
core power supply while all outputs operate with a +2.5 V or +3.3
V supply. All inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
Selection Guide
Description
Maximum Access Time
133 MHz
6.5
100 MHz Unit
8.5
175
70
ns
Maximum Operating Current
210
mA
mA
Maximum CMOS Standby Current
70
Cypress Semiconductor Corporation
Document Number: 38-05544 Rev. *P
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 22, 2013
CY7C1381D
CY7C1383D
CY7C1383F
Logic Block Diagram – CY7C1381D
(512 K × 36) [1]
ADDRESS
REGISTER
A0, A1, A
MODE
A
[1:0]
ADV
CLK
Q1
Q0
BURST
COUNTER
AND LOGIC
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQP D
DQ
BYTE
WRITE REGISTER
D, DQP D
BW
D
DQ C , DQP C
DQ C , DQP C
BW
C
WRITE REGISTER
DQ DQP
OUTPUT
BUFFERS
DQs
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
DQP
A
B
B
,
B
DQ B, DQP B
BW
B
C
D
WRITE REGISTER
DQ DQP
WRITE REGISTER
A
,
BYTE
DQ
BYTE
WRITE REGISTER
A, DQP A
BW
A
WRITE REGISTER
BWE
INPUT
GW
REGISTERS
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
Logic Block Diagram – CY7C1383D/CY7C1383F
(1 M × 18) [1]
ADDRESS
REGISTER
A0,A1,A
A[1:0]
MODE
ADV
Q1
COUNTER AND
BURST
Q0
DQ
B,DQP B
DQ
DQ
B
,DQP
,DQP
B
WRITE DRIVER
BW
BW
B
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQP A
A
A
WRITE DRIVER
A
BWE
GW
INPUT
REGISTERS
ENABLE
CE
CE
1
2
CE
3
OE
SLEEP
CONTROL
Note
1. CY7C1383F have only 1 chip enable (CE ).
1
Document Number: 38-05544 Rev. *P
Page 2 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................6
Functional Overview ........................................................7
Single Read Accesses ................................................7
Single Write Accesses Initiated by ADSP ...................7
Single Write Accesses Initiated by ADSC ...................7
Burst Sequences .........................................................8
Sleep Mode .................................................................8
Interleaved Burst Address Table .................................8
Linear Burst Address Table .........................................8
ZZ Mode Electrical Characteristics ..............................8
Truth Table ........................................................................9
Truth Table for Read/Write ............................................10
Truth Table for Read/Write ............................................10
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11
Disabling the JTAG Feature ......................................11
Test Access Port (TAP) .............................................11
PERFORMING A TAP RESET ..................................11
TAP REGISTERS ......................................................11
TAP Instruction Set ...................................................11
TAP Controller State Diagram .......................................13
TAP Controller Block Diagram ......................................14
TAP Timing ......................................................................15
TAP AC Switching Characteristics ...............................15
3.3 V TAP AC Test Conditions .......................................16
3.3 V TAP AC Output Load Equivalent .........................16
2.5 V TAP AC Test Conditions .......................................16
2.5 V TAP AC Output Load Equivalent .........................16
TAP DC Electrical Characteristics
Scan Register Sizes .......................................................17
Instruction Codes ...........................................................17
Boundary Scan Order ....................................................18
Maximum Ratings ...........................................................19
Operating Range .............................................................19
Neutron Soft Error Immunity .........................................19
Electrical Characteristics ...............................................19
Capacitance ....................................................................20
Thermal Resistance ........................................................20
AC Test Loads and Waveforms .....................................21
Switching Characteristics ..............................................22
Timing Diagrams ............................................................23
Ordering Information ......................................................27
Ordering Code Definitions .........................................27
Package Diagrams ..........................................................28
Acronyms ........................................................................30
Document Conventions .................................................30
Units of Measure .......................................................30
Appendix: Silicon Errata Document for
RAM9 (90-nm), 18-Mb (CY7C138*D)
Synchronous & NoBL™ SRAMs ...................................31
Part Numbers Affected ..............................................31
Product Status ...........................................................31
Ram9 Sync/NoBL ZZ Pin,
JTAG & Chip Enable Issues Errata Summary ..................31
Document History Page .................................................34
Sales, Solutions, and Legal Information ......................37
Worldwide Sales and Design Support .......................37
Products ....................................................................37
PSoC Solutions .........................................................37
and Operating Conditions .............................................16
Identification Register Definitions ................................17
Document Number: 38-05544 Rev. *P
Page 3 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enable)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
VSS/DNU
14
VDD
15
NC
VDD
ZZ
CY7C1383D
(1 M × 18)
CY7C1381D
(512 K × 36)
NC
16
NC
VSS
VDD
ZZ
VSS
17
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
20
21
VDDQ
VSSQ
DQD
22
DQD
23
DQD
24
DQD
25
26
27
NC
VSSQ
VDDQ
DQD
DQD
29
VSSQ
VDDQ
NC
NC
NC
28
DQPD
30
Document Number: 38-05544 Rev. *P
Page 4 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout(3 Chip Enable)
CY7C1381D (512 K × 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE3
7
8
9
ADV
10
A
11
NC
NC/288M
NC/144M
DQPC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
DQC
NC/1G
DQB
DQC
VDD
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE NC/36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1383F (1 M × 18)
1
2
A
3
CE1
4
BWB
5
NC
6
CE3
7
8
9
ADV
10
A
11
A
NC/288M
NC/144M
NC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
NC
VSS
VDD
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPA
DQA
NC
NC/1G
NC
NC
DQB
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
VSS
DQB
DQB
DQB
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
NC/72M
TDI
A1
TDO
MODE NC/36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document Number: 38-05544 Rev. *P
Page 5 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Pin Definitions
Name
A ,
I/O
Description
Input
Synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK
if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
A ,
A
0
1
BWA, BWB,
Input
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
BWC, BWD Synchronous
on the rising edge of CLK.
GW
CLK
CE1
Input
Synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write is
conducted (all bytes are written, regardless of the values on BW[A:D] and BWE).
Input
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
CE3
OE
Input
Synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
Input
Synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
Input
Asynchronous
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins.
OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input
Synchronous
Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically increments
the address in a burst cycle.
ADSP
Input
Synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
Input
Synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
.
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized
BWE
ZZ
Input
Synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
LOW to conduct a byte write.
Input
Asynchronous
ZZ sleep input. This active HIGH input places the device in a non time critical sleep condition with data
integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal
pull down.
I/O
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
DQs
Synchronous
addresses presented during the previous
read cycle. The direction of the pins is controlled
clock rise of the
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed
in a tristate condition.The outputs are automatically tristated during the data portion of a write sequence,
during the first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
I/O
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
sequences, DQPX is controlled by BWX correspondingly.
DQPX
Synchronous
MODE
Input Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode pin has an internal pull-up.
Document Number: 38-05544 Rev. *P
Page 6 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Pin Definitions (continued)
Name
VDD
I/O
Description
Power Supply Power supply inputs to the core of the device.
VDDQ
I/O Power Power supply for the I/O circuitry.
Supply
VSS
Ground
I/O Ground Ground for the I/O circuitry.
JTAG Serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
Ground for the core of the device.
VSSQ
TDO
Output
Synchronous
not being used, this pin can be left unconnected. This pin is not available on TQFP packages.
TDI
JTAG Serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
Input
used, this pin can be left floating or connected to VDD through a pull-up resistor. This pin is not available
on TQFP packages.
Synchronous
TMS
JTAG Serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
Input
used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Synchronous
TCK
JTAG
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected to
VSS. This pin is not available on TQFP packages.
NC
–
No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
VSS/DNU
Ground/DNU This pin can be connected to ground or can be left floating.
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter and/or
control logic, and later presented to the memory core. If the OE
input is asserted LOW, the requested data is available at the data
outputs with a maximum to tCDV after clock rise. ADSP is ignored
if CE1 is HIGH.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCDV) is 6.5 ns (133 MHz device).
CY7C1381D/CY7C1383D/CY7C1383F supports secondary
cache in systems using a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that use a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with the processor address strobe
(ADSP) or the controller address strobe (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX) are ignored during this first clock cycle. If the write
inputs are asserted active (see Truth Table for Read/Write on
page 10 for appropriate states that indicate a write) on the next
clock rise, the appropriate data is latched and written into the
device. Byte writes are allowed. All I/O are tristated during a byte
write. As this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/O must be tristated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tristated when a write cycle is detected,
regardless of the state of OE.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
Document Number: 38-05544 Rev. *P
Page 7 of 37
CY7C1381D
CY7C1383D
CY7C1383F
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered to
the memory core The information presented to DQ[A:D] is written
into the specified address location. Byte writes are allowed. All
I/O are tristated when a write is detected, even a byte write.
Because this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/O must be tristated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tristated when a write cycle is detected,
regardless of the state of OE.
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Burst Sequences
CY7C1381D/CY7C1383D/CY7C1383F provides an on-chip
two-bit wraparound burst counter inside the SRAM. The burst
counter is fed by A[1:0], and can follow either a linear or
interleaved burst order. The burst order is determined by the
state of the MODE input. A LOW on MODE selects a linear burst
sequence. A HIGH on MODE selects an interleaved burst order.
Leaving MODE unconnected causes the device to default to a
interleaved burst sequence.
Linear Burst Address Table
(MODE = GND)
Sleep Mode
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, CE3,
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
80
Unit
mA
ns
ZZ > VDD– 0.2 V
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
tZZS
–
2tCYC
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 38-05544 Rev. *P
Page 8 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Truth Table
The truth table for CY7C1381D/CY7C1383D/CY7C1383F follows. [2, 3, 4, 5, 6]
Cycle Description
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
L
X
X
H
X
X
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L–H Tri-State
L–H Tri-State
L–H Tri-State
L–H Tri-State
L–H Tri-State
None
L
X
L
L
None
L
H
H
X
L
None
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L–H
Read Cycle, Begin Burst
L
L
L
H
X
L
L–H Tri-State
Write Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L–H
L–H
D
Q
Read Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Read Cycle, Begin Burst
L
L
L
H
L
L–H Tri-State
L–H
L–H Tri-State
L–H
L–H Tri-State
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L–H
L–H
L–H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L–H Tri-State
L–H
L–H Tri-State
Q
H
X
X
L–H
L–H
D
D
L
Notes
2. X = Don't Care, H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after the
X
or with the assertion of
. As a result,
is a don't care for the
OE
ADSC
OE
ADSP
remainder of the write cycle.
6.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when
is
inactive
OE
or when the device is deselected, and all data bits behave as output when
OE
is active (LOW).
OE
Document Number: 38-05544 Rev. *P
Page 9 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Truth Table for Read/Write
The truth table for CY7C1381D read/write follows. [7, 8]
Function (CY7C1381D)
Read
GW
H
BWE
BWD
X
BWC
X
BWB
BWA
X
H
L
L
L
L
L
L
L
L
X
H
H
L
Read
H
H
H
H
Write Byte A (DQA, DQPA)
Write Byte B(DQB, DQPB)
H
H
H
L
H
H
H
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
Write Byte C (DQC, DQPC)
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
H
H
L
L
H
H
L
H
H
L
H
H
H
L
L
H
H
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
H
H
L
L
L
Write Byte D (DQD, DQPD)
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
H
L
L
L
L
L
L
H
H
H
L
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
Truth Table for Read/Write
The truth table for CY7C1383D/CY7C1383F read/write follows. [7, 8]
Function (CY7C1383D/CY7C1383F)
GW
BWE
BWB
BWA
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
L
Write All Bytes
H
L
L
X
H
L
L
X
X
H
H
L
L
X
X
H
L
Write All Bytes
Read
H
H
H
H
H
L
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
L
L
H
L
L
L
Write All Bytes
X
X
X
Notes
7. X=Don't Care, H = Logic HIGH, L = Logic LOW.
8. The table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write is done based on which byte write is active.
X
Document Number: 38-05544 Rev. *P
Page 10 of 37
CY7C1381D
CY7C1383D
CY7C1383F
the rising edge of TCK. Data is output on the TDO ball on the
falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1381D/CY7C1383F incorporates a serial boundary
scan test access port (TAP). This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V
I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
CY7C1381D/CY7C1383F contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
may be left unconnected. At power up, the device comes up in a
reset state, which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
Test Access Port (TAP)
SRAM with minimal delay. The bypass register is set LOW (VSS
when the BYPASS instruction is executed.
)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
Test Mode Select (TMS)
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The Boundary Scan Order on page 18 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 13. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Identification (ID) Register
The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
TAP Instruction Set
Overview
Performing a TAP Reset
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Instruction
Codes on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
Instructions are loaded into the TAP controller during the Shift-IR
state, when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction when it is shifted in, the TAP controller needs to
be moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI ball on
Document Number: 38-05544 Rev. *P
Page 11 of 37
CY7C1381D
CY7C1383D
CY7C1383F
EXTEST
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
IDCODE
The IDCODE instruction causes a vendor-specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required; that is, while data captured is
shifted out, the preloaded data is shifted in.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command places
all SRAM outputs into a high Z state.
EXTEST Output Bus Tri-State
IEEE standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
SAMPLE/PRELOAD
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tristate,” is latched into the preload register
during the Update-DR state in the TAP controller, it directly
controls the state of the output (Q-bus) pins, when the EXTEST
is entered as the current instruction. When HIGH, it enables the
output buffers to drive the output bus. When LOW, this bit places
the output bus into a high Z condition.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 38-05544 Rev. *P
Page 12 of 37
CY7C1381D
CY7C1383D
CY7C1383F
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
0
SELECT
DR-SCAN
SELECT
IR-SCAN
IDLE
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
1
0
PAUSE-IR
1
0
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05544 Rev. *P
Page 13 of 37
CY7C1381D
CY7C1383D
CY7C1383F
TAP Controller Block Diagram
0
0
Bypass Register
2
1
Selection
Circuitry
Instruction Register
31 30 29 .
S
election
TDI
TDO
Circuitr
y
.
.
2
1
0
Identification Register
x
.
.
.
.
. 2 1 0
Boundary Scan Register
TAP CONTROLLER
TCK
TMS
Document Number: 38-05544 Rev. *P
Page 14 of 37
CY7C1381D
CY7C1383D
CY7C1383F
TAP Timing
Figure 3. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
Parameter [9, 10]
Clock
Description
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH Time
TCK Clock LOW Time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes
9.
t
and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS CH
10. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document Number: 38-05544 Rev. *P
Page 15 of 37
CY7C1381D
CY7C1383D
CY7C1383F
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times ...................................................1 ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50 Ω
20pF
ZO= 50 Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [11]
Description
Test Conditions
VDDQ = 3.3 V
Min
2.4
2.0
2.9
2.1
–
Max
–
Unit
V
VOH1
Output HIGH Voltage
IOH = –4.0 mA
OH = –1.0 mA
I
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
–
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOH = –100 µA
–
V
–
V
IOL = 8.0 mA
0.4
0.4
0.2
0.2
V
I
OL = 8.0 mA
–
V
IOL = 100 µA
–
V
VDDQ = 2.5 V
–
V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
2.0
1.7
–0.3
–0.3
–5
VDD + 0.3
V
VDD + 0.3
V
VIL
0.8
0.7
5
V
VDDQ = 2.5 V
V
IX
GND < VIN < VDDQ
µA
Note
11. All voltages referenced to V (GND).
SS
Document Number: 38-05544 Rev. *P
Page 16 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Identification Register Definitions
CY7C1381D
(512 K × 36)
CY7C1383F
(1 M × 18)
Instruction Field
Description
Revision Number (31:29)
Device Depth (28:24) [12]
000
000
Describes the version number.
Reserved for internal use.
01011
01011
000001
Device Width (23:18) 165-ball FBGA
000001
Defines the memory type and
architecture.
Cypress Device ID (17:12)
100101
010101
Defines the width and density.
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
Allows unique identification of SRAM
vendor.
ID Register Presence Indicator (0)
1
1
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Bit Size (× 18)
Instruction Bypass
3
1
3
1
Bypass
ID
32
89
32
89
Boundary Scan Order (165-ball FBGA package)
Instruction Codes
Instruction
EXTEST
Code
Description
000
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM outputs to high Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a high Z state.
RESERVED
011
100
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use. This instruction is reserved for future use.
Do Not Use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
12. Bit #24 is “1” in the register definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05544 Rev. *P
Page 17 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Boundary Scan Order
165-ball FBGA [13, 14]
Bit #
1
Ball ID
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
N6
N7
2
3
N10
P11
P8
4
F2
5
G2
H1
H3
J1
6
R8
7
R9
8
P9
B9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
C10
A8
K1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
L1
B8
M1
J2
A7
B7
K2
B6
L2
A6
M2
N1
N2
P1
B5
A5
A4
B4
R1
R2
P3
B3
A3
A2
R3
P2
H10
G11
F11
E11
D11
G10
F10
E10
B2
C2
B1
R4
P4
A1
N5
P6
C1
D1
E1
R6
Internal
F1
Notes
13. Balls which are NC (No Connect) are pre-set LOW.
14. Bit# 89 is pre-set HIGH.
Document Number: 38-05544 Rev. *P
Page 18 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Maximum Ratings
Operating Range
Ambient
Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.
Range
VDD
VDDQ
Temperature
0 °C to +70 °C
–40 °C to +85 °C
Commercial
Industrial
3.3 V– 5% / 2.5 V – 5% to
Storage Temperature ............................... –65 °C to +150 °C
+ 10%
VDD
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
Neutron Soft Error Immunity
Test
Parameter Description
Conditions
Typ Max [15] Unit
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
LSBU
LMBU
SEL
Logical
Single-Bit
Upsets
25 °C
25 °C
85 °C
361
394
0.01
0.1
FIT/
Mb
DC Input Voltage ................................–0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Logical
Multi-Bit
Upsets
0
FIT/
Mb
Latch-up Current ....................................................> 200 mA
Single Event
Latch Up
0
FIT/
Dev
Electrical Characteristics
Over the Operating Range
Parameter [16, 17]
Description
Test Conditions
Min
Max
Unit
VDD
Power Supply Voltage
I/O Supply Voltage
3.135
3.135
2.375
2.4
3.6
VDD
2.625
–
V
V
VDDQ
for 3.3 V I/O
for 2.5 V I/O
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage [16]
Input LOW Voltage [16]
for 3.3 V I/O, IOH = –4.0 mA
for 2.5 V I/O, IOH = –1.0 mA
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 3.3 V I/O
V
2.0
–
V
–
0.4
0.4
V
–
V
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 3.3 V I/O
–0.3
–0.3
–5
0.8
0.7
5
V
for 2.5 V I/O
V
Input Leakage Current except ZZ GND VI VDDQ
and MODE
A
Input Current of MODE
Input = VSS
–30
–
–
5
A
A
A
A
A
mA
Input = VDD
Input Current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
IDD
Output Leakage Current
GND VI VDD, Output Disabled
VDD = Max, IOUT = 0 mA,
–5
–
VDD Operating Supply Current
7.5 ns cycle,
210
f = fMAX = 1/tCYC
133 MHz
10 ns cycle,
100 MHz
–
175
mA
Notes
15. No LMBU or SEL events occurred during testing; this column represents a statistical c2, 95% confidence limit calculation. For more details refer to Application Note
AN54908, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates.
16. Overshoot: V
< V + 1.5 V (pulse width less than t
/2), undershoot: V
> –2 V (pulse width less than t
/2).
CYC
IH(AC)
DD
CYC
IL(AC)
17. T
: Assumes a linear ramp from 0 V to V
within 200 ms. During this time V < V and V
< V
.
power up
DD(min)
IH
DD
DDQ
DD
Document Number: 38-05544 Rev. *P
Page 19 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Electrical Characteristics (continued)
Over the Operating Range
Parameter [16, 17]
Description
Test Conditions
Min
Max
Unit
ISB1
Automatic CE power-down
Current – TTL Inputs
Max VDD, Device Deselected,
7.5 ns cycle,
133 MHz
–
140
mA
VIN VIH or VIN VIL, f = fMAX
,
inputs switching
10 ns cycle,
100 MHz
–
–
120
70
ISB2
Automatic CE power-down
Current – CMOS Inputs
Max VDD, Device Deselected,
VIN VDD – 0.3 V or VIN 0.3 V,
f = 0, inputs static
All speeds
mA
mA
ISB3
Automatic CE power-down
Current – CMOS Inputs
Max VDD, Device Deselected,
VIN VDDQ – 0.3 V or VIN 0.3 V, 133 MHz
f = fMAX, inputs switching
7.5 ns cycle,
–
–
–
130
110
80
10 ns cycle,
100 MHz
ISB4
Automatic CE power-down
Current – TTL Inputs
Max VDD, Device Deselected,
VIN VDD – 0.3 V or VIN 0.3 V,
f = 0, inputs static
All Speeds
mA
Capacitance
100-pin TQFP 165-ballFBGA
Parameter [18]
Description
Test Conditions
Unit
Package
Package
CIN
Input capacitance
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
5
5
5
9
9
9
pF
pF
pF
CCLK
CIO
Clock input capacitance
Input/Output capacitance
Thermal Resistance
100-pin TQFP 165-ballFBGA
Parameter [18]
Description
Test Conditions
Unit
Package
Package
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, in accordance with
EIA/JESD51.
28.66
20.7
°C/W
JC
Thermal resistance
(junction to case)
4.08
4.0
°C/W
Note
18. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05544 Rev. *P
Page 20 of 37
CY7C1381D
CY7C1383D
CY7C1383F
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
10%
L
GND
5 pF
R = 351
1 ns
1 ns
INCLUDING
JIG AND
SCOPE
V = 1.5 V
T
(a)
(b)
(c)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
10%
L
GND
5 pF
R = 1538
1 ns
1 ns
INCLUDING
JIG AND
SCOPE
V = 1.25 V
T
(a)
(b)
(c)
Document Number: 38-05544 Rev. *P
Page 21 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Switching Characteristics
Over the Operating Range
133 MHz
Max
100 MHz
Parameter [19, 20]
Description
Unit
Min
Min
Max
tPOWER
Clock
tCYC
VDD(typical) to the first access [21]
1
–
1
–
ms
Clock cycle time
Clock HIGH
7.5
2.1
2.1
–
–
–
10
2.5
2.5
–
–
–
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z [22, 23, 24]
–
2.0
2.0
0
6.5
–
–
2.0
2.0
0
8.5
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
–
tCHZ
Clock to high Z [22, 23, 24]
4.0
3.2
–
5.0
3.8
–
tOEV
OE LOW to output valid
–
–
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to output low Z [22, 23, 24]
OE HIGH to output high Z [22, 23, 24]
0
0
–
4.0
–
5.0
Address setup before CLK rise
ADSP, ADSC setup before CLK rise
ADV setup before CLK rise
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BW[A:D] setup before CLK rise
Data input setup before CLK rise
Chip enable setup
tDS
tCES
Hold Times
tAH
Address hold after CLK rise
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
ADSP, ADSC hold after CLK rise
GW, BWE, BW[A:D] hold after CLK rise
ADV hold after CLK rise
tWEH
tADVH
tDH
Data input hold after CLK rise
Chip enable hold after CLK rise
tCEH
Notes
19. Timing reference level is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
20. Test conditions shown in (a) of Figure 4 on page 21 unless otherwise noted.
21. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V
initially, before a read or write operation can be
POWER
DD(minimum)
initiated.
22. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of Figure 4 on page 21. Transition is measured ±200 mV from steady-state voltage
OEHZ
CHZ CLZ OELZ
23. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
OEHZ
OELZ
CHZ
CLZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system condition.
24. This parameter is sampled and not 100% tested.
Document Number: 38-05544 Rev. *P
Page 22 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Timing Diagrams
Figure 5. Read Cycle Timing [25]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
X
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
CHZ
OEHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
25. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document Number: 38-05544 Rev. *P
Page 23 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Timing Diagrams (continued)
Figure 6. Write Cycle Timing [26, 27]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW
X
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Notes
26. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
27.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document Number: 38-05544 Rev. *P
Page 24 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Timing Diagrams (continued)
Figure 7. Read/Write Cycle Timing [28, 29, 30]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
Notes
28. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
29. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
30.
GW is HIGH.
Document Number: 38-05544 Rev. *P
Page 25 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Timing Diagrams (continued)
Figure 8. ZZ Mode Timing [31, 32]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
31. Device must be deselected when entering ZZ mode. See Truth Table on page 9 for all possible signal conditions to deselect the device.
32. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05544 Rev. *P
Page 26 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a
worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit
us at t http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
133 CY7C1381D-133AXC
CY7C1383D-133AXC
CY7C1381D-133AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
lndustrial
CY7C1383D-133AXI
CY7C1383F-133BZI
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
100 CY7C1381D-100AXC
CY7C1381D-100BZI
Commercial
lndustrial
CY7C1381D-100BZXI
Ordering Code Definitions
CY
7
C 138X X - XXX XX
X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Frequency Range: XXX = 133 MHz or 100 MHz
Die Revision: X = D or F
D 90 nm
F errata fix PCN084636
Part Identifier: 138X = 1381 or 1383
1381 = FT, 512 Kb × 36 (18 Mb)
1383 = FT, 1 Mb × 36 (18 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05544 Rev. *P
Page 27 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Package Diagrams
Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 38-05544 Rev. *P
Page 28 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Package Diagrams (continued)
Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *F
Document Number: 38-05544 Rev. *P
Page 29 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
Chip Enable
Symbol
°C
Unit of Measure
CMOS
EIA
Complementary Metal Oxide Semiconductor
Electronic Industries Alliance
Fine-Pitch Ball Grid Array
Input/Output
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
millivolt
MHz
µA
mA
mm
ms
mV
ns
FBGA
I/O
JEDEC
JTAG
LMBU
LSB
Joint Electron Devices Engineering Council
Joint Test Action Group
Logical Multi-Bit Upsets
Least Significant Bit
nanosecond
ohm
LSBU
MSB
OE
Logical Single-Bit Upsets
Most Significant Bit
%
percent
Output Enable
pF
V
picofarad
volt
SEL
Single Event Latch Up
Static Random Access Memory
Test Access Port
SRAM
TAP
W
watt
TCK
TDI
Test Clock
Test Data-In
TDO
TMS
TQFP
TTL
Test Data-Out
Test Mode Select
Thin Quad Flat Pack
Transistor-Transistor Logic
Document Number: 38-05544 Rev. *P
Page 30 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Appendix: Silicon Errata Document for RAM9 (90-nm), 18-Mb (CY7C138*D) Synchronous &
NoBL™ SRAMs
This section describes the Ram9 Sync/NoBL ZZ pin, JTAG and Chip Enable issues. Details include trigger conditions, the devices
affected, proposed workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have
further questions.
Part Numbers Affected
Density & Revision
Package Type Operating Range
18Mb-Ram9 Synchronous SRAMs: CY7C138*D
All packages
Commercial/
Industrial
Product Status
All of the devices in the Ram9 18Mb Sync/NoBL family are qualified and available in production quantities.
Ram9 Sync/NoBL ZZ Pin, JTAG & Chip Enable Issues Errata Summary
The following table defines the errata applicable to available Ram9 18Mb Sync/NoBL family devices.
Item
Issues
Description
Device
Fix Status
1. ZZ Pin
When asserted HIGH, the ZZ pin places
deviceina“sleep”conditionwithdataintegrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
18M-Ram9 (90nm)
For the 18M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
2. JTAG
During JTAG test mode, the Boundary scan
18M-Ram9 (90nm)
This issue will be fixed in the
new revision, which use the
65 nm technology. Please
contact your local sales rep for
availability.
Functionality circuitry does not perform as described in the
datasheet.However, it is possible to perform
the JTAG test with these devices in “BYPASS
mode”.
3. Chip Enable The internal Chip Enable CE3# pad is floating 18M-Ram9Synchronous This issue was fixed in the new
instead of being tied to Ground. This floating
input may cause unstable behavior of the
device during normal mode of operation.
revision of the device by a
substrate change. Please
contact your local sales rep for
availability.
SRAMs 119-ball BGA
package option only
(90nm)
Document Number: 38-05544 Rev. *P
Page 31 of 37
CY7C1381D
CY7C1383D
CY7C1383F
1. ZZ Pin Issue
■ PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■ TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■ SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■ WORKAROUND
Tie the ZZ pin externally to ground.
■ FIX STATUS
Fix was done for the 72Mb RAM9 Synchronous SRAMs and 72M RAM9 NoBL SRAMs devices. Fixed devices have a new
revision. The following table lists the devices affected and the new revision after the fix.
2. JTAG Functionality
■ PROBLEM DEFINITION
The problem occurs only when the device is operated in the JTAG test mode.During this mode, the JTAG circuitry can perform
incorrectly by delivering the incorrect data or the incorrect scan chain length.
■ TRIGGER CONDITIONS
Several conditions can trigger this failure mode.
1. The device can deliver an incorrect length scan chain when operating in JTAG mode.
2. Some Byte Write inputs only recognize a logic HIGH level when in JTAG mode.
3. Incorrect JTAG data can be read from the device when the ZZ input is tied HIGH during JTAG operation.
■ SCOPE OF IMPACT
The device fails for JTAG test. This does not impact the normal functionality of the device.
■ WORKAROUND
1.Perform JTAG testing with these devices in “BYPASS mode”.
2.Do not use JTAG test.
Document Number: 38-05544 Rev. *P
Page 32 of 37
CY7C1381D
CY7C1383D
CY7C1383F
3. Chip Enable Issue
■ PROBLEM DEFINITION
The die used for CY7C138*D has three Chip Enables, CE1#, CE2 and CE3#. The devices having part numbers CY7C138*D
(with 119-ball BGA package option only) utilize a single Chip Enable (CE1#) signal. CE2 and CE3# signals which are unused
should be internally connected to Vcc and Ground respectively to keep them in “enabled” state, thus allowing CE1# to have
full control of the chip. The internal Chip Enable CE3# pad is floating instead of being tied to Ground. This state of CE3# signal
can result in incorrect or undesirable operation of the SRAM.
■ TRIGGER CONDITIONS
There are no specific trigger conditions. The issue can occur at any time during the normal operation of the device.
■ SCOPE OF IMPACT
This issue affects the normal functionality, and can cause unstable operation of the device.
■ WORKAROUND
Use the fixed revision of the device.
■ FIX STATUS
Fix was done for all the devices having this issue and was involved re-design of the substrate in order to have CE2 and CE3#
pads bonded to Vcc and Ground lines respectively in the substrate. Fixed devices have a new revision. The following table lists
the devices affected and the new revision after the fix.
Table 1. List of Affected Devices and the new revision
Revision after the Fix
New Revision after the Fix
CY7C138*D (119-ball BGA package)
CY7C138*F (119-ball BGA package)
Document Number: 38-05544 Rev. *P
Page 33 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Document History Page
Document Title: CY7C1381D/CY7C1383D/CY7C1383F, 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM
Document Number: 38-05544
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
254518
288531
RKF
SYT
See ECN New data sheet
*A
See ECN Updated Features (Removed 117 MHz speed bin).
Updated Selection Guide (Removed 117 MHz speed bin).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Edited description for
non-compliance with 1149.1)
Updated Electrical Characteristics (Removed 117 MHz speed bin).
Updated Switching Characteristics (Removed 117 MHz speed bin).
Updated Ordering Information (Added Pb-free information for 100-pin TQFP,
119-ball BGA and 165-ball FBGA package) and added comment of ‘Pb-free
BG packages availability’ below the Ordering Information.
*B
326078
PCI
See ECN Changed status from Preliminary to Final.
Updated Pin Configurations (Address expansion pins/balls in the pinouts for
all packages are modified as per JEDEC standard).
Updated TAP Instruction Set (Changed description of OVERVIEW and
EXTEST sub-sections, added a sub-section EXTEST Output Bus Tri-State).
Updated Identification Register Definitions (Splitted Device Width (23:18) row
into two rowsDevice Width(23:18) 119-ball BGA andanother row Device Width
(23:18) 165-ball FBGA).
Updated Electrical Characteristics (Modified test conditions for VOL, VOH
parameters).
Updated Thermal Resistance (Changed JA for 100-pin TQFP Package from
31 C/W to 28.66 C/W, changed JC for 100-pin TQFP Package from 6 C/W
to 4.08 C/W, changed JA for 119-ball BGA Package from 45 C/W to
23.8 C/W, changed JC for 119-ball BGA Package from 7 C/W to 6.2 C/W,
changed JA for 165-ball FBGA Package from 46 C/W to 20.7 C/W, changed
JC for 165-ball FBGA Package from 3 C/W to 4.0 C/W).
Updated Ordering Information (Updated part numbers) and removed comment
of ‘Pb-free BG packages availability’ below the Ordering Information.
*C
*D
351895
416321
PCI
See ECN Updated Ordering Information (Updated part numbers).
NXR
See ECN Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Updated Electrical Characteristics (Changed description of IX parameter from
Input Load Current to Input Leakage Current, changed the minimum value of
IX parameter corresponding to Input Current of MODE from –5 A to –30 A,
changed the maximum value of IX parameter corresponding to Input Current
of MODE from 30 A to 5 A, changed the minimum value of IX parameter
corresponding to Input Current of ZZ from –30 A to –5 A, changed the
minimum value of IX parameter corresponding to Input Current of ZZ from 5 A
to 30 A, Changed VIH < VDD to VIH < VDD in Note 17).
Updated Ordering Information (Updated part numbers) and replaced Package
Name column with Package Diagram in the Ordering Information table.
*E
*F
475009
776456
VKN
VKN
See ECN Updated TAP AC Switching Characteristics (Changed the minimum values of
t
TH, tTL parameters from 25 ns to 20 ns and changed the maximum value of
tTDOV parameter from 5 ns to 10 ns).
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
See ECN Added part numbers CY7C1381F and CY7C1383F and its related information.
Added Note 1 regarding Chip Enable.
Updated Ordering Information (Updated part numbers).
Document Number: 38-05544 Rev. *P
Page 34 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Document History Page (continued)
Document Title: CY7C1381D/CY7C1383D/CY7C1383F, 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM
Document Number: 38-05544
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
Added Neutron Soft Error Immunity.
Updated Ordering Information (By including parts that are available) and
modified the disclaimer for the Ordering information.
*G
2752731
VKN /
PYRS
08/17/09
*H
*I
2897182
3159479
NJY
NJY
03/22/2010 Updated Ordering Information (Removed inactive parts).
Updated Package Diagrams.
02/01/2011 Updated Package Diagrams.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*J
*K
*L
3192403
3210400
3440174
NJY
NJY
NJY
03/10/2011 Updated in new template.
03/30/2011 Updated Ordering Information (Removed pruned part CY7C1381F-133BGC).
11/16/2011 Updated OrderingInformation (Added two part numbers CY7C1383D-133AXC
and CY7C1383D-133AXI).
*M
*N
3489571
3578427
NJY
01/10/2012 Updated Ordering Information (Added part number CY7C1383F-133BZI).
Updated Package Diagrams.
PRIT
04/11/2012 Updated Features (Removed CY7C1381F related information, removed
119-ball BGA package related information, removed 165-ball FBGA package
related information for CY7C1383D, added 165-ball FBGA package related
information for CY7C1383F).
Updated Functional Description (Removed CY7C1381F related information,
removed the Note “For best practices or recommendations, refer to the
Cypress application note AN1064, SRAM System Design Guidelines on
www.cypress.com.” and its reference, removed the Note “CE3, CE2 are for
100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only
in 1 chip enable.”).
Updated Logic Block Diagram – CY7C1381D (Removed CY7C1381F related
information).
Updated Pin Configurations (Removed CY7C1381F related information,
removed 119-ball BGA package related information, removed 165-ball FBGA
package related information for CY7C1383D, added 165-ball FBGA package
related information for CY7C1383F).
Updated Pin Definitions (Removed the Note “CE3, CE2 are for 100-pin TQFP
and 165-ball FBGA packages only. 119-ball BGA is offered only in 1 chip
enable.” and its reference).
Updated Functional Overview (Removed CY7C1381F related information,
removed the Note “CE3, CE2 are for 100-pin TQFP and 165-ball FBGA
packages only. 119-ball BGA is offered only in 1 chip enable.” and its
reference).
Updated Truth Table (Removed CY7C1381F related information).
Updated Truth Table for Read/Write (Removed CY7C1381F related
information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed CY7C1381F
and CY7C1383D related information).
Updated Identification Register Definitions (Removed CY7C1381F and
CY7C1383D related information, removed 119-ball BGA package related
information).
Updated Scan Register Sizes (Removed 119-ball BGA package related
information).
Removed Boundary Scan Order (Corresponding to 119-ball BGA package).
Updated Capacitance (Removed 119-ball BGA package related information).
Updated Thermal Resistance (Removed 119-ball BGA package related
information).
Updated Package Diagrams (Removed 119-ball BGA package related
information).
Document Number: 38-05544 Rev. *P
Page 35 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Document History Page (continued)
Document Title: CY7C1381D/CY7C1383D/CY7C1383F, 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM
Document Number: 38-05544
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*O
3945784
PRIT
03/27/2013 Updated Package Diagrams:
spec 51-85180 – Changed revision from *E to *F.
*P
3977530
PRIT
04/22/2013 Addded Appendix: Silicon Errata Document for RAM9 (90-nm), 18-Mb
(CY7C138*D) Synchronous & NoBL™ SRAMs.
Document Number: 38-05544 Rev. *P
Page 36 of 37
CY7C1381D
CY7C1383D
CY7C1383F
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05544 Rev. *P
Revised April 22, 2013
Page 37 of 37
All products and company names mentioned in this document may be the trademarks of their respective holders.
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