CY7C1382A-133BGC [CYPRESS]
Cache SRAM, 1MX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119;
| 型号： | CY7C1382A-133BGC |
| 厂家： | 
CYPRESS |
| 描述： | Cache SRAM, 1MX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119 静态存储器 |
| 文件： | 总32页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1380A
CY7C1382A
PRELIMINARY
512K x 36 / 1M x 18 Pipelined SRAM
inputs, address-pipelining Chip Enable (CE), burst control in-
puts (ADSC, ADSP, and ADV), write enables (BWa, BWb,
BWc, BWd and BWE), and Global Write (GW).
Features
• Fast clock speed: 167, 150, 133, 100 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 3.4, 3.8, 4.2 and 5.0 ns
• Optimal for depth expansion
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data (DQ
) and the data
a,b,c,d
parity (DQP
nous.
) outputs, enabled by OE, are also asynchro-
a,b,c,d
• 3.3V (–5% / +10%) power supply
DQ
and DQP
apply to CY7C1380 and DQ and
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
a,b,c,d
a,b,c,d a,b
DQP apply to CY7C1382. a, b, c, d each are 8 bits wide in
the case of DQ and 1 bit wide in the case of DP.
a,b
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• High-density, high-speed packages
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
Functional Description
controls DQa and DQPa. BWb controls DQ and DQP . BWc
b
b
controls DQcand DQPd. BWd controls DQd-DQd and DQPd.
BWa, BWb, BWc, and BWd can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. WRITE
pass-through capability allows written data available at the out-
put for the immediately next READ cycle. This device also in-
corporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1380A and CY7C1382A SRAMs integrate
524,288x36 and 1,048,576x18 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
isters controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
All inputs and outputs of the CY7C1380A and the CY7C1382A
are JEDEC standard JESD8-5 compatible.
Selection Guide
167 MHz
150 MHz
3.8
133 MHz
4.2
100 MHz
5.0
Maximum Access Time (ns)
3.4
350
30
Maximum Operating Current (mA)
Commercial
310
280
250
Maximum CMOS Standby Current (mA)
30
30
30
Shaded areas contain advance information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
May 18, 2000
CY7C1380A
CY7C1382A
PRELIMINARY
Logic Block Diagram CY7C1380A - 512K x 36
MODE
2
(A
)
[1;0]
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
17
19
ADDRESS
REGISTER
CE
D
512KX36
MEMORY
ARRAY
A
[18:0]
19
17
GW
DQ , DP
BYTEWRITE
REGISTERS
D
Q
d
d
BWE
BW
d
DQ , DP
BYTEWRITE
REGISTERS
D
D
D
Q
Q
Q
c
c
BW
c
DQ , DP
b
b
BYTEWRITE
REGISTERS
BW
b
DQ , DP
a
a
BYTEWRITE
BW
a
REGISTERS
36
36
CE
1
2
D
D
Q
CE
ENABLE CE
REGISTER
CE
3
Q
OUTPUT
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
a,b,c,d
a,b
DP
CY7C1382A - 1M X 18
MODE
2
(A
)
[1;0]
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
Q
1
ADSP
Q
17
19
ADDRESS
REGISTER
CE
D
1M X 18
A
[19:0]
19
17
MEMORY
ARRAY
GW
DQ , DP
BYTEWRITE
REGISTERS
D
Q
b
b
BWE
BW
b
DQ , DP
BYTEWRITE
REGISTERS
D
Q
a
a
BW
a
18
18
CE
2
1
D
CE
Q
CE
ENABLE CE
REGISTER
CE
3
D
Q
OUTPUT
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
a,b
DP
a,b
2
CY7C1380A
CY7C1382A
PRELIMINARY
Pin Configurations
100-Pin TQFP
(Top View)
DQPc
1
NC
NC
NC
VDDQ
VSSQ
NC
DQPb
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
A
NC
NC
VDDQ
VSSQ
NC
DPa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
2
DQc
VDDQ
VSSQ
DQc
3
4
5
6
DQc
7
NC
DQc
8
DQb
DQb
VSSQ
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DPb
NC
DQc
9
9
VSSQ
10
11
12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQc
DQc
13
NC
14
CY7C1382A
(1M x 18)
CY7C1380A
(512K X 36)
VDD
15
NC
VDD
ZZ
NC
16
VDD
ZZ
VSS
17
DQd
18
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
DQPa
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
DQd
19
VDDQ
20
VSSQ
21
DQd
22
DQd
23
DQd
24
DQd
25
NC
VSSQ
26
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
VDDQ
27
DQd
28
DQd
29
DQPd
30
3
CY7C1380A
CY7C1382A
PRELIMINARY
Pin Configurations (continued)
CY7C1380A (512K x 36)
1
3
2
4
5
6
7
A
A
A
V
DDQ
A
A
A
V
V
A
ADSP
ADSC
A
A
DDQ
A
B
C
D
E
F
NC
NC
NC
V
NC
A
A
A
DD
DQPb
DQb
DQb
V
DQPc
NC
DQb
DQb
DQc
DQc
SS
SS
DQc
V
V
CE
V
SS
SS
1
V
DQc
DQc
DQc
OE
V
SS
V
SS
DDQ
DQc
DQc
DDQ
DQb
DQb
DQb
DQb
ADV
GW
G
H
J
BWc
BWb
V
V
SS
SS
V
V
V
V
NC
V
NC
DD
DD
DDQ
DDQ
DD
K
L
DQa
DQa
DQd
DQd
V
DQd
DQa
DQa
DQa
DQa
DQPa
A
V
SS
CLK
NC
SS
DQd
BWd
BWa
M
V
V
V
DQd
DQd
BWE
A1
V
DDQ
DDQ
SS
SS
DQa
DQa
N
P
R
T
DQd
V
V
SS
SS
DQd
NC
DQPd
V
A0
V
SS
SS
MODE
A
V
A
NC
ZZ
V
DD
DD
NC
NC
A
A
NC
U
TMS
V
TDI
TCK
TDO
NC
V
DDQ
DDQ
CY7C1382A (1M x 18)
1
3
2
4
5
6
7
A
B
C
D
E
F
A
A
V
A
A
A
V
A
A
V
A
A
ADSP
ADSC
DDQ
NC
DDQ
NC
NC
DQb
NC
V
NC
A
A
A
DD
V
NC
DQb
DQPa
NC
NC
NC
SS
SS
V
V
DQa
CE
V
SS
SS
1
DQa
V
NC
DQb
NC
OE
V
SS
V
DDQ
DDQ
SS
DQa
NC
NC
ADV
GW
G
H
J
BWb
V
NC
DQb
SS
V
DQa
V
SS
SS
V
V
V
V
NC
V
NC
DD
DDQ
DD
DDQ
DD
K
L
DQa
NC
DQb
NC
V
NC
NC
DQa
NC
DQa
NC
A
V
SS
CLK
NC
SS
DQb
V
BWa
SS
M
V
V
V
BWE
A1
DQb
NC
V
DDQ
SS
DDQ
SS
NC
N
P
DQb
NC
V
V
SS
SS
DQPb
DQa
V
A0
V
SS
SS
R
T
NC
V
MODE
A
A
A
NC
ZZ
Vdd
NC
DD
A
A
NC
U
V
TMS
TDI
TCK
TDO
V
DDQ
NC
DDQ
4
CY7C1380A
CY7C1382A
PRELIMINARY
Pin Definitions (100-Pin TQFP)
x18 Pin Locations x36 Pin Locations
Name
A0
A1
A
I/O
Description
37, 36, 32–25,
37, 36, 32–35,
Input-
Synchronous
Address Inputs used to select one of the address
locations. Sampled at the rising edge of the CLK if
ADSP or ADSC is active LOW, and CE CE , and
42–50, 80–82, 99, 42–50, 81, 82, 99,
100
100
1,
2
CE are sampled active. A
feed the 2-bit
3
[1:0]
counter.
93, 94
93, 94, 95, 96,
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualifiedwith
BWE to conduct byte writes to the SRAM. Sampled
on the rising edge of CLK.
88
88
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When as-
serted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regard-
less of the values on BW
and BWE).
a,b,c,d
87
89
87
89
BWE
CLK
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on
the rising edge of CLK. This signal must be assert-
ed LOW to conduct a byte write.
Input-Clock
Clock Input. Used to capture allsynchronous inputs
to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst
operation.
98
98
CE
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the
1
rising edge of CLK. Used in conjunction with CE
2
and CE to select/deselect the device. ADSP is ig-
3
nored if CE is HIGH.
1
97
92
86
97
92
86
CE
CE
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the
2
3
rising edge of CLK. Used in conjunction with CE
1
and CE to select/deselect the device.
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and CE to select/deselect the device.
2
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a
read cycle when emerging from a deselected state.
83
84
83
84
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge
ofCLK. When asserted, it automatically increments
the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the
rising edge of CLK. When asserted LOW, A is cap-
tured in the address registers. A
are also loaded
[1:0]
into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is
ignored when CE is deasserted HIGH.
1
5
CY7C1380A
CY7C1382A
PRELIMINARY
Pin Definitions (100-Pin TQFP) (continued)
x18 Pin Locations x36 Pin Locations
Name
ADSC
I/O
Description
Address Strobe from Controller, sampled on the ris-
ing edge of CLK. When asserted LOW, A is cap-
85
31
64
85
31
64
Input-
Synchronous
[x:0]
tured in the address registers. A
are also loaded
[1:0]
into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
MODE
ZZ
Input-
Static
Selects Burst Order. When tied to GND selects lin-
ear burst sequence. When tied to V
or left float-
DDQ
ing selects interleaved burst sequence. This is a
strap pin and should remain static during device
operation.
Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the
device in a non-time critical “sleep” condition with
data integrity preserved.
(a) 58, 59, 62, 63,
68, 69, 72, 73
(b) 8, 9, 12, 13, 18, (b) 68, 69, 72–75,
(a) 52, 53, 56–59,
62, 63
DQa
DQb
DQc
DQd
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed
into an on-chip data register that is triggered by the
rising edgeof CLK. As outputs, theydeliver the data
contained in the memory location specified by A
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs.
When HIGH, DQa and DPa are placed in a
three-state condition.
19, 22, 23
78, 79
(c) 2, 3, 6–9, 12, 13
(d) 18, 19, 22–25,
28, 29
74, 24
51, 80, 1, 30
DQPa
DQPb
DQPc
DQPd
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed
into an on-chip data register that is triggered by the
rising edgeof CLK. As outputs, theydeliver the data
contained in the memory location specified by A
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs.
When HIGH, DQx and DPx are placed in a
three-state condition.
15, 41, 65, 91
17, 40, 67, 90
15, 41, 65, 91
17, 40, 67, 90
V
Power Supply
Ground
Power supply inputs to the core of the device.
Should be connected to 3.3V –5% +10% power
supply.
DD
V
V
V
Ground for the core of the device. Should be con-
nected to ground of the system.
SS
4, 11, 20, 27, 54,
61, 70, 77
4, 11, 20, 27, 54, 61,
70, 77
I/O Power
Supply
Power supply for the I/O circuitry. Should be con-
nected to a 2.5 –5% –3.3V 10% power supply.
DDQ
SSQ
5, 10, 21, 26, 55,
60, 71, 76
5, 10, 21, 26, 55, 60,
71, 76
I/O Ground
Ground for the I/O circuitry. Should be connected
to ground of the system.
1, 2, 3, 6, 7, 14, 16, 14, 16, 38, 39, 66
25, 28, 29, 30, 38,
39, 51, 52, 53, 56,
57, 66, 75, 78, 79,
95, 96
NC
-
No Connects.
6
CY7C1380A
CY7C1382A
PRELIMINARY
Pin Definitions (119-Ball BGA)
x18 Pin Locations
x36 Pin Locations
4P, 4N,
2A, 2B, 2C, 2R, 3A, A1
Name
I/O
Input-
Description
Address Inputs used to select one of the address
4P, 4N, 2A, 2B, 2C,
3A, 5A, 6A, 3B, 5B,
3C, 5C, 6C, 2R, 6R, 3B, 3C, 3T, 4T, 5A,
A0
Synchronous locations. Sampled at the rising edge of the CLK
if ADSP or ADSC is active LOW, and CE is sam-
A
2T, 3T, 5T, 6B, 6T
5B, 5C, 5T, 6A, 6B,
6C, 6R
pled active. A
feed the 2-bit counter.
[1:0]
5L, 3G
5L, 5G, 3G, 3L
BWa
BWb
BWc
BWd
Input-
Byte Write Select Inputs, active LOW. Qualified
Synchronous with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
4H
4H
GW
Input-
Global Write Enable Input, active LOW. When as-
Synchronous serted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regard-
less of the values on BW
and BWE).
a,b,c,d
4M
4K
4M
4K
BWE
CLK
Input-
Byte Write Enable Input, active LOW. Sampled on
Synchronous the rising edge of CLK. This signal must be assert-
ed LOW to conduct a byte write.
Input-Clock
Clock Input. Used to capture all synchronous in-
puts to the device. Also used to increment the
burst counter when ADV is asserted LOW, during
a burst operation.
4E
4F
4E
4F
CE
Input-
Chip Enable Input, active LOW. Sampled on the
1
Synchronous rising edge of CLK. ADSP is ignored if CE is
1
HIGH.
OE
Input-
Output Enable, asynchronous input, active LOW.
Asynchronous Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a
read cycle when emerging from a deselected
state.
4G
4A
4G
4A
ADV
Input-
Advance Input signal, sampled on the rising edge
Synchronous of CLK. When asserted, it automatically incre-
ments the address in a burst cycle.
ADSP
Input-
Synchronous rising edge of CLK. When asserted LOW, A is cap-
tured in the address registers. A are also load-
Address Strobe from Processor, sampled on the
[1:0]
ed into the burst counter. When ADSP and ADSC
are both asserted, only ADSP is recognized.
ASDP is ignored when CE is deasserted HIGH.
1
7
CY7C1380A
CY7C1382A
PRELIMINARY
Pin Definitions (119-Ball BGA) (continued)
x18 Pin Locations
4B
x36 Pin Locations
4B
Name
ADSC
I/O
Description
Address Strobe from Controller, sampled on the
is
Input-
Synchronous rising edge of CLK. When asserted LOW, A
[x:0]
captured in the address registers. A
are also
[1:0]
loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recog-
nized.
3R
7T
3R
7T
MODE
ZZ
Input-
Static
Selects Burst Order. When tied to GND selects
linear burst sequence. When tied to V
or left
DDQ
floating selects interleaved burst sequence. This
is a strap pin and should remain static during de-
vice operation.
Input-
ZZ“sleep” Input. Thisactive HIGH inputplaces the
Asynchronous device in a non-time critical “sleep” condition with
data integrity preserved.
(a) 6F, 6H, 6L, 6N,
7E, 7G, 7K, 7P
(b) 1D, 1H, 1L, 1N,
2E, 2G, 2K, 2M
(a) 6K, 6L, 6M, 6N,
7K, 7L, 7N, 7P
(b) 6E, 6F, 6G, 6H,
7D, 7E, 7G, 7H
(c) 1D, 1E, 1G, 1H,
2E, 2F, 2G, 2H
(d) 1K, 1L, 1N, 1P,
2K, 2L, 2M, 2N
DQa
DQb
DQc
DQd
I/O-
Bidirectional Data I/O lines. As inputs, they feed
Synchronous into an on-chip data register that is triggered by
the rising edge ofCLK. As outputs, they deliver the
data contained in the memory location specified
by A during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQx and DQPx are placed
in a three-state condition.
U5
U3
U2
U5
U3
U2
TDO
TDI
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data
on the negative edge of TCK.
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK.
TMS
TCK
Test Mode Se- This pin controls the Test Access Port state ma-
lect
Synchronous
chine. Sampled on the rising edge of TCK.
U4
U4
JTAG-Clock
Clock input to the JTAG circuitry.
6D, 2P
6P, 6D, 2D, 2P
DQPa
DQPb
DQPc
DQPd
I/O-
Bidirectional Data I/O lines. As inputs, they feed
Synchronous into an on-chip data register that is triggered by
the rising edge ofCLK. As outputs, they deliver the
data contained in the memory location specified
by A during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQx and DPx are placed in
a three-state condition.
2J, 4C, 4J, 4R, 5R, 6J 2J, 4C, 4J, 4R, 5R,
6J
V
V
Power Supply Power supply inputs to the core of the device.
Should be connected to 3.3V power supply.
DD
SS
3D, 3E, 3F, 3H, 3K,
3M, 3N, 3P, 5D, 5E,
5F, 5H, 5K, 5M, 5N,
5P
3D, 3E, 3F, 3H, 3K,
3M, 3N, 3P, 5D, 5E,
5F, 5H, 5K, 5M, 5N,
5P
Ground
Ground for the device. Should be connected to
ground of the system.
1A, 1F, 1J, 1M, 1U,
7A, 7F, 7J, 7M, 7U
1A, 1F, 1J, 1M, 1U,
7A, 7F, 7J, 7M, 7U
V
I/O Power
Supply
Power supply for the I/O circuitry.
No Connects.
DDQ
1B, 1C, 1E, 1G, 1K,
1P, 1R, 1T, 2D, 2F,
2H, 2L, 2N, 3J, 4D,
4L, 4T, 5J, 6E, 6G,
6K, 6M, 6P, 6U, 7B,
7C, 7D, 7H, 7L, 7N,
7R
1B, 1C, 1R, 1T, 2T,
3J, 4D, 4L, 5J, 6T,
6U, 7B, 7C, 7R
NC
-
8
CY7C1380A
CY7C1382A
PRELIMINARY
logic while being delivered to the RAM core. The write signals
(GW, BWE, and BWx) and ADV inputs are ignored during this
first cycle.
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx sig-
nals. The CY7C1380A/CY7C1382A provides byte write capa-
bility that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
imum access delay from the clock rise (t ) is 3.8 ns (133-MHz
CO
device).
The CY7C1380A/CY7C1382A supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium® and i486 pro-
cessors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC). Ad-
dress advancement through the burst sequence is controlled
by the ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automati-
cally increments the address for the rest of the burst access.
Byte Write (BW
for CY7C1380A
&
BW
for
a,b,c,d
a,b
CY7C1382A) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because the CY7C1380A/CY7C1382A is a common I/O de-
vice, the Output Enable (OE) must be deasserted HIGH before
presenting data to the DQ inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
for 1380 and BW for
a,b,c,d
a,b
1382) inputs. A Global Write Enable (GW) overrides all byte
write inputs and writes data to all four bytes. All writes are
simplified with on-chip synchronous self-timed write circuitry.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BWx) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
Synchronous Chip Selects (CE , CE , CE for TQFP / CE for
1
2
3
1
BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. ADSP is
ignored if CE is HIGH.
1
cycle to complete. The address presented to A
is loaded
[17:0]
Single Read Accesses
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is ig-
nored during this cycle. If a global write is conducted, the data
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
presented to the DQ
is written into the corresponding ad-
[x:0]
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
1
dress location in the RAM core. If a byte write is conducted,
only the selected bytes are written. Bytes not selected during
a byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.0 ns (200-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Because the CY7C1380A/CY7C1382A is a common I/O de-
vice, the Output Enable (OE) must be deasserted HIGH before
presenting data to the DQ
inputs. Doing so will three-state
[x:0]
the output drivers. As a safety precaution, DQ
are automat-
[x:0]
ically three-stated whenever a write cycle is detected, regard-
less of the state of OE.
Burst Sequences
The CY7C1380A/CY7C1382A provides a two-bit wraparound
counter, fed by A
, that implements either an interleaved or
[1:0]
linear burst sequence. The interleaved burst sequence is de-
signed specifically to support Intel® Pentium applications. The
linear burst sequence is designed to support processors that
follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is load-
ed into the address register and the address advancement
9
CY7C1380A
CY7C1382A
PRELIMINARY
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Linear Burst Sequence
First
Address
Second
Address
Third
Fourth
Address
Address
Interleaved Burst Sequence
A
A
A
A
[1:0]
[1:0]
[1:0]
[1:0]
First
Address
Second
Address
Third
Address
Fourth
Address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
A
A
A
A
[1:0]
[1:0]]
[1:0]
[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CEs, ADSP, and ADSC must remain inactive for the duration
of t
after the ZZ input returns LOW.
ZZREC
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
I
t
t
Snooze mode
standby current
ZZ > V – 0.2V
15
mA
DDZZ
DD
Deviceoperationto
ZZ
ZZ > V – 0.2V
2t
CYC
ns
ns
ZZS
DD
ZZ recovery time
ZZ < 0.2V
2t
CYC
ZZREC
10
CY7C1380A
CY7C1382A
PRELIMINARY
Cycle Descriptions[1, 2, 3, 4]
Next Cycle
Unselected
Add. Used
None
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
CE
X
1
CE
X
X
0
CE
1
ADSP
X
0
ADSC
ADV
X
X
X
X
X
X
X
0
OE
X
X
X
X
X
X
X
1
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Write
X
3
2
1
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
X
Unselected
None
0
X
Unselected
None
X
1
0
0
X
Unselected
None
X
0
0
1
X
Unselected
None
X
0
0
1
X
Begin Read
External
External
Next
1
0
0
X
Begin Read
0
1
0
1
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
1
X
X
1
1
Next
1
0
0
Next
X
X
1
0
1
Hi-Z
DQ
Next
1
0
0
Current
Current
Current
Current
Current
Current
External
Next
X
X
1
1
1
Hi-Z
DQ
1
1
0
X
X
1
1
1
Hi-Z
DQ
1
1
0
X
1
1
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Begin Write
X
1
1
Begin Write
0
X
0
Continue Write
Continue Write
Suspend Write
Suspend Write
X
X
X
X
X
X
X
X
X
X
X
1
1
Next
X
1
0
Current
Current
None
X
1
1
X
X
1
ZZ “sleep”
X
X
Note:
1. X=”Don't Care.” 1= HIGH, 0 = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has a single chip select CE1.
11
CY7C1380A
CY7C1382A
PRELIMINARY
Write Cycle Descriptions[5, 6, 7]
Function (1380)
Read
GW
1
BWE
BWd
X
1
BWc
X
1
BWb
X
1
BWa
X
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
Read
1
Write Byte 0 - DQa
Write Byte 1 - DQb
Write Bytes 1, 0
Write Byte 2 - DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 - DQd
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
1
1
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
0
1
1
0
0
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
0
0
0
1
1
0
0
0
0
Write All Bytes
0
X
X
X
X
Function (1382)
GW
BWE
BWb
BWa
Read
Read
1
1
1
1
1
0
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
Write Byte 0 - DQ
Write Byte 1 - DQ
Write All Bytes
and DP
0
[7:0]
and DP
[15:8]
1
Write All Bytes
12
CY7C1380A
CY7C1382A
PRELIMINARY
ry. Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1380A/CY7C1382A incorporates a serial boundary
scan Test Access Port (TAP) in the FBGA package only. The
TQFP package does not offer this functionality. This port oper-
ates in accordance with IEEE Standard 1149.1-1900, but does
not have the set of functions required for full 1149.1 compli-
ance. These functions from the IEEE specification are exclud-
ed because their inclusion places an added delay in the critical
speed path of the SRAM. Note that the TAP controller func-
tions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP op-
erates using JEDEC standard 3.3V I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as de-
scribed in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary "01" pattern to allow
for fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V ) to prevent clocking of the device. TDI and TMS are in-
ternally pulled up and may be unconnected. They may alter-
SS
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
nately be connected to V
through a pull-up resistor. TDO
DD
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the oper-
ation of the device.
Test Access Port (TAP) - Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a xx-bit-long regis-
ter, and the x18 configuration has a yy-bit-long register.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the regis-
ters and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruc-
tion that is loaded into the TAP instruction register. For infor-
mation on loading the instruction register, see the TAP Con-
troller State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Defi-
nitions table.
The TDO output pin is used to serially clock data-out from the
registers. The e output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five ris-
ing edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is oper-
ating. At power-up, the TAP is reset internally to ensure that
TDO comes up in a high-Z state.
Eight different instructions are possible with the three-bit in-
struction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RE-
SERVED and should not be used. The other five instructions
are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller can-
not be used to load address, data or control signals into the
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuit-
13
CY7C1380A
CY7C1382A
PRELIMINARY
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE / PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
When the SAMPLE / PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible
that during the Capture-DR state, an input or output will under-
go a transition. The TAP may then try to capture a signal while
in transition (metastable state). This will not harm the device,
but there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP control-
ler needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be ex-
ecuted whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in the TAP controller, and there-
fore this device is not compliant to the 1149.1 standard.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (TCS and TCH). The SRAM clock input might not
be captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK captured in the
boundary scan register.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE / PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE / PRELOAD instruction, EX-
TEST places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP con-
troller enters the Shift-DR state. The IDCODE instruction is
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE / PRELOAD in-
struction will have the same effect as the Pause-DR command.
loaded into the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
Bypass
When the BYPASS instruction is loaded in the instruction reg-
ister and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The advan-
tage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a
board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Reserved
SAMPLE / PRELOAD
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
14
CY7C1380A
CY7C1382A
PRELIMINARY
TAP Controller State Diagram
TEST-LOGIC
1
RESET
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
CAPTURE-DR
0
1
1
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
15
CY7C1380A
CY7C1382A
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
0
TDO
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
.
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
[5, 6]
TAP Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
1.7
Max.
Unit
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
I
I
I
I
= –2.0 mA
= –100 mA
= 2.0 mA
V
V
OH1
OH
OH
OL
OL
V
2.1
OH2
V
0.7
0.2
V
OL1
V
= 100 mA
V
OL2
V
V
1.7
–0.3
–5
V
+0.3
DD
V
IH
IL
0.7
V
I
GND < V < V
DDQ
5
mA
X
I
Notes:
5. All Voltage referenced to Ground.
6. Overshoot: VIH(AC)<VDD+1.5V for t<tTCYC/2, Undershoot:VIL(AC)<0.5V for t<tTCYC/2, Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V for t<200 ms.
16
CY7C1380A
CY7C1382A
PRELIMINARY
[7, 8]
TAP AC Switching Characteristics Over the Operating Range
Parameters
Description
Min.
Max
Unit
ns
t
t
t
t
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
TCYC
TF
10
MHz
ns
40
40
TH
TCK Clock LOW
ns
TL
Set-up Times
t
t
t
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
TMSS
TDIS
CS
Hold Times
t
t
t
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
TMSH
TDIH
CH
Capture Hold after Clock Rise
Output Times
t
t
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
TDOV
TDOX
0
Notes:
7. CS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
t
8. Test conditions are specified using the load in TAP AC test conditions. TR/TF = 1 ns.
17
CY7C1380A
CY7C1382A
PRELIMINARY
TAP Timing and Test Conditions
1.25V
50
Ω
ALL INPUT PULSES
1.50V
TDO
3.3V
Z =50
Ω
0
=20 pF
C
L
0V
GND
(a)
t
TL
t
TH
Test Clock
TCK
t
TCYC
t
TMSS
t
TMSH
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data-In
TDI
Test Data-Out
TDO
t
t
TDOX
TDOV
18
CY7C1380A
CY7C1382A
PRELIMINARY
Identification Register Definitions
Instruction Field
512K x 36
1M x 18
Description
Revision Number
xxxx
xxxx
Reserved for version number.
(31:28)
Device Depth
(27:23)
00111
00100
01000
00011
Defines depth of SRAM. 512K or 1M
Defines with of the SRAM. x36 or x18
Reserved for future use.
Device Width
(22:18)
Cypress Device ID
(17:12)
xxxxx
xxxxx
Cypress JEDEC ID
(11:1)
xxxxxxxxxxx
1
xxxxxxxxxxx
1
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
ID Register Presence
(0)
Scan Register Sizes
Register Name
Instruction
Bit Size (x18)
Bit Size (x36)
3
1
3
1
Bypass
ID
32
70
32
51
Boundary Scan
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register be-
tween TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
Captures the Input/Output contents. Places the boundary scan register be-
tween TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction
does not implement 1149.1 preload function and is therefore not 1149.1
compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
19
CY7C1380A
CY7C1382A
PRELIMINARY
Boundary Scan Order (512K X 18)
Boundary Scan Order (1M X 18)
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Bit #
Bit #
36
Bit #
Bit #
36
1
A
2R
A
6B
1
A
2R
DQb
2E
2
A
3T
4T
5T
6R
3B
5B
6P
7N
6M
7L
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
BWa#
BWb#
BWc#
BWd#
A
5L
2
A
2T
3T
5T
6R
3B
5B
7P
6N
6L
7K
7T
6H
7G
6F
7E
6D
6T
6A
5A
4G
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
DQb
DQb
NC
2G
1H
5R
2K
1L
3
A
5G
3G
3L
3
A
4
A
4
A
5
A
5
A
DQb
DQb
DQb
DQb
DQb
MODE
A
6
A
2B
4E
3A
2A
2D
1E
2F
1G
1D
1D
2E
2G
1H
5R
2K
1L
6
A
7
A
CE#
A
7
A
2M
1N
2P
3R
2C
3C
5C
6C
4N
4P
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
8
DQa
DQa
DQa
DQa
ZZ
9
A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
6K
7P
6N
6L
A
DQa
DQa
DQa
DQa
DQa
A
A
A
A1
7K
7T
6H
7G
6F
7E
6D
7H
6G
6E
7D
6A
5A
4G
A0
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
A
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
A
ADV#
2M
1N
2P
1K
2L
ADSP# 4A
ADSC# 4B
OE#
BWE#
GW#
CLK
A
4F
4M
4H
4K
6B
5L
2N
1P
3R
2C
3C
5C
6C
4N
4P
A
ADV#
BWa#
BWb#
A
ADSP# 4A
ADSC# 4B
3G
2B
4E
3A
2A
1D
A
OE#
4F
4M
4H
4K
A
CE#
A
BWE#
GW#
CLK
A
A1
A
A0
DQb
20
CY7C1380A
CY7C1382A
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–55°C to +150°C
Latch-Up Current.................................................... >200 mA
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Ambient
Supply Voltage on V Relative to GND........ –0.3V to +4.6V
[10]
DD
Range Temp.
V
V
DDQ
DD
DC Voltage Applied to Outputs
[9]
in High Z State ................................. –0.5V to V
+ 0.5V
+ 0.5V
Com’l
0−70°C
3.3V +10% /–5%
2.375V–V
DDQ
DD
[9]
DC Input Voltage .............................. –0.5V to V
DDQ
Electrical Characteristics Over the Operating Range
Parameter
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
Unit
V
3.3V range
3.3V range
2.5V range
V
V
V
V
V
V
DD
V
3.6
DDQ
V
DD
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
V
= Min., I = -1.0 mA
3.3V
2.5V
3.3V
2.5V
3.3 V
2.5V
3.3V
2.5V
OH
DD
OH
1.7
V
V
= Min., I = 1.0 mA
0.4
0.7
OL
DD
OL
V
2.0
1.7
V
V
IH
IL
[9]
V
Input LOW Voltage
–0.3
–0.3
–5
0.8
0.7
5
I
I
Input Load Current
except ZZ and MODE
GND £ V £ V
mA
X
I
DDQ
Input Current of MODE
Input Current of ZZ
–30
–5
30
2
mA
mA
mA
ZZ
Input = V
SS
I
I
Output Leakage
Current
GND £ V £ V
Output Disabled
–2
OZ
I
DDQ,
V
Operating Supply
V
f = f
= Max., I
= 0 mA,
6.0-ns cycle, 167 MHz
6.7-ns cycle, 150 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
6.0-ns cycle, 167 MHz
6.7-ns cycle, 150 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
All speed grades
350
310
280
250
130
110
95
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD
DD
DD
OUT
CYC
= 1/t
MAX
I
I
Automatic CE
Power-Down
Current—TTL Inputs
Max. V , Device
SB1
DD
Deselected,
V
Š V or V <V
IN
IH
IN
IL
f = f
= 1/t
MAX
CYC
80
Automatic CE
Max. V , Device
30
SB2
DD
Power-Down
Deselected, V < 0.3V or
IN
Current—CMOS Inputs
V
> V
- 0.3V, f = 0
DDQ
IN
Shaded areas contain advance information.
Notes:
9. Minimum voltage equals –2.0V for pulse durations of less than 20 ns
10. A is the temperature.
T
21
CY7C1380A
CY7C1382A
PRELIMINARY
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
Test Conditions
Min.
Max.
100
80
Unit
mA
mA
mA
mA
mA
I
Automatic CE
Power-Down
Current—CMOS Inputs
Max. V , Device
6.0-ns cycle, 167 MHz
6.7-ns cycle, 150 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
All Speeds
SB3
DD
Deselected, or V ≤ 0.3V or
IN
V
> V
− 0.3V
DDQ
IN
f = f
= 1/t
65
MAX
CYC
50
I
Automatic CS
Max. V , Device
20
SB4
DD
Power-Down
Deselected,
Current—TTL Inputs
V
≥ V or V ≤ V , f = 0
IN
IH
IN
IL
Capacitance[11]
Parameter
Description
Input Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
C
C
5
4
8
pF
pF
pF
IN
A
V
V
= 3.3V,
DD
Clock Input Capacitance
Input/Output Capacitance
CLK
I/O
= 2.5V
DDQ
AC Test Loads and Waveforms[12]
R=317
Ω
3.3V
OUTPUT
[10]
OUTPUT
ALL INPUT PULSES
90%
3.0V
90%
10%
Z =50
Ω
0
R =50
10%
1 V/ns
Ω
L
5 pF
GND
R=351
Ω
1 V/ns
≤
≤
= 1.5V
VTH
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
11. Tested initially and after any design or process changes that may affect these parameters.
12. Input waveform should have a slew rate of 1 V/ns.
22
CY7C1380A
CY7C1382A
PRELIMINARY
[13, 14, 15]
Switching Characteristics Over the Operating Range
-167
-150
-133
-100
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Parameter
Description
Clock Cycle Time
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
6.0
2.1
2.1
1.5
0.5
6.7
2.5
2.5
1.5
0.5
7.5
3.0
3.0
1.5
0.5
10.0
3.0
3.0
1.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CYC
CH
Clock HIGH
Clock LOW
CL
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
AS
AH
3.4
3.8
4.2
5.0
CO
1.5
1.5
0.5
1.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
1.5
0
1.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
1.5
0
1.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
1.5
0
DOH
ADS
ADH
WES
WEH
ADVS
ADVH
DS
BWE, GW, BW Set-Up Before CLK Rise 1.5
x
BWE, GW, BW Hold After CLK Rise
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0
x
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip enable Set-Up
DH
CES
CEH
CHZ
CLZ
EOHZ
EOLZ
EOV
Chip enable Hold After CLK Rise
[14]
Clock to High-Z
3.0
3.0
3.5
3.0
3.5
3.5
3.5
4.0
4.0
3.5
4.0
4.0
[14]
Clock to Low-Z
[14, 15]
OE HIGH to Output High-Z
[14, 15]
OE LOW to Output Low-Z
0
0
0
0
[14]
OE LOW to Output Valid
Notes:
13. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
14.
tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
15. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ
.
23
CY7C1380A
CY7C1382A
PRELIMINARY
1
Switching Waveforms
[4, 16, 17]
Write Cycle Timing
Single Write
Burst Write
Pipelined Write
t
Unselected
CH
t
CYC
CLK
t
ADH
t
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
ADSC
ADV
t
ADH
t
ADSC initiated write
ADS
t
t
ADVH
ADVS
t
ADV Must Be Inactive for ADSP Write
WD2
AS
WD1
WD3
ADD
GW
WE
t
AH
t
WH
t
WH
t
WS
t
WS
t
t
CES
CE masks ADSP
CEH
1
CE
1
t
t
CEH
CES
Unselected with CE
2
CE
CE
2
3
t
CES
t
CEH
OE
t
DH
t
DS
High-Z
High-Z
Data In
3a
2a
= UNDEFINED
2d
1a
2b
2c
= DON’T CARE
Notes:
16. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Descriptions table).
17. WDx stands for Write Data to Address X.
24
CY7C1380A
CY7C1382A
PRELIMINARY
Switching Waveforms (continued)
[4, 16, 18]
Read Cycle Timing
Burst Read
Single Read
Unselected
t
t
CYC
CH
Pipelined Read
CLK
t
t
ADH
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
t
ADS
ADSC initiated read
ADSC
ADV
t
ADVS
t
ADH
Suspend Burst
t
t
ADVH
AS
ADD
GW
WE
RD3
RD1
RD2
t
AH
t
WS
t
WS
t
WH
t
t
CES
CEH
t
WH
CE masks ADSP
1
CE
CE
1
2
Unselected with CE
2
t
t
CES
t
CEH
CE
OE
3
CES
t
EOV
t
CEH
t
OEHZ
t
DOH
t
CO
Data Out
2c
1a
2d
3a
2a
2b
t
CLZ
t
CHZ
= DON’T CARE
= UNDEFINED
Note:
18. RDx stands for Read Data from Address X.
25
CY7C1380A
CY7C1382A
PRELIMINARY
Switching Waveforms (continued)
[4, 16, 17, 18]
Read/Write Cycle Timing
Single Read
Single Write
Unselected
Burst Read
t
CYC
t
CH
Pipelined Read
CLK
t
t
ADH
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
ADSC
ADV
t
ADS
t
t
ADVS
ADH
t
AS
t
ADVH
RD1
ADD
WD2
RD3
t
AH
GW
WE
t
WS
t
t
WS
WH
t
CES
t
t
CEH
WH
CE masks ADSP
1
CE
CE
1
2
t
CES
t
CEH
CE
3
t
t
EOV
CES
t
CEH
OE
t
EOHZ
t
t
DS
t
DH
DOH
t
EOLZ
3b
Out
2a
Out
3c
Out
3a
Out
3d
Data In/Out
1a
2a
In
Out
Out
t
CO
t
CHZ
= UNDEFINED
= DON’T CARE
26
CY7C1380A
CY7C1382A
PRELIMINARY
Switching Waveforms (continued)
[4, 19, 20]
Pipeline Timing
t
t
t
CYC
CL
CH
CLK
t
AS
WD1
WD2
WD3
WD4
RD1
RD2
RD3
RD4
ADD
t
t
ADS
ADH
ADSC initiated Reads
ADSC
ADSP initiated Reads
ADSP
ADV
t
t
CEH
CES
CE
1
CE
t
t
WEH
WES
WE
ADSP ignored
with CE HIGH
1
OE
t
t
CLZ
Data In/Out
1a
In
1a
2a
3a
4a
2a
In
3a
In
4a
Out Out Out Out
In
CDV
t
DOH
Back to Back Reads
= DON’T CARE
t
CHZ
= UNDEFINED
Notes:
19. Device originally deselected.
20. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
27
CY7C1380A
CY7C1382A
PRELIMINARY
Switching Waveforms (continued)
OE Switching Waveforms
OE
t
EOV
t
EOHZ
Three-State
I/Os
t
EOLZ
28
CY7C1380A
CY7C1382A
PRELIMINARY
Switching Waveforms (continued)
[4, 21, 22]
ZZ Mode Timing
CLK
ADSP
HIGH
ADSC
CE
1
2
LOW
CE
HIGH
CE
ZZ
3
t
ZZS
I
DD
I
(active)
DD
t
ZZREC
I
DDZZ
I/Os
Three-state
NotefjdfdhfdjfdfjdjdjdjNo
Note:
21. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
22. I/Os are in three-state when exiting ZZ sleep mode.
29
CY7C1380A
CY7C1382A
PRELIMINARY
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
167
150
133
100
167
150
133
100
167
150
133
100
167
150
133
100
Ordering Code
Package Type
100-Lead Thin Quad Flat Pack
CY7C1380A-167AC
CY7C1380A-150AC
CY7C1380A-133AC
CY7C1380A-100AC
CY7C1382A-167AC
CY7C1382A-150AC
CY7C1382A-133AC
CY7C1382A-100AC
CY7C1380A-167BGC
CY7C1380A-150BGC
CY7C1380A-133BGC
CY7C1380A-100BGC
CY7C1382A-167BGC
CY7C1382A-150BGC
CY7C1382A-133BGC
CY7C1382A-100BGC
A101
Commercial
BG119
119 Ball BGA
Document #:38-00984-**
Intel and Pentium are registered trademarks of Intel Corporation.
30
CY7C1380A
CY7C1382A
PRELIMINARY
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
31
CY7C1380A
CY7C1382A
PRELIMINARY
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
Revision History
Document Title: CY7C1380/CY7C1382
Document Number:38-00984
ORIG. OF
REV.
**
ECN NO.
ISSUE DATE
3/16/2000
CHANGE
DESCRIPTION OF CHANGE
1. New Datasheet
CXV
*A
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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Cache SRAM, 1MX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
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