CY7C1382BV25 [CYPRESS]
512K x 36 / 1 Mb x 18 Pipelined SRAM; 512K X 1分之36兆×18 SRAM流水线
| 型号： | CY7C1382BV25 |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 36 / 1 Mb x 18 Pipelined SRAM |
| 文件： | 总30页 (文件大小：838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C1380BV25
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
512K x 36 / 1 Mb x 18 Pipelined SRAM
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), burst control in-
puts (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
Features
• Fast clock speed: 200,166, 150, 133 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns
• Optimal for depth expansion
BWc, BWd and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and Burst
Mode Control (MODE). The data (DQa,b,c,d) and the data par-
ity (DQPa,b,c,d) outputs, enabled by OE, are also asynchro-
nous.
• 2.5V (±5%) Operation
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
DQa,b,c,d and DQPa,b,c,d apply to CY7C1380BV25 and DQa,b
and DQPa,b apply to CY7C1382BV25. a, b, c, d each are of 8
bits wide in the case of DQ and 1 bit wide in the case of DP.
• Address, data, and control registers
• Internally self-timed WRITE CYCLE
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DQPa. BWb controls DQb and DQPb. BWc
controls DQc and DQPd. BWd controls DQd-DQd and DQPd.
BWa, BWb BWc, and BWd can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. WRITE
pass-through capability allows written data available at the out-
put for the immediately next READ cycle. This device also in-
corporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced sin-
gle-layer polysilicon, triple-layer metal technology. Each mem-
ory cell consists of six transistors.
The CY7C1382BV25 and CY7C1380BV25 SRAMs integrate
1,048,576x18 and 524,288x36 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
isters controlled by a positive-edge-triggered clock input
All inputs and outputs of the CY7C1380BV25 and the
CY7C1382BV25 are JEDEC standard JESD8-5 compatible.
Selection Guide
200 MHz
3.0
166 MHz
3.4
150 MHz
3.8
133 MHz
4.2
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
280
230
190
160
Maximum CMOS Standby Current (mA)
30
30
30
30
Shaded areas contain advance information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 5, 2001
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
CY7C1380AV25 - 512K x 36
MODE
2
(A
)
[1;0]
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
17
19
ADDRESS
REGISTER
CE
D
512KX36
MEMORY
ARRAY
A
[18:0]
19
17
GW
DQd, DPd
BYTEWRITE
REGISTERS
D
Q
BWE
BW
d
DQc, DPc
BYTEWRITE
REGISTERS
D
D
D
Q
Q
Q
BW
c
DQb, DPb
BYTEWRITE
REGISTERS
BW
b
DQa, DPa
BYTEWRITE
REGISTERS
BW
a
36
36
CE
2
1
CE
D
D
Q
ENABLE CE
REGISTER
CE
3
Q
OUTPUT
REGISTERS
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
CLK
OE
ZZ
SLEEP
CONTROL
DQ
a,b,c,d
DP
a,b
CY7C1382AV25 - 1M X 18
MODE
2
(A
)
[1;0]
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
17
19
ADDRESS
REGISTER
CE
D
1 Mb X 18
A
[19:0]
19
17
MEMORY
ARRAY
GW
DQb, DPb
BYTEWRITE
REGISTERS
D
Q
BWE
BW
b
DQa, DPa
BYTEWRITE
REGISTERS
D
Q
BW
a
18
18
CE
2
1
CE
D
CE
Q
ENABLE CE
REGISTER
CE
3
D
Q
OUTPUT
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
a,b
a,b
DP
2
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Pin Configurations
100-Pin TQFP
Top View
NC,DQPc
1
NC,DQPb
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DPa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
2
DQc
VDDQ
VSSQ
DQc
3
4
5
6
DQc
7
DQc
8
NC
DQc
9
DQb
DQb
VSSQ
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DPb
NC
VSSQ
10
11
12
9
VDDQ
DQc
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQc
13
NC
14
CY7C1380BV25
(512K X 36)
VDD
15
NC
VDD
ZZ
CY7C1382BV25
(1 Mb x 18)
NC
16
VSS
17
DQd
18
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
NC,DQPa
DQd
19
20
21
VDDQ
VSSQ
DQd
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
22
DQd
23
DQd
24
DQd
25
VSSQ
26
27
28
VDDQ
DQd
DQd
29
NC
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
NC,DQPd
30
3
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Pin Configurations (continued)
CY7C1380BV25 (512K x 36)
1
2
3
4
5
6
7
A
A
A
VDDQ
NC
A
A
A
A
VDDQ
A
A
ADSP
ADSC
VDD
B
C
D
E
F
NC
NC
NC
A
A
A
A
VSS
VSS
VSS
VSS
DQPb
DQb
DQb
DQPc
DQc
NC
DQb
DQb
DQc
DQc
CE1
OE
VSS
VDDQ
DQc
VDDQ
DQb
DQb
VDDQ
DQa
VSS
BWb
VSS
NC
DQb
ADV
GW
VDD
G
H
J
DQc
DQc
VDD
DQd
DQd
BWc
VSS
NC
DQc
DQc
DQb
VDD
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
K
L
VSS
VSS
DQa
DQa
DQa
DQa
DQPa
A
CLK
NC
BWd
VSS
VSS
BWa
VSS
VSS
VSS
DQa
VDDQ
DQa
M
DQd
DQd
BWE
A1
N
P
R
T
DQPd
DQa
VSS
MODE
A
A0
VDD
A
NC
A
A
NC
ZZ
NC
NC
NC
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
CY7C1382BV25 (1 Mb x 18)
1
3
2
4
5
6
7
A
B
C
D
E
F
A
A
A
A
VDDQ
NC
A
A
VDDQ
NC
A
A
ADSP
ADSC
VDD
NC
NC
A
A
A
A
VSS
VSS
VSS
VSS
DQb
NC
NC
NC
DQPa
NC
NC
DQa
VDDQ
DQa
NC
DQb
CE1
OE
VSS
DQa
VDDQ
NC
VSS
VSS
VSS
NC
NC
ADV
GW
VDD
G
H
J
DQb
NC
BWb
VSS
NC
NC
DQb
DQa
VDD
VDDQ
DQa
VDDQ
NC
VDD
DQb
NC
K
L
VSS
NC
DQa
NC
DQa
NC
A
VSS
VSS
CLK
NC
DQb
VDDQ
DQb
NC
BWa
VSS
VSS
NC
VDDQ
NC
M
DQb
NC
BWE
A1
VSS
VSS
N
P
R
T
DQPb
DQa
VSS
MODE
A
A0
VDD
NC
VSS
NC
A
NC
A
A
NC
ZZ
A
NC
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
4
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Pin Definitions
Name
I/O
Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and
CE3 are sampled active. A[1:0] feed the 2-bit counter.
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless of
the values on BWa,b,c,d and BWE).
BWE
CLK
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ig-
nored if CE1 is HIGH.
CE2
CE3
OE
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE3 to select/deselect the device. (TQFP Only)
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE2 to select/deselect the device. (TQFP Only)
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH,
I/O pins are three-stated, and act as input data pins. OE is masked during the
first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When
asserted LOW, A is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When
asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized.
MODE
ZZ
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to VDDQ or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation.
Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved.
DQa, DQPa
DQb, DQPb
DQc, DQPc
DQd, DQPd
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A during the previous clock rise
of the read cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are
placed in a three-state condition.
TDO
TDI
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK
(BGA Only).
JTAG serial
input
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA
Only).
Synchronous
5
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Pin Definitions
Name
I/O
Description
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising
edge of TCK (BGA Only).
TCK
VDD
JTAG serial
clock
Serial clock to the JTAG circuit (BGA Only).
Power Supply
Power supply inputs to the core of the device. Should be connected to 3.3V
–5% +10% power supply.
VSS
Ground
Ground for the core of the device. Should be connected to ground of the sys-
tem.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry. Should be connected to a 3.3V –5% +10%
power supply.
VSSQ
NC
I/O Ground
-
Ground for the I/O circuitry. Should be connected to ground of the system.
No Connects.
6
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
ed into the address register and the address advancement
logic while being delivered to the RAM core. The write signals
(GW, BWE, and BWx) and ADV inputs are ignored during this
first cycle.
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise (tCO) is 3.8 ns (133-MHz
device).
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx sig-
nals. The CY7C1380BV25/CY7C1382BV25 provides byte
write capability that is described in the write cycle description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write (BWa,b,c,d for CY7C1380BV25 & BWa,b for
CY7C1382BV25) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
The CY7C1380BV25/CY7C1382BV25 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486 processors. The linear burst sequence is suited for pro-
cessors that utilize a linear burst sequence. The burst order is
user selectable, and is determined by sampling the MODE in-
put. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Because the CY7C1380BV25/CY7C1382BV25 is a common
I/O device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for 1380V25 and
BWa,b for 1382V25) inputs. A Global Write Enable (GW) over-
rides all byte write inputs and writes data to all four bytes. All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BWx) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented to A[17:0] is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is ig-
nored during this cycle. If a global write is conducted, the data
presented to the DQ[x:0] is written into the corresponding ad-
dress location in the RAM core. If a byte write is conducted,
only the selected bytes are written. Bytes not selected during
a byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for
BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. ADSP is
ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.0 ns (200-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Because the CY7C1380BV25/CY7C1382BV25 is a common
I/O device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ[x:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[x:0]
are automatically three-stated whenever a write cycle is de-
tected, regardless of the state of OE.
Burst Sequences
The CY7C1380BV25/CY7C1382BV25 provides a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst se-
quence is designed specifically to support Intel® Pentium®
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst se-
quence is user selectable through the MODE input.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is load-
7
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Interleaved Burst Sequence
A[1:0]
A[1:0]
A[1:0]
A[1:0]
First
Second
Third
Fourth
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Address
Address
Address
Address
A[1:0]]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CEs, ADSP, and ADSC must remain inactive for the duration
of tZZREC after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Test Conditions
Min.
Max.
Unit
Snooze mode
standby current
ZZ > VDD − 0.2V
15
mA
tZZS
Deviceoperationto
ZZ
ZZ > VDD − 0.2V
ZZ < 0.2V
2tCYC
ns
ns
tZZREC
ZZ recovery time
2tCYC
8
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Cycle Descriptions[1, 2, 3, 4]
Next Cycle
Unselected
Add. Used
None
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
CE3
X
1
CE2
X
X
0
CE1
1
ADSP
X
0
ADSC
ADV
X
X
X
X
X
X
X
0
OE
X
X
X
X
X
X
X
1
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Write
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
X
Unselected
None
0
X
Unselected
None
X
1
0
0
X
Unselected
None
X
0
0
1
X
Unselected
None
X
0
0
1
X
Begin Read
External
External
Next
1
0
0
X
Begin Read
0
1
0
1
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
1
X
X
1
1
Next
1
0
0
Next
X
X
1
0
1
Hi-Z
DQ
Next
1
0
0
Current
Current
Current
Current
Current
Current
External
Next
X
X
1
1
1
Hi-Z
DQ
1
1
0
X
X
1
1
1
Hi-Z
DQ
1
1
0
X
1
1
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Begin Write
X
1
1
Begin Write
0
X
0
Continue Write
Continue Write
Suspend Write
Suspend Write
X
X
X
X
X
X
X
X
X
X
X
1
1
Next
X
1
0
Current
Current
None
X
1
1
X
X
1
ZZ “sleep”
X
X
Note:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. CE1, CE2 and CE3 are available only in the TQFP package. BGA package has a single chip select CE1.
9
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Write Cycle Descriptions[5, 6, 7]
Function (1380AV25)
Read
GW
1
BWE
BWd
X
1
BWc
X
1
BWb
X
1
BWa
X
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
Read
1
Write Byte 0 - DQa
Write Byte 1 - DQb
Write Bytes 1, 0
Write Byte 2 - DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 - DQd
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
1
1
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
0
1
1
0
0
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
0
0
0
1
1
0
0
0
0
Write All Bytes
0
X
X
X
X
Function (1382AV25)
Read
GW
BWE
BWb
BWa
1
1
1
1
1
0
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
Read
Write Byte 0 - DQ[7:0] and DP0
Write Byte 1 - DQ[15:8] and DP1
Write All Bytes
Write All Bytes
10
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
ry. Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1380BV25/CY7C1382BV25 incorporates a serial
boundary scan Test Access Port (TAP) in the FBGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1-1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruc-
tion register. This register is loaded when it is placed between
the TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as de-
scribed in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow
for fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port (TAP) - Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a xx-bit-long regis-
ter, and the x18 configuration has a yy-bit-long register.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the regis-
ters and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruc-
tion that is loaded into the TAP instruction register. For infor-
mation on loading the instruction register, see the TAP Control-
ler State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is con-
nected to the Most Significant Bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Defi-
nitions table.
The TDO output pin is used to serially clock data-out from the
registers. The e output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO
comes up in a high-Z state.
Eight different instructions are possible with the three-bit in-
struction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RE-
SERVED and should not be used. The other five instructions
are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller can-
not be used to load address, data or control signals into the
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuit-
11
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE / PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
When the SAMPLE / PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible
that during the Capture-DR state, an input or output will under-
go a transition. The TAP may then try to capture a signal while
in transition (metastable state). This will not harm the device,
but there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP control-
ler needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be ex-
ecuted whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in the TAP controller, and there-
fore this device is not compliant to the 1149.1 standard.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK captured in the
boundary scan register.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE / PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE / PRELOAD instruction, EX-
TEST places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP con-
troller enters the Shift-DR state. The IDCODE instruction is
loaded into the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE / PRELOAD in-
struction will have the same effect as the Pause-DR command.
Bypass
When the BYPASS instruction is loaded in the instruction reg-
ister and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The advan-
tage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a
board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Reserved
SAMPLE / PRELOAD
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
12
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
TAP Controller State Diagram
TEST-LOGIC
1
RESET
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
13
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
TDO
2
1
0
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[5, 6]
Parameter
VOH1
VOH2
VOL1
Description
Test Conditions
Min.
1.7
Max.
Unit
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOH = –2.0 mA
IOH = –100 mA
IOL = 2.0 mA
IOL = 100 mA
2.1
V
0.7
0.2
V
VOL2
V
VIH
1.7
–0.3
–5
VDD+0.3
0.7
V
VIL
V
IX
GND < VI < VDDQ
5
mA
Notes:
5. All Voltage referenced to Ground.
6. Overshoot: VIH(AC)<VDD+1.5V for t<tTCYC/2. Undershoot:VIL(AC)<0.5V for t<tTCYC/2. Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V for t<200 ms.
14
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[7, 8]
Parameters
tTCYC
Description
Min.
Max.
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
tTF
10
MHz
ns
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
tTDOX
0
Notes:
7. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
8. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
15
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
TAP Timing and Test Conditions
1.25V
50Ω
ALL INPUT PULSES
TDO
2.5V
Z =50Ω
0
1.25V
C =20 pF
L
0V
GND
(a)
tTL
tTH
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
16
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Identification Register Definitions
Instruction Field
Revision Number
512K x 36
1 Mb x 18
Description
xxxx
xxxx
Reserved for version number.
(31:28)
Device Depth
(27:23)
00111
01000
Defines depth of SRAM. 512K or 1 Mb
Defines with of the SRAM. x36 or x18
Reserved for future use.
Device Width
(22:18)
00100
00011
Cypress Device ID
(17:12)
xxxxx
xxxxx
Cypress JEDEC ID
(11:1)
00011100100
1
00011100100
1
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
ID Register Presence
(0)
Scan Register Sizes
Register Name
Instruction
Bit Size (x18)
Bit Size (x36)
3
1
3
1
Bypass
ID
32
70
32
51
Boundary Scan
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register be-
tween TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
Captures the Input/Output contents. Places the boundary scan register be-
tween TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction
does not implement 1149.1 preload function and is therefore not 1149.1
compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
17
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Boundary Scan Order (512K X 18)
Boundary Scan Order (1 Mb X 18)
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Bit #
Bit #
36
Bit #
Bit #
36
1
A
2R
A
6B
1
A
2R
DQb
2E
2
A
3T
4T
5T
6R
3B
5B
6P
7N
6M
7L
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
BWa
BWb
BWc
BWd
A
5L
2
A
2T
3T
5T
6R
3B
5B
7P
6N
6L
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
DQb
DQb
NC
2G
1H
5R
2K
1L
3
A
5G
3G
3L
3
A
4
A
4
A
5
A
5
A
DQb
DQb
DQb
DQb
DQb
MODE
A
6
A
2B
4E
3A
2A
2D
1E
2F
1G
1D
1D
2E
2G
1H
5R
2K
1L
6
A
7
A
CE
7
A
2M
1N
2P
3R
2C
3C
5C
6C
4N
4P
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
A
8
DQa
DQa
DQa
DQa
ZZ
9
A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
7K
7T
6H
7G
6F
7E
6D
6T
6A
5A
4G
4A
4B
4F
4M
4H
4K
6B
5L
6K
7P
6N
6L
A
DQa
DQa
DQa
DQa
DQa
A
A
A
A1
7K
7T
6H
7G
6F
7E
6D
7H
6G
6E
7D
6A
5A
4G
4A
4B
4F
4M
4H
4K
A0
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
A
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
A
ADV
ADSP
ADSC
OE
BWE
GW
CLK
A
2M
1N
2P
1K
2L
2N
1P
3R
2C
3C
5C
6C
4N
4P
A
ADV
ADSP
ADSC
OE
BWa
BWb
A
3G
2B
4E
3A
2A
1D
A
A
CE
A
BWE
GW
CLK
A
A1
A
A0
DQb
18
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–55°C to +150°C
Latch-Up Current.................................................... >200 mA
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
Range
Temp.[9]
VDD
VDDQ
DC Voltage Applied to Outputs
in High Z State[9]................................. –0.5V to VDDQ + 0.5V
Com’l
0−70°C
2.5V +10%/–5%
2.375V – VDD
DC Input Voltage[9].............................. –0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
Max. Unit
3.3V range
3.3V range
2.5V range
3.135
3.135
2.375
1.7
3.6
3.6
V
V
V
V
VDDQ
VDD
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[9]
VDD = Min., IOH = −1.0 mA
2.5V
2.5V
2.5V
2.5V
VDD = Min., IOL = 1.0 mA
0.7
1.7
–0.3
−5
0.7
5
Input Load Current
GND ≤ VI ≤ VDDQ
µA
except ZZ and MODE
IZZ
Input Current of MODE
Input Current of ZZ
Input = VSS
−30
−5
30
µA
µA
IOZ
IDD
Output Leakage Current
VDD Operating Supply
GND ≤ VI ≤ VDDQ, Output Disabled
−2
2
µA
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
5.0-ns cycle, 200 MHz
6.0-ns cycle, 166 MHz
6.7-ns cycle, 150 MHz
7.5-ns cycle, 133 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 166 MHz
6.7-ns cycle, 150 MHz
7.5-ns cycle, 133 MHz
All speed grades
280
230
190
160
100
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
AutomaticCEPower-Down Max. VDD, Device Deselected,
Current—TTL Inputs IN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
V
50
35
ISB2
AutomaticCEPower-Down Max. VDD, Device Deselected,
Current—CMOS Inputs IN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0
30
V
ISB3
AutomaticCEPower-Down Max. VDD, Device Deselected, or 5.0-ns cycle, 200 MHz
90
70
40
25
50
mA
mA
mA
mA
mA
Current—CMOS Inputs
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
6.0-ns cycle, 166 MHz
6.7-ns cycle, 150 MHz
7.5-ns cycle, 133 MHz
All Speeds
ISB4
AutomaticCEPower-Down Max. VDD, Device Deselected,
Current—TTL Inputs IN ≥ VIH or VIN ≤ VIL, f = 0
V
Shaded areas contain advance information.
Notes:
9. Minimum voltage equals –2.0V for pulse durations of less than 20 ns TA is the temperature.
19
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Capacitance[10]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
DD = 3.3V,
DDQ = 2.5V
3
3
3
V
V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
AC Test Loads and Waveforms[11]
R=1667Ω
2.5V
OUTPUT
[10]
OUTPUT
ALL INPUT PULSES
90%
2.5V
GND
90%
10%
Z =50Ω
0
R =50Ω
10%
L
5 pF
R=1538Ω
≤ 2.5 ns
≤ 2.5 ns
= 1.25V
VTH
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
10. Tested initially and after any design or process changes that may affect these parameters.
11. Input waveform should have a slew rate of 1 V/ns.
20
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Switching Characteristics Over the Operating Range[12, 13, 14]
-200
a-166
-150
-133
Parameter
tCYC
tCH
Description
Clock Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit
5.0
1.8
1.8
1.4
0.4
6.0
2.1
2.1
1.5
0.5
6.7
2.5
2.5
1.5
0.5
7.5
3.0
3.0
1.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock HIGH
tCL
Clock LOW
tAS
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
tAH
tCO
3.0
3.4
3.8
4.2
tDOH
tADS
tADH
tWES
tWEH
tADVS
tADVH
tDS
1.5
1.4
0.4
1.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
1.5
0
1.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
1.5
0
1.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
1.5
0
BWE, GW, BWx Set-Up Before CLK Rise 1.4
BWE, GW, BWx Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.5
0
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip enable Set-Up
tDH
tCES
tCEH
tCHZ
tCLZ
Chip enable Hold After CLK Rise
Clock to High-Z[13]
Clock to Low-Z[13]
OE HIGH to Output High-Z[13, 14]
OE LOW to Output Low-Z[13, 14]
OE LOW to Output Valid[13]
3.0
3.0
3.5
3.0
3.5
3.5
3.5
4.0
4.0
3.5
4.0
4.0
tEOHZ
tEOLZ
tEOV
0
0
0
0
Shaded areas contain advance information.
Notes:
12. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC test loads.
13. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
14. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ
.
a.
21
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
1
Switching Waveforms
Write Cycle Timing[4, 15, 16]
Single Write
tCYC
tADH
Burst Write
Pipelined Write
tCH
Unselected
CLK
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADH
tADS
ADSC initiated write
tADVH
tADVS
tAS
ADV Must Be Inactive for ADSP Write
WD3
ADD
GW
WE
WD1
WD2
tAH
tWH
tWH
tWS
tWS
tCES
tCEH
CE1 masks ADSP
CE
1
tCEH
tCES
Unselected with CE2
CE
2
CE
3
tCES
tCEH
OE
tDH
tDS
High-Z
High-Z
Data
In
3a
2a
1a
2b
2c
2d
= DON’T CARE
= UNDEFINED
Notes:
15. WE is the combination of BWE, BWx and GW to define a write cycle (see Write Cycle Descriptions table).
16. WDx stands for Write Data to Address X.
22
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Switching Waveforms (continued)
Read Cycle Timing[4, 15, 17]
Burst Read
Single Read
tCYC
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
ADV
tADVS
tADH
Suspend Burst
tADVH
tAS
ADD
GW
RD1
RD3
RD2
tAH
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
OE
tCES
tEOV
tCEH
tOEHZ
tDOH
tCO
Data Out
2c
1a
2d
3a
2a
2b
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
17. RDx stands for Read Data from Address X.
23
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[4, 15, 16, 17]
Single Read
tCYC
Single Write
tCH
Unselected
Burst Read
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADS
tADVS
tADH
tAS
tADVH
WD2
ADD
RD1
RD3
tAH
GW
WE
CE1
tWS
tWS
tWH
tCES
tCEH
tWH
CE1 masks ADSP
CE2
CE3
tCES
tCEH
tEOV
tCES
tCEH
OE
tEOHZ
tDS
tDH
tDOH
tEOLZ
tCO
2a
Out
3b
Out
3c
Out
3a
Out
3d
Out
Data In/Out
1a
2a
In
Out
tCHZ
= UNDEFINED
= DON’T CARE
24
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Switching Waveforms (continued)
Pipeline Timing[4, 18, 19]
tCYC
tCL
tCH
CLK
tAS
WD1
WD2
WD3
WD4
RD1
RD2
RD3
RD4
ADD
tADS
tADH
ADSC initiated Reads
ADSC
ADSP initiated Reads
ADSP
ADV
tCEH
tCES
CE1
CE
tWES
tWEH
WE
OE
ADSP ignored
with CE1 HIGH
tCLZ
Data In/Out
1a
In
1a
2a
3a
4a
2a
In
3a
In
4a
Out Out Out Out
In
tCDV
tDOH
Back to Back Reads
tCHZ
= UNDEFINED
= DON’T CARE
Notes:
18. Device originally deselected.
19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
25
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Switching Waveforms (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
Three-State
I/Os
tEOLZ
26
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Switching Waveforms (continued)
ZZ Mode Timing [4, 20, 21]
CLK
ADSP
HIGH
ADSC
CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
IDD
IDD(active)
tZZREC
IDDZZ
I/Os
Three-state
Note:
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
21. I/Os are in three-state when exiting ZZ sleep mode.
27
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
200
166
150
133
200
166
150
133
200
166
150
133
200
166
150
133
Ordering Code
Package Type
100-Lead Thin Quad Flat Pack
CY7C1380BV25-200AC
CY7C1380BV25-166AC
CY7C1380BV25-150AC
CY7C1380BV25-133AC
CY7C1380BV25-200BGC
CY7C1380BV25-166BGC
CY7C1380BV25-150BGC
CY7C1380BV25-133BGC
CY7C1382BV25-200AC
CY7C1382BV25-166AC
CY7C1382BV25-150AC
CY7C1382BV25-133AC
CY7C1382BV25-200BGC
CY7C1382BV25-166BGC
CY7C1382BV25-150BGC
CY7C1382BV25-133BGC
A101
BG119
A101
Commercial
119 Ball BGA
100-Lead Thin Quad Flat Pack
Commercial
BG119
119 Ball BGA
Shaded areas contain advance information.
Document #: 38-01075-*A
28
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
29
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4 mm) BG119
51-85115
Revision History
Document Title: CY7C1380BV25/CY7C1382BV25
Document Number: 38-01075
ORIG. OF
REV.
**
ECN NO.
ISSUE DATE
9/30/2000
05/04/01
CHANGE
DESCRIPTION OF CHANGE
1. New Data Sheet
MPR
*A
3771
PKS
1.Changed Vih/Vil values
2. Changed Icc Values
3. Changed Pin Capacitance values
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号：
CY7C1382BV25-167AC
Cache SRAM, 1MX18, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
©2020 ICPDF网 联系我们和版权申明