CY7C1382DV25-200AC [CYPRESS]

Cache SRAM, 1MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
CY7C1382DV25-200AC
型号: CY7C1382DV25-200AC
厂家: CYPRESS    CYPRESS
描述:

Cache SRAM, 1MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

静态存储器
文件: 总30页 (文件大小:789K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
18-Mbit (512K x 36/1M x 18) Pipelined SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 250 MHz  
The CY7C1380DV25/CY7C1382DV25 SRAM integrates  
524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced  
synchronous peripheral circuitry and a two-bit counter for  
internal burst operation. All synchronous inputs are gated by  
registers controlled by a positive-edge-triggered Clock Input  
(CLK). The synchronous inputs include all addresses, all data  
inputs, address-pipelining Chip Enabl[e2] (CE1), depth-  
expansion Chip Enables (CE2 and CE3 ), Burst Control  
inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and  
BWE), and Global Write (GW). Asynchronous inputs include  
the Output Enable (OE) and the ZZ pin.  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
• Available speed grades are 250, 225, 200,167, and  
133 MHz  
• Registered inputs and outputs for pipelined operation  
• 2.5V core power supply  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
— 2.8 ns (for 225-MHz device)  
— 3.0 ns (for 200-MHz device)  
— 3.4 ns (for 167-MHz device)  
— 4.2 ns (for 133-MHz device)  
• Provide high-performance 3-1-1-1 access rate  
User-selectable burst counter supporting Intel®  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two or four bytes wide as  
controlled by the byte write control inputs. GW when active  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
causes all bytes to be written.  
LOW  
• Single Cycle Chip Deselect  
The CY7C1380DV25/CY7C1382DV25 operates from a +2.5V  
core power supply while all outputs may operate with a +2.5  
supply. All inputs and outputs are JEDEC-standard JESD8-5-  
compatible.  
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA  
and 165-ball fBGA packages  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
Selection Guide  
250 MHz  
225 MHz  
2.8  
200 MHz  
3.0  
167 MHz  
3.4  
133 MHz  
4.2  
Unit  
ns  
mA  
mA  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
2.6  
350  
70  
325  
70  
300  
70  
275  
70  
245  
70  
Shaded areas contain advance information.  
Please contact your local Cypress sales representative for availability of these parts.  
Notes:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE , CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.  
3
2
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-05546 Rev. **  
Revised August 12, 2004  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
1
Logic Block Diagram – CY7C1380DV25 (512K x 36)  
A0, A1, A  
ADDRESS  
REGISTER  
2
A[1:0]  
MODE  
Q1  
ADV  
CLK  
BURST  
COUNTER  
AND  
CLR  
Q0  
LOGIC  
ADSC  
ADSP  
DQ  
BYTE  
WRITE REGISTER  
D ,DQPD  
DQ  
BYTE  
WRITE DRIVER  
D ,DQPD  
BW  
D
DQC ,DQP  
BYTE  
WRITE DRIVER  
C
DQC ,DQP  
BYTE  
WRITE REGISTER  
C
BW  
C
OUTPUT  
BUFFERS  
OUTPUT  
REGISTERS  
MEMORY  
ARRAY  
DQ s  
SENSE  
AMPS  
DQPA  
DQB ,DQP  
BYTE  
WRITE DRIVER  
B
E
DQB ,DQP  
BYTE  
WRITE REGISTER  
B
DQP  
DQP  
B
C
BW  
BW  
B
A
DQPD  
DQ  
BYTE  
WRITE DRIVER  
A ,DQPA  
DQ  
A ,DQPA  
BYTE  
WRITE REGISTER  
BWE  
INPUT  
REGISTERS  
GW  
ENABLE  
REGISTER  
PIPELINED  
ENABLE  
CE  
CE  
CE  
1
2
3
OE  
SLEEP  
CONTROL  
ZZ  
2
Logic Block Diagram – CY7C1382DV25 (1M x 18)  
ADDRESS  
A0, A1, A  
REGISTER  
A[1:0]  
2
MODE  
Q1  
ADV  
CLK  
BURST  
COUNTER AND  
LOGIC  
CLR  
Q0  
ADSC  
ADSP  
DQB,DQP  
B
DQB,DQP  
WRITE REGISTER  
B
WRITE DRIVER  
OUTPUT  
BUFFERS  
BW  
B
A
DQs  
DQP  
DQP  
OUTPUT  
REGISTERS  
SENSE  
AMPS  
MEMORY  
ARRAY  
A
B
DQA,DQP  
A
E
DQA,DQP  
WRITE REGISTER  
A
WRITE DRIVER  
BW  
BWE  
GW  
INPUT  
REGISTERS  
ENABLE  
REGISTER  
CE1  
CE2  
PIPELINED  
ENABLE  
CE3  
OE  
ZZ  
SLEEP  
CONTROL  
Document #: 38-05546 Rev. **  
Page 2 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Pin Configurations  
100-pin TQFP Pinout  
DQPC  
1
DQP  
B
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
NC  
A
1
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQC  
DQB  
B
2
NC  
2
DQc  
VDDQ  
VSSQ  
DQ  
3
NC  
NC  
3
VDDQ  
4
VDDQ  
VSSQ  
NC  
VDDQ  
VSSQ  
NC  
4
VSSQ  
5
5
DQ  
DQ  
DQ  
C
DQ  
DQ  
DQ  
DQ  
B
B
B
B
6
6
C
C
7
NC  
DQP  
A
7
8
DQ  
B
B
DQ  
A
A
8
DQ  
C
9
DQ  
DQ  
9
VSSQ  
VDDQ  
VSSQ  
VDDBQ  
DQ  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VSSQ  
VSSQ  
VDDAQ  
DQ  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VDDQ  
DQ  
C
DQ  
B
B
DQ  
C
DQ  
B
DQ  
DQ  
A
NC  
VDD  
NC  
VSS  
NC  
VDD  
ZZ  
NC  
VDD  
NC  
VSS  
NC  
VDD  
ZZ  
CY7C1382DV25  
(1M x 18)  
CY7C1380DV25  
(512K X 36)  
VSDS  
VSBS  
DQ  
DQ  
A
DQ  
DQ  
A
A
DQ  
D
DQA  
DQ  
B
DQ  
VDDQ  
VSSQ  
VDDQ  
VSSQ  
VDDQ  
VSSQ  
VDDQ  
VSSQ  
DQ  
D
DQ  
DQ  
DQ  
DQ  
A
A
A
A
DQ  
B
B
B
DQ  
DQ  
NC  
NC  
A
A
DQ  
D
DQ  
DQ  
D
DQP  
DQ  
D
NC  
VSSQ  
VDDQ  
NC  
VSSQ  
VDDQ  
VSSQ  
VDDAQ  
DQ  
VSSQ  
VDDQ  
NC  
DQ  
D
DQ  
D
DQA  
NC  
NC  
DQPD  
DQP  
A
NC  
NC  
Document #: 38-05546 Rev. **  
Page 3 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Pin Configurations (continued)  
119-ball BGA (1 Chip Enable with JTAG)  
CY7C1380DV25 (512K x 36)  
1
2
3
4
5
6
7
VDDQ  
A
A
A
A
VDDQ  
A
B
C
ADSP  
ADSC  
VDD  
NC  
NC  
A
A
A
A
A
A
A
A
NC  
NC  
DQC  
DQC  
VDDQ  
DQPC  
DQC  
DQC  
VSS  
VSS  
VSS  
NC  
CE1  
VSS  
VSS  
VSS  
DQPB  
DQB  
DQB  
DQB  
DQB  
VDDQ  
D
E
F
OE  
DQC  
DQC  
VDDQ  
DQD  
DQD  
VDDQ  
DQD  
DQC  
DQC  
VDD  
BWC  
VSS  
NC  
BWB  
VSS  
NC  
DQB  
DQB  
VDD  
DQA  
DQA  
DQA  
DQA  
DQB  
DQB  
VDDQ  
DQA  
DQA  
VDDQ  
DQA  
G
H
J
ADV  
GW  
VDD  
CLK  
NC  
BWE  
A1  
DQD  
VSS  
VSS  
K
L
M
N
DQD  
DQD  
DQD  
BWD  
VSS  
VSS  
BWA  
VSS  
VSS  
P
R
DQD  
NC  
DQPD  
A
VSS  
MODE  
A0  
VDD  
VSS  
NC  
DQPA  
A
DQA  
NC  
T
U
NC  
VDDQ  
NC / 72M  
TMS  
A
TDI  
A
TCK  
A
TDO  
NC / 36M  
NC  
ZZ  
VDDQ  
CY7C1382DV25 (512K x 18)  
2
A
A
1
3
A
A
4
5
A
A
6
A
A
7
A
B
C
D
E
F
VDDQ  
NC  
NC  
DQB  
NC  
VDDQ  
VDDQ  
NC  
NC  
NC  
DQA  
VDDQ  
ADSP  
ADSC  
VDD  
NC  
CE1  
A
A
A
A
NC  
DQB  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
DQPA  
NC  
DQA  
OE  
G
H
J
NC  
DQB  
VDDQ  
DQB  
NC  
VDD  
NC  
VSS  
NC  
NC  
DQA  
VDD  
DQA  
NC  
VDDQ  
BWB  
VSS  
NC  
ADV  
GW  
VDD  
NC  
DQB  
VSS  
CLK  
NC  
BWE  
A1  
VSS  
NC  
DQA  
NC  
DQA  
NC  
DQA  
K
L
M
N
P
DQB  
VDDQ  
DQB  
NC  
NC  
DQB  
NC  
NC  
VSS  
VSS  
VSS  
NC  
VDDQ  
NC  
BWA  
VSS  
VSS  
VSS  
DQPB  
A0  
DQA  
R
T
U
NC  
NC / 72M  
VDDQ  
A
A
TMS  
MODE  
A
TDI  
VDD  
NC / 36M  
TCK  
NC  
A
TDO  
A
A
NC  
NC  
ZZ  
VDDQ  
Document #: 38-05546 Rev. **  
Page 4 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Pin Configurations (continued)  
165-ball fBGA  
CY7C1380DV25 (512K x 36)  
1
NC / 288M  
NC  
DQPC  
DQC  
2
3
4
5
6
7
8
9
10  
11  
NC  
NC / 144M  
DQPB  
DQB  
A
A
B
C
D
E
F
G
H
J
K
L
CE1  
BWC  
BWD  
VSS  
VDD  
BWB  
BWA  
VSS  
VSS  
CE3  
CLK  
VSS  
VSS  
ADSC  
A
BWE  
GW  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
ADV  
ADSP  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
A
NC  
DQC  
DQC  
DQC  
DQC  
NC  
DQD  
DQD  
DQD  
CE2  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
VDDQ  
VDDQ  
VDDQ  
A
NC  
DQB  
DQB  
DQB  
DQB  
NC  
DQA  
DQA  
DQA  
OE  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
DQC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
DQB  
DQC  
DQC  
NC  
DQD  
DQD  
DQD  
DQB  
DQB  
ZZ  
DQA  
DQA  
DQA  
VDDQ  
VDDQ  
VDDQ  
DQD  
DQPD  
NC  
DQD  
NC  
NC / 72M  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
TDI  
VSS  
A
A1  
VSS  
NC  
TDO  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
DQA  
DQPA  
A
M
N
P
A0  
MODE NC / 36M  
A
A
TMS  
TCK  
A
A
A
A
R
CY7C1382DV25 (1M x 18)  
1
NC / 288M  
NC  
2
3
CE1  
CE2  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
4
BWB  
NC  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
5
6
7
8
9
10  
11  
A
A
NC  
A
A
CE  
BWE  
GW  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
ADSC  
OE  
VSS  
ADV  
ADSP  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
3
A
NC  
DQB  
DQB  
DQB  
DQB  
NC  
NC  
NC  
BWA  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
CLK  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
A
NC  
NC  
NC  
NC  
NC  
NC / 144M  
DQPA  
DQA  
B
C
D
E
F
G
H
J
K
L
NC  
NC  
NC  
NC  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
DQA  
DQA  
DQA  
ZZ  
NC  
NC  
NC  
NC  
DQB  
DQB  
DQB  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQA  
DQA  
DQA  
NC  
NC  
DQB  
DQPB  
NC  
NC  
NC  
NC / 72M  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
TDI  
VSS  
A
A1  
VSS  
NC  
TDO  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
NC  
NC  
A
M
N
P
MODE NC / 36M  
A
A
TMS  
A0  
TCK  
A
A
A
A
R
Document #: 38-05546 Rev. **  
Page 5 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Pin Definitions  
Name  
I/O  
Description  
A0, A1, A  
Input-  
Address Inputs used to select one of the address locations. Sampled at  
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2,  
and CE3[2]are sampled active. A1: A0 are fed to the two-bit counter.  
Synchronous  
BWA, BWB  
BWC, BWD  
Input-  
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte  
Synchronous  
writes to the SRAM. Sampled on the rising edge of CLK.  
GW  
Input-  
Global Write Enable Input, active LOW. When asserted LOW on the rising  
edge of CLK, a global write is conducted (ALL bytes are written, regardless  
of the values on BWX and BWE).  
Synchronous  
BWE  
CLK  
Input-  
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK.  
Synchronous  
This signal must be asserted LOW to conduct a byte write.  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. Also used  
to increment the burst counter when ADV is asserted LOW, during a burst  
operation.  
CE1  
Input-  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used  
in conjunction with CE2 and CE3 to select/deselect the device. ADSP is  
ignored if CE1 is HIGH.  
Synchronous  
[2]  
CE2  
Input-  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used  
Synchronous  
in conjunction with CE1 and CE3 to select/deselect the device.  
[2]  
CE3  
Input-  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used  
in conjunction with CE1 and CE2 to select/deselect the device.Not available  
for AJ package version. Not connected for BGA. Where referenced, CE3 is  
assumed active throughout this document for BGA.  
Synchronous  
OE  
Input-  
Output Enable, asynchronous input, active LOW. Controls the direction of  
the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted  
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during  
the first clock of a read cycle when emerging from a deselected state.  
Asynchronous  
ADV  
Input-  
Advance Input signal, sampled on the rising edge of CLK, active LOW.  
Synchronous  
When asserted, it automatically increments the address in a burst cycle.  
ADSP  
Input-  
Address Strobe from Processor, sampled on the rising edge of CLK,  
active LOW. When asserted LOW, addresses presented to the device are  
captured in the address registers. A1: A0 are also loaded into the burst  
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.  
ASDP is ignored when CE1 is deasserted HIGH.  
Synchronous  
ADSC  
Input-  
Address Strobe from Controller, sampled on the rising edge of CLK,  
active LOW. When asserted LOW, addresses presented to the device are  
captured in the address registers. A1: A0 are also loaded into the burst  
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.  
Synchronous  
ZZ  
Input-  
ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in  
a non-time-critical “sleep” condition with data integrity preserved. For normal  
operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-  
down.  
Asynchronous  
I/O-  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register  
that is triggered by the rising edge of CLK. As outputs, they deliver the data  
contained in the memory location specified by the addresses presented  
during the previous clock rise of the read cycle. The direction of the pins is  
controlled by OE. When OE is asserted LOW, the pins behave as outputs.  
When HIGH, DQs and DQPX are placed in a tri-state condition.  
DQs, DQPX  
Synchronous  
VDD  
VSS  
Power Supply  
Ground  
Power supply inputs to the core of the device.  
Ground for the core of the device.  
Document #: 38-05546 Rev. **  
Page 6 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Pin Definitions (continued)  
Name  
I/O  
Description  
VSSQ  
I/O Ground  
Ground for the I/O circuitry.  
VDDQ  
I/O Power Supply  
Power supply for the I/O circuitry.  
MODE  
Input-  
Static  
Selects Burst Order. When tied to GND selects linear burst sequence. When  
tied to VDD or left floating selects interleaved burst sequence. This is a strap  
pin and should remainstatic during device operation. ModePin has an internal  
pull-up.  
TDO  
TDI  
JTAG serial output  
Synchronous  
Serial data-out to the JTAG circuit. Delivers data on the negative edge of  
TCK. If the JTAG feature is not being utilized, this pin should be disconnected.  
This pin is not available on TQFP packages.  
JTAG serial  
input  
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the  
JTAG feature is not being utilized, this pin can be disconnected or connected  
to VDD. This pin is not available on TQFP packages.  
Synchronous  
TMS  
JTAG serial  
input  
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the  
JTAG feature is not being utilized, this pin can be disconnected or connected  
to VDD. This pin is not available on TQFP packages.  
Synchronous  
TCK  
NC  
JTAG-Clock  
-
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized,  
this pin must be connected to VSS. This pin is not available on TQFP  
packages.  
No Connects. Not internally connected to the die  
Document #: 38-05546 Rev. **  
Page 7 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
memory array. The Write signals (GW, BWE, and BWX) and  
ADV inputs are ignored during this first cycle.  
Functional Overview  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock.  
Maximum access delay from the clock rise (tCO) is 2.6 ns (250-  
MHz device).  
ADSP-triggered Write accesses require two clock cycles to  
complete. If GW is asserted LOW on the second clock rise, the  
data presented to the DQs inputs is written into the corre-  
sponding address location in the memory array. If GW is HIGH,  
then the Write operation is controlled by BWE and BWX  
signals. The CY7C1380DV25/CY7C1382DV25 provides Byte  
Write capability that is described in the Write Cycle Descrip-  
tions table. Asserting the Byte Write Enable input (BWE) with  
the selected Byte Write (BWX) input, will selectively write to  
only the desired bytes. Bytes not selected during a Byte Write  
operation will remain unaltered. A synchronous self-timed  
Write mechanism has been provided to simplify the Write  
operations.  
Because the CY7C1380DV25/CY7C1382DV25 is a common  
I/O device, the Output Enable (OE) must be deserted HIGH  
before presenting data to the DQs inputs. Doing so will tri-state  
the output drivers. As a safety precaution, DQs are automati-  
cally tri-stated whenever a Write cycle is detected, regardless  
of the state of OE.  
The CY7C1380DV25/CY7C1382DV25 supports secondary  
cache in systems utilizing either a linear or interleaved burst  
sequence. The interleaved burst order supports Pentium and  
i486processors. The linear burst sequence is suited for  
processors that utilize a linear burst sequence. The burst order  
is user selectable, and is determined by sampling the MODE  
input. Accesses can be initiated with either the Processor  
Address Strobe (ADSP) or the Controller Address Strobe  
(ADSC). Address advancement through the burst sequence is  
controlled by the ADV input. A two-bit on-chip wraparound  
burst counter captures the first address in a burst sequence  
and automatically increments the address for the rest of the  
burst access.  
Byte Write operations are qualified with the Byte Write Enable  
(BWE) and Byte Write Select (BWX) inputs. A Global Write  
Enable (GW) overrides all Byte Write inputs and writes data to  
all four bytes. All writes are simplified with on-chip  
synchronous self-timed Write circuitry.  
Three synchronous Chip Selects (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. ADSP is ignored if CE1  
is HIGH.  
Single Write Accesses Initiated by ADSC  
ADSC Write accesses are initiated when the following condi-  
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is  
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,  
and (4) the appropriate combination of the Write inputs (GW,  
BWE, and BWX) are asserted active to conduct a Write to the  
desired byte(s). ADSC-triggered Write accesses require a  
single clock cycle to complete. The address presented to A is  
loaded into the address register and the address  
advancement logic while being delivered to the memory array.  
The ADV input is ignored during this cycle. If a global Write is  
conducted, the data presented to the DQs is written into the  
corresponding address location in the memory core. If a Byte  
Write is conducted, only the selected bytes are written. Bytes  
not selected during a Byte Write operation will remain  
unaltered. A synchronous self-timed Write mechanism has  
been provided to simplify the Write operations.  
Single Read Accesses  
This access is initiated when the following conditions are  
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)  
CE1, CE2, CE3 are all asserted active, and (3) the Write  
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored  
if CE1 is HIGH. The address presented to the address inputs  
(A) is stored into the address advancement logic and the  
Address Register while being presented to the memory array.  
The corresponding data is allowed to propagate to the input of  
the Output Registers. At the rising edge of the next clock the  
data is allowed to propagate through the output register and  
onto the data bus within 2.6 ns (250-MHz device) if OE is  
active LOW. The only exception occurs when the SRAM is  
emerging from a deselected state to a selected state, its  
outputs are always tri-stated during the first cycle of the  
access. After the first cycle of the access, the outputs are  
controlled by the OE signal. Consecutive single Read cycles  
are supported. Once the SRAM is deselected at clock rise by  
the chip select and either ADSP or ADSC signals, its output  
will tri-state immediately.  
Because the CY7C1380DV25/CY7C1382DV25 is a common  
I/O device, the Output Enable (OE) must be deserted HIGH  
before presenting data to the DQs inputs. Doing so will tri-state  
the output drivers. As a safety precaution, DQs are automati-  
cally tri-stated whenever a Write cycle is detected, regardless  
of the state of OE.  
Burst Sequences  
The CY7C1380DV25/CY7C1382DV25 provides a two-bit  
wraparound counter, fed by A1: A0, that implements either an  
interleaved or linear burst sequence. The interleaved burst  
sequence is designed specifically to support Intel Pentium  
applications. The linear burst sequence is designed to support  
processors that follow a linear burst sequence. The burst  
sequence is user selectable through the MODE input.  
Asserting ADV LOW at clock rise will automatically increment  
the burst counter to the next address in the burst sequence.  
Both Read and Write burst operations are supported.  
Single Write Accesses Initiated by ADSP  
This access is initiated when both of the following conditions  
are satisfied at clock rise: (1) ADSP is asserted LOW, and  
(2) CE1, CE2, CE3 are all asserted active. The address  
presented to A is loaded into the address register and the  
address advancement logic while being delivered to the  
Document #: 38-05546 Rev. **  
Page 8 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Sleep Mode  
Interleaved Burst Address Table  
(MODE = Floating or VDD  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must  
remain inactive for the duration of tZZREC after the ZZ input  
returns LOW  
)
First  
Second  
Address  
A1: A0  
Third  
Address  
A1: A0  
Fourth  
Address  
A1: A0  
Address  
A1: A0  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Linear Burst Address Table  
(MODE = GND)  
First  
Second  
Address  
A1: A0  
Third  
Address  
A1: A0  
Fourth  
Address  
A1: A0  
Address  
A1: A0  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
ZZ Mode Electrical Characteristics  
Parameter  
IDDZZ  
tZZS  
tZZREC  
tZZI  
Description  
Sleep mode standby current  
Device operation to ZZ  
ZZ recovery time  
ZZ Active to sleep current  
ZZ Inactive to exit sleep current  
Test Conditions  
ZZ > VDD – 0.2V  
ZZ > VDD – 0.2V  
ZZ < 0.2V  
This parameter is sampled  
This parameter is sampled  
Min.  
Max.  
80  
2tCYC  
Unit  
mA  
ns  
ns  
ns  
2tCYC  
0
2tCYC  
tRZZI  
ns  
Truth Table[ 3, 4, 5, 6, 7, 8]  
Operation  
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK  
DQ  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Sleep Mode, Power Down  
Read Cycle, Begin Burst  
Read Cycle, Begin Burst  
Write Cycle, Begin Burst  
Read Cycle, Begin Burst  
Read Cycle, Begin Burst  
None  
None  
None  
None  
None  
H
L
L
L
L
X
L
L
L
L
L
X
X
L
X
L
X
X
H
H
H
H
H
X
X
X
H
X
H
X
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
X
L
L
H
H
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
H
X
L
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
L
None  
X
X
X
L
L
L
X
L-H  
Tri-State  
Q
External  
External  
External  
External  
External  
Next  
L
L-H Tri-State  
H
H
H
H
L-H  
L-H  
D
Q
H
H
H
H
L
L-H Tri-State  
L-H  
Read Cycle, Continue Burst  
X
H
Q
Notes:  
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.  
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.  
5. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.  
OE  
OE  
6. CE , CE , and CE are available only in the TQFP package. BGA package has only 2 chip selects CE and CE .  
1
2
3
1
2
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks  
X
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a  
don't care for the remainder of the write cycle  
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is  
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).  
9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.  
X
Document #: 38-05546 Rev. **  
Page 9 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Truth Table[ 3, 4, 5, 6, 7, 8] (continued)  
Operation  
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK  
DQ  
L-H Tri-State  
L-H  
L-H Tri-State  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Next  
Next  
Next  
Next  
Next  
Current  
Current  
Current  
Current  
Current  
Current  
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
H
X
X
H
X
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
L
H
X
X
L
H
L
H
X
X
Q
L-H  
L-H  
L-H  
L-H Tri-State  
L-H  
L-H Tri-State  
D
D
Q
L
H
H
H
H
L
Q
L-H  
L-H  
D
D
L
Truth Table for Read/Write[5, 9]  
Function (CY7C1380DV25)  
Read  
Read  
Write Byte A – (DQA and DQPA)  
Write Byte B – (DQB and DQPB)  
Write Bytes B, A  
Write Byte C – (DQC and DQPC)  
Write Bytes C, A  
GW  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE  
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BWD  
BWC  
BWB  
X
H
H
L
BWA  
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
L
H
H
L
Write Bytes C, B  
Write Bytes C, B, A  
Write Byte D – (DQD and DQPD)  
Write Bytes D, A  
Write Bytes D, B  
Write Bytes D, B, A  
Write Bytes D, C  
Write Bytes D, C, A  
Write Bytes D, C, B  
Write All Bytes  
L
H
H
L
L
H
H
L
L
X
L
X
Write All Bytes  
X
Truth Table for Read/Write[5, 9]  
Function (CY7C1382DV25)  
Read  
Read  
Write Byte A – (DQA and DQPA)  
Write Byte B – (DQB and DQPB)  
Write Bytes B, A  
GW  
H
H
H
H
H
H
L
BWE  
BWB  
X
H
H
L
L
L
X
BWA  
H
L
L
L
L
L
X
X
H
L
H
L
Write All Bytes  
Write All Bytes  
L
X
Document #: 38-05546 Rev. **  
Page 10 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Test Data-In (TDI)  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
The TDI ball is used to serially input information into the  
registers and can be connected to the input of any of the  
registers. The register between TDI and TDO is chosen by the  
instruction that is loaded into the TAP instruction register. For  
information on loading the instruction register, see figure . TDI  
is internally pulled up and can be unconnected if the TAP is  
unused in an application. TDI is connected to the most signif-  
icant bit (MSB) of any register. (See Tap Controller Block  
Diagram.)  
The CY7C1380DV25/CY7C1382DV25 incorporates a serial  
boundary scan test access port (TAP). This part is fully  
compliant with 1149.1. The TAP operates using JEDEC-  
standard 2.5V I/O logic levels.  
The CY7C1380DV25/CY7C1382DV25 contains  
a
TAP  
controller, instruction register, boundary scan register, bypass  
register, and ID register.  
Disabling the JTAG Feature  
Test Data-Out (TDO)  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
(VSS) to prevent clocking of the device. TDI and TMS are inter-  
nally pulled up and may be unconnected. They may alternately  
be connected to VDD through a pull-up resistor. TDO should be  
left unconnected. Upon power-up, the device will come up in  
a reset state which will not interfere with the operation of the  
device.  
The TDO output ball is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine. The output changes on the  
falling edge of TCK. TDO is connected to the least significant  
bit (LSB) of any register. (See Tap Controller State Diagram.)  
TAP Controller Block Diagram  
TAP Controller State Diagram  
0
Bypass Register  
TEST-LOGIC  
1
RESET  
0
2
1
0
0
0
Selection  
Circuitry  
1
1
1
Instruction Register  
31 30 29  
Identification Register  
RUN-TEST/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
Selection  
0
TDI  
TDO  
Circuitr  
y
.
.
. 2 1  
0
0
1
1
CAPTURE-DR  
CAPTURE-IR  
0
0
x
.
.
.
.
. 2 1  
SHIFT-DR  
0
SHIFT-IR  
0
Boundary Scan Register  
1
1
1
1
EXIT1-DR  
EXIT1-IR  
TCK  
TMS  
0
0
TAP CONTROLLER  
PAUSE-DR  
0
PAUSE-IR  
0
1
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
Performing a TAP Reset  
A RESET is performed by forcing TMS HIGH (VDD) for five  
rising edges of TCK. This RESET does not affect the operation  
of the SRAM and may be performed while the SRAM is  
operating.  
UPDATE-DR  
UPDATE-IR  
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO  
comes up in a High-Z state.  
The 0/1 next to each state represents the value of TMS at the  
rising edge of TCK.  
TAP Registers  
Registers are connected between the TDI and TDO balls and  
allow data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through  
the instruction register. Data is serially loaded into the TDI ball  
on the rising edge of TCK. Data is output on the TDO ball on  
the falling edge of TCK.  
Test Access Port (TAP)  
Test Clock (TCK)  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
Instruction Register  
Test Mode Select (TMS)  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the  
TDI and TDO balls as shown in the Tap Controller Block  
Diagram. Upon power-up, the instruction register is loaded  
with the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as  
described in the previous section.  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to  
leave this ball unconnected if the TAP is not used. The ball is  
pulled up internally, resulting in a logic HIGH level.  
Document #: 38-05546 Rev. **  
Page 11 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
When the TAP controller is in the Capture-IR state, the two  
least significant bits are loaded with a binary “01” pattern to  
allow for fault isolation of the board-level serial test data path.  
0s. EXTEST is not implemented in this SRAM TAP controller,  
and therefore this device is not compliant to 1149.1. The TAP  
controller does recognize an all-0 instruction.  
When an EXTEST instruction is loaded into the instruction  
register, the SRAM responds as if a SAMPLE/PRELOAD  
instruction has been loaded. There is one difference between  
the two instructions. Unlike the SAMPLE/PRELOAD  
instruction, EXTEST places the SRAM outputs in a High-Z  
state.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between the  
TDI and TDO balls. This allows data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
(VSS) when the BYPASS instruction is executed.  
IDCODE  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO balls and allows  
the IDCODE to be shifted out of the device when the TAP  
controller enters the Shift-DR state.  
The IDCODE instruction is loaded into the instruction register  
upon power-up or whenever the TAP controller is given a test  
logic reset state.  
Boundary Scan Register  
The boundary scan register is connected to all the input and  
bidirectional balls on the SRAM.  
The boundary scan register is loaded with the contents of the  
RAM I/O ring when the TAP controller is in the Capture-DR  
state and is then placed between the TDI and TDO balls when  
the controller is moved to the Shift-DR state. The EXTEST,  
SAMPLE/PRELOAD and SAMPLE Z instructions can be used  
to capture the contents of the I/O ring.  
SAMPLE Z  
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI and the LSB is connected to TDO.  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO balls when the TAP  
controller is in a Shift-DR state. It also places all SRAM outputs  
into a High-Z state.  
Identification (ID) Register  
SAMPLE/PRELOAD  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in the Identification Register  
Definitions table.  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the in-  
struction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and output pins is cap-  
tured in the boundary scan register.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because  
there is a large difference in the clock frequencies, it is possi-  
ble that during the Capture-DR state, an input or output will  
undergo a transition. The TAP may then try to capture a signal  
while in transition (metastable state). This will not harm the  
device, but there is no guarantee as to the value that will be  
captured. Repeatable results may not be possible.  
To guarantee that the boundary scan register will capture the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture set-up plus  
hold times (tCS and tCH). The SRAM clock input might not be  
captured correctly if there is no way in a design to stop (or  
slow) the clock during a SAMPLE/PRELOAD instruction. If this  
is an issue, it is still possible to capture all other signals and  
simply ignore the value of the CK and CK captured in the  
boundary scan register.  
Once the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the bound-  
ary scan register between the TDI and TDO pins.  
PRELOAD allows an initial data pattern to be placed at the  
latched parallel outputs of the boundary scan register cells pri-  
or to the selection of another boundary scan test operation.  
The shifting of data for the SAMPLE and PRELOAD phases  
can occur concurrently when required—that is, while data  
captured is shifted out, the preloaded data can be shifted in.  
TAP Instruction Set  
Overview  
Eight different instructions are possible with the three-bit  
instruction register. All combinations are listed in the  
Instruction Codes table. Three of these instructions are listed  
as RESERVED and should not be used. The other five instruc-  
tions are described in detail below.  
The TAP controller used in this SRAM is not fully compliant to  
the 1149.1 convention because some of the mandatory 1149.1  
instructions are not fully implemented.  
The TAP controller cannot be used to load address data or  
control signals into the SRAM and cannot preload the I/O  
buffers. The SRAM does not implement the 1149.1 commands  
EXTEST or INTEST or the PRELOAD portion of  
SAMPLE/PRELOAD; rather, it performs a capture of the I/O  
ring when these instructions are executed.  
Instructions are loaded into the TAP controller during the Shift-  
IR state when the instruction register is placed between TDI  
and TDO. During this state, instructions are shifted through the  
instruction register through the TDI and TDO balls. To execute  
the instruction once it is shifted in, the TAP controller needs to  
be moved into the Update-IR state.  
EXTEST  
EXTEST is a mandatory 1149.1 instruction which is to be  
executed whenever the instruction register is loaded with all  
Document #: 38-05546 Rev. **  
Page 12 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
BYPASS  
boundary scan path when multiple devices are connected  
together on a board.  
When the BYPASS instruction is loaded in the instruction  
register and the TAP is placed in a Shift-DR state, the bypass  
register is placed between the TDI and TDO balls. The  
advantage of the BYPASS instruction is that it shortens the  
Reserved  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
TAP Timing  
1
2
3
4
5
6
Test Clock  
(TCK)  
t
t
t
CYC  
TH  
TL  
t
t
t
t
TMSS  
TDIS  
TMSH  
Test Mode Select  
(TMS)  
TDIH  
Test Data-In  
(TDI)  
t
TDOV  
t
TDOX  
Test Data-Out  
(TDO)  
DON’T CARE  
UNDEFINED  
TAP AC Switching Characteristics Over the Operating Range[10, 11]  
Parameter  
Clock  
tTCYC  
tTF  
tTH  
tTL  
Description  
Min.  
Max.  
Unit  
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH time  
TCK Clock LOW time  
50  
ns  
MHz  
ns  
20  
25  
25  
ns  
Output Times  
tTDOV TCK Clock LOW to TDO Valid  
tTDOX TCK Clock LOW to TDO Invalid  
Set-up Times  
tTMSS TMS Set-up to TCK Clock Rise  
tTDIS  
5
ns  
ns  
0
5
5
5
ns  
ns  
TDI Set-up to TCK Clock Rise  
Capture Set-up to TCK Rise  
tCS  
Hold Times  
tTMSH  
tTDIH  
TMS hold after TCK Clock Rise  
TDI Hold after Clock Rise  
Capture Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
tCH  
Notes:  
10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.  
R
F
Document #: 38-05546 Rev. **  
Page 13 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
2.5V TAP AC Test Conditions  
2.5V TAP AC Output Load Equivalent  
1.25V  
Input pulse levels ............................................... .VSS to 2.5V  
Input rise and fall time..................................................... 1 ns  
Input timing reference levels.........................................1.25V  
Output reference levels.................................................1.25V  
Test load termination supply voltage.............................1.25V  
50  
TDO  
ZO= 50Ω  
20pF  
TAP DC Electrical Characteristics And Operating Conditions  
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[12]  
Parameter  
VOH1  
VOH2  
VOL1  
VOL2  
VIH  
Description  
Test Conditions  
Min.  
2.0  
2.1  
Max.  
Unit  
V
V
V
V
V
V
µA  
Output HIGH Voltage IOH = –1.0 mA, VDDQ = 2.5V  
Output HIGH Voltage IOH = –100 µA, VDDQ = 2.5V  
Output LOW Voltage IOL = 8.0 mA, VDDQ = 2.5V  
Output LOW Voltage IOL = 100 µA  
Input HIGH Voltage  
0.4  
0.2  
VDD + 0.3  
VDDQ = 2.5V  
VDDQ = 2.5V  
VDDQ = 2.5V  
1.7  
–0.3  
–5  
VIL  
IX  
Input LOW Voltage  
Input Load Current  
0.7  
5
GND < VIN < VDDQ  
Note:  
12. All voltages referenced to V (GND).  
SS  
Document #: 38-05546 Rev. **  
Page 14 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Identification Register Definitions  
CY7C1380DV25  
CY7C1382DV25  
Instruction Field  
Revision Number (31:29)  
(512K x36)  
(1M x 18)  
000  
Description  
Describes the version number  
000  
01011  
01011  
Reserved for internal use  
Device Depth (28:24)  
000000  
100101  
00000110100  
000000  
010101  
00000110100  
Device Width (23:18)  
Cypress Device ID (17:12)  
Cypress JEDEC ID Code (11:1)  
Defines memory type and architecture  
Defines width and density  
Allows unique identification of SRAM  
vendor  
1
1
ID Register Presence Indicator (0)  
Indicates the presence of an ID register  
Scan Register Sizes  
Bit Size (x36)  
Register Name  
Bit Size (x18)  
Instruction  
Bypass  
ID  
3
1
32  
85  
89  
3
1
32  
85  
89  
Boundary Scan Order (119-ball BGA package)  
Boundary Scan Order (165-ball fBGA package)  
Identification Codes  
Instruction  
EXTEST  
Code  
000  
Description  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM outputs to High-Z state.  
001  
010  
IDCODE  
Loads the ID register with the vendor ID code and places the register between TDI and  
TDO. This operation does not affect SRAM operations.  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM output drivers to a High-Z state.  
SAMPLE Z  
011  
100  
RESERVED  
SAMPLE/PRELOAD  
Do Not Use: This instruction is reserved for future use.  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Does not affect SRAM operation.  
101  
110  
111  
RESERVED  
RESERVED  
BYPASS  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect SRAM  
operations.  
Document #: 38-05546 Rev. **  
Page 15 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
119-Ball BGA Boundary Scan Order [13, 14]  
CY7C1380DV25 (256K x 36)  
CY7C1382DV25 (512K x 18)  
Bit #  
1
2
3
4
5
6
7
8
Ball ID  
Bit #  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
Ball ID  
E4  
G4  
A4  
G3  
C3  
B2  
B3  
A3  
C2  
A2  
B1  
C1  
D2  
E1  
F2  
G1  
H2  
D1  
E2  
G2  
H1  
J3  
K2  
L1  
M2  
N1  
P1  
K1  
L2  
N2  
P2  
R3  
T1  
R1  
T2  
Bit #  
1
2
3
4
5
6
7
8
Ball ID  
Bit #  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
Ball ID  
E4  
G4  
A4  
G3  
C3  
B2  
B3  
A3  
C2  
A2  
B1  
C1  
D2  
E1  
F2  
G1  
H2  
D1  
E2  
G2  
H1  
J3  
K2  
L1  
M2  
N1  
P1  
K1  
L2  
N2  
P2  
R3  
T1  
R1  
T2  
H4  
T4  
T5  
T6  
R5  
L5  
R6  
U6  
R7  
T7  
P6  
N7  
M6  
L7  
K6  
P7  
N6  
L6  
K7  
J5  
H6  
G7  
F6  
E7  
D7  
H7  
G6  
E6  
D6  
C7  
B7  
C6  
A6  
C5  
B5  
G5  
B6  
D4  
B4  
F4  
M4  
A5  
K4  
H4  
T4  
T5  
T6  
R5  
L5  
R6  
U6  
R7  
T7  
P6  
N7  
M6  
L7  
K6  
P7  
N6  
L6  
9
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
K7  
J5  
H6  
G7  
F6  
E7  
D7  
H7  
G6  
E6  
D6  
C7  
B7  
C6  
A6  
C5  
B5  
G5  
B6  
D4  
B4  
F4  
M4  
A5  
K4  
L3  
R2  
T3  
L3  
R2  
T3  
L4  
L4  
N4  
P4  
Internal  
N4  
P4  
Internal  
Notes:  
13. Balls which are NC (No Connect) are pre-set LOW  
14. Bit# 85 is pre-set HIGH  
Document #: 38-05546 Rev. **  
Page 16 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
165-Ball BGA Boundary Scan Order [13, 15]  
CY7C1380DV25 (256K x 36)  
CY7C1380DV25 (256K x 36)  
Bit #  
1
2
3
4
5
6
7
8
Ball ID  
N6  
N7  
10N  
P11  
P8  
R8  
R9  
P9  
Bit #  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
Ball ID  
A9  
B9  
C10  
A8  
B8  
A7  
B7  
B6  
A6  
B5  
A5  
A4  
B4  
B3  
A3  
A2  
B2  
C2  
B1  
A1  
C1  
D1  
E1  
F1  
G1  
D2  
E2  
F2  
G2  
H1  
H3  
J1  
K1  
L1  
M1  
J2  
Bit #  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
Ball ID  
K2  
L2  
M2  
N1  
N2  
P1  
R1  
R2  
P3  
R3  
P2  
R4  
P4  
N5  
P6  
R6  
9
P10  
R10  
R11  
H11  
N11  
M11  
L11  
K11  
J11  
M10  
L10  
K10  
J10  
H9  
H10  
G11  
F11  
E11  
D11  
G10  
F10  
E10  
D10  
C11  
A11  
B11  
A10  
B10  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
Internal  
Notes:  
15. Bit# 89 is pre-set HIGH.  
Document #: 38-05546 Rev. **  
Page 17 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
165-Ball BGA Boundary Scan Order [13, 15]  
CY7C1382DV25 (512K x 18)  
CY7C1382DV25 (512K x 18)  
Bit #  
1
2
3
4
5
6
7
8
Ball ID  
N6  
N7  
10N  
P11  
P8  
R8  
R9  
P9  
Bit #  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
Ball ID  
A9  
B9  
C10  
A8  
B8  
A7  
B7  
B6  
A6  
B5  
A5  
A4  
B4  
B3  
A3  
A2  
B2  
C2  
B1  
A1  
C1  
D1  
E1  
F1  
G1  
D2  
E2  
F2  
G2  
H1  
H3  
J1  
K1  
L1  
M1  
J2  
Bit#  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
Ball ID  
K2  
L2  
M2  
N1  
N2  
P1  
R1  
R2  
P3  
R3  
P2  
R4  
P4  
N5  
P6  
R6  
9
P10  
R10  
R11  
H11  
N11  
M11  
L11  
K11  
J11  
M10  
L10  
K10  
J10  
H9  
H10  
G11  
F11  
E11  
D11  
G10  
F10  
E10  
D10  
C11  
A11  
B11  
A10  
B10  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
Internal  
Document #: 38-05546 Rev. **  
Page 18 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Current into Outputs (LOW)......................................... 20 mA  
Maximum Ratings  
Static Discharge Voltage........................................... >2001V  
(Above which the useful life may be impaired. For user guide-  
(per MIL-STD-883, Method 3015)  
lines, not tested.)  
Latch-up Current..................................................... >200 mA  
Storage Temperature .................................65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Ambient  
VDD/VDDQ  
Range  
Commercial  
Industrial  
Temperature  
0°C to +70°C  
–40°C to +85°C  
Supply Voltage on VDD Relative to GND........ –0.3V to +3.6V  
2.5V +_ 5%  
DC Voltage Applied to Outputs  
in Tri-State........................................... –0.5V to VDDQ + 0.5V  
DC Input Voltage....................................–0.5V to VDD + 0.5V  
Electrical Characteristics Over the Operating Range[16, 17]  
Parameter  
VDD  
VDDQ  
VOH  
VOL  
VIH  
VIL  
IX  
Description  
Test Conditions  
Min.  
Max.  
2.625  
VDD  
Unit  
V
V
V
V
Power Supply Voltage  
I/O Supply Voltage  
Output HIGH Voltage  
Output LOW Voltage  
2.375  
2.375  
2.0  
VDD = Min., IOH = 1.0 mA  
VDD = Min., IOL= 1.0 mA  
0.4  
VDD + 0.3V  
Input HIGH Voltage[16] VDDQ = 2.5V  
Input LOW Voltage[16] VDDQ = 2.5V  
Input Load  
Input Current of MODE Input = VSS  
Input = VDD  
Input Current of ZZ  
1.7  
–0.3  
–5  
V
V
0.7  
5
GND VI VDDQ  
µA  
µA  
µA  
µA  
µA  
µA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
–5  
30  
Input = VSS  
Input = VDD  
–30  
–5  
5
5
IOZ  
IDD  
Output Leakage Current GND VI VDD, Output Disabled  
VDD Operating Supply VDD = Max., IOUT = 0 mA,  
4.0-ns cycle, 250 MHz  
4.4-ns cycle, 225 MHz  
5.0-ns cycle, 200 MHz  
6.0-ns cycle, 167 MHz  
7.5-ns cycle, 133 MHz  
4.0-ns cycle, 250 MHz  
4.4-ns cycle, 225 MHz  
5.0-ns cycle, 200 MHz  
6.0-ns cycle, 167 MHz  
7.5-ns cycle, 133 MHz  
All speeds  
350  
325  
300  
275  
TBD  
160  
TBD  
150  
140  
TBD  
70  
Current  
f = fMAX = 1/tCYC  
ISB1  
Automatic CE  
VDD = Max, Device Deselected,  
Power-down  
VIN VIH or VIN VIL  
Current—TTL Inputs  
f = fMAX = 1/tCYC  
ISB2  
Automatic CE  
Power-down  
VDD = Max, Device Deselected,  
V
IN 0.3V or VIN > VDDQ – 0.3V,  
Current—CMOS Inputs f = 0  
ISB3  
Automatic CE  
VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz  
135  
TBD  
130  
125  
TBD  
80  
mA  
mA  
mA  
mA  
mA  
mA  
Power-down  
V
IN 0.3V or VIN > VDDQ – 0.3V  
4.4-ns cycle, 225 MHz  
5.0-ns cycle, 200 MHz  
6.0-ns cycle, 167 MHz  
7.5-ns cycle, 133 MHz  
All speeds  
Current—CMOS Inputs f = fMAX = 1/tCYC  
ISB4  
Automatic CE  
VDD = Max, Device Deselected,  
VIN VIH or VIN VIL, f = 0  
Power-down  
Current—TTL Inputs  
Shaded areas contain advance information.  
Notes:  
16. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC) > –2V (Pulse width less than t  
/2).  
IH  
DD  
CYC  
IL  
CYC  
17. T  
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
DDQ DD\  
Power-up  
DD  
IH  
DD  
Document #: 38-05546 Rev. **  
Page 19 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Thermal Resistance[18]  
TQFP  
BGA  
fBGA  
Parameter  
Description  
Test Conditions  
Package  
Package  
Package  
Unit  
ΘJA  
Thermal Resistance  
Test conditions follow standard  
test methods and procedures  
for measuring thermal  
31  
45  
46  
°C/W  
(Junction to Ambient)  
ΘJC  
Thermal Resistance  
(Junction to Case)  
6
7
3
°C/W  
impedance, per EIA / JESD51.  
Capacitance[18]  
TQFP  
BGA  
fBGA  
Parameter  
Description  
Test Conditions  
Package  
Package  
Package  
Unit  
pF  
CIN  
Input Capacitance  
TA = 25°C, f = 1 MHz,  
5
5
5
8
8
8
9
9
9
VDD /VDDQ = 2.5V  
CCLK  
CI/O  
Clock Input Capacitance  
Input/Output Capacitance  
pF  
pF  
AC Test Loads and Waveforms  
2.5V I/O Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R = 1538Ω  
1 ns  
1 ns  
V = 1.25V  
T
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
Note:  
18. Tested initially and after any design or process change that may affect these parameters  
Document #: 38-05546 Rev. **  
Page 20 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Switching Characteristics Over the Operating Range[23, 24]  
250 MHz  
225 MHz  
200 MHz  
167 MHz  
133 MHz  
Parameter  
tPOWER  
Clock  
tCYC  
tCH  
tCL  
Description  
Min. Max Min. Max. Min. Max. Min. Max Min. Max Unit  
VDD(Typical) to the First Access[19]  
1
1
1
1
1
ms  
Clock Cycle Time  
Clock HIGH  
4.0  
1.7  
1.7  
4.4  
2.0  
2.0  
5
2.0  
2.0  
6
2.2  
2.2  
7.5  
2.5  
2.5  
ns  
ns  
ns  
Clock LOW  
Output Times  
tCO  
tDOH  
tCLZ  
tCHZ  
tOEV  
tOELZ  
tOEHZ  
Set-up Times  
tAS  
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
Clock to Low-Z[20, 21, 22]  
2.6  
2.8  
3.0  
3.4  
4.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1.0  
1.0  
1.0  
1.0  
1.3  
1.3  
1.3  
1.3  
1.3  
1.3  
Clock to High-Z[20, 21, 22]  
2.6  
2.6  
2.8  
2.8  
3.0  
3.0  
3.4  
3.4  
3.4  
4.2  
OE LOW to Output Valid  
OE LOW to Output Low-Z[20, 21, 22]  
OE HIGH to Output High-Z[20, 21, 22]  
0
0
0
0
0
2.6  
2.8  
3.0  
3.4  
4.0  
Address Set-up Before CLK Rise  
ADSC, ADSP Set-up Before CLK  
Rise  
1.2  
1.2  
1.4  
1.4  
1.4  
1.4  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
tADS  
tADVS  
tWES  
ADV Set-up Before CLK Rise  
GW, BWE, BWX Set-up Before CLK  
Rise  
1.2  
1.2  
1.4  
1.4  
1.4  
1.4  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
tDS  
tCES  
Data Input Set-up Before CLK Rise  
Chip Enable Set-Up Before CLK Rise 1.2  
1.2  
1.4  
1.4  
1.4  
1.4  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
Hold Times  
tAH  
tADH  
tADVH  
tWEH  
tDH  
Address Hold After CLK Rise  
ADSP, ADSC Hold After CLK Rise  
ADV Hold After CLK Rise  
GW, BWE, BWX Hold After CLK Rise 0.3  
Data Input Hold After CLK Rise  
Chip Enable Hold After CLK Rise  
0.3  
0.3  
0.3  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
0.3  
0.3  
tCEH  
Shaded areas contain advance information.  
Notes:  
19. This part has a voltage regulator internally; t  
can be initiated.  
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation  
DD  
POWER  
20. t  
, t  
,t  
, and t  
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
CHZ CLZ OELZ  
OEHZ  
21. At any given voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
CLZ  
OEHZ  
OELZ  
CHZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z prior to Low-Z under the same system conditions  
22. This parameter is sampled and not 100% tested.  
23. Timing reference level is 1.5V when V  
= 1.25V when V  
= 2.5V.  
DDQ  
DDQ  
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
Document #: 38-05546 Rev. **  
Page 21 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Switching Waveforms  
Read Cycle Timing[25]  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
ADH  
ADS  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Burst continued with  
new base address  
t
t
WEH  
WES  
GW, BWE,  
BWx  
Deselect  
cycle  
t
t
CEH  
CES  
CE  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV  
suspends  
burst.  
t
t
OEV  
CO  
t
t
OEHZ  
t
OELZ  
t
CHZ  
DOH  
t
CLZ  
t
Q(A2)  
Q(A2 + 1)  
Q(A2 + 2)  
Q(A2 + 3)  
Q(A2)  
Q(A2 + 1)  
Q(A1)  
Data Out (Q)  
High-Z  
CO  
Burst wraps around  
to its initial state  
Single READ  
BURST READ  
DON’T CARE  
UNDEFINED  
Note:  
25. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
Document #: 38-05546 Rev. **  
Page 22 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Switching Waveforms (continued)  
Write Cycle Timing[25, 26]  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC extends burst  
t
t
ADH  
ADS  
t
t
ADH  
ADS  
ADSC  
ADDRESS  
BWE,  
t
t
AH  
AS  
A1  
A2  
A3  
Byte write signals are  
ignored for first cycle when  
ADSP initiates burst  
t
t
WEH  
WES  
BW  
X
t
t
WEH  
WES  
GW  
CE  
t
t
CEH  
CES  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV suspends burst  
t
t
DH  
DS  
Data In (D)  
D(A2)  
D(A2 + 1)  
D(A2 + 1)  
D(A2 + 2)  
D(A2 + 3)  
D(A3)  
D(A3 + 1)  
D(A3 + 2)  
D(A1)  
High-Z  
t
OEHZ  
Data Out (Q)  
BURST READ  
Single WRITE  
BURST WRITE  
Extended BURST WRITE  
DON’T CARE  
UNDEFINED  
Note:  
26.  
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.  
X
Document #: 38-05546 Rev. **  
Page 23 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Switching Waveforms (continued)  
Read/Write Cycle Timing[25, 27, 28]  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
A4  
A5  
A6  
ADDRESS  
BWE,  
t
t
WEH  
WES  
BW  
X
t
t
CEH  
CES  
CE  
ADV  
OE  
t
t
DH  
t
CO  
DS  
t
OELZ  
Data In (D)  
High-Z  
High-Z  
D(A3)  
D(A5)  
D(A6)  
t
t
OEHZ  
CLZ  
Data Out (Q)  
Q(A1)  
Q(A2)  
Q(A4)  
Q(A4+1)  
Q(A4+2)  
Q(A4+3)  
Back-to-Back READs  
Single WRITE  
BURST READ  
Back-to-Back  
WRITEs  
DON’T CARE  
UNDEFINED  
Notes:  
27.  
ADSP or ADSC.  
The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by  
28. GW is HIGH.  
Document #: 38-05546 Rev. **  
Page 24 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Switching Waveforms (continued)  
ZZ Mode Timing [29, 30]  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes:  
29. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.  
30. DQs are in high-Z when exiting ZZ sleep mode  
Document #: 38-05546 Rev. **  
Page 25 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Ordering Information  
Speed  
Package  
Operating  
Range  
Commercial  
(MHz)  
Ordering Code  
Name  
Part and Package Type  
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)  
250  
CY7C1380DV25-250AC  
A101  
CY7C1382DV25-250AC  
CY7C1380DV25-250BGC  
CY7C1382DV25-250BGC  
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1380DV25-250BZC  
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1382DV25-250BZC  
225  
200  
CY7C1380DV25-225AC  
CY7C1382DV25-225AC  
A101  
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)  
CY7C1380DV25-225BGC  
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1382DV25-225BGC  
CY7C1380DV25-225BZC  
CY7C1382DV25-225BZC  
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1380DV25-200AC  
A101  
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)  
CY7C1382DV25-200AC  
CY7C1380DV25-200BGC  
CY7C1382DV25-200BGC  
CY7C1380DV25-200BZC  
CY7C1382DV25-200BZC  
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
167  
CY7C1380DV25-167AC  
A101  
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)  
CY7C1382DV25-167AC  
CY7C1380DV25-167BGC  
CY7C1382DV25-167BGC  
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1380DV25-167BZC  
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1382DV25-167BZC  
133  
167  
CY7C1380DV25-133AC  
A101  
A101  
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)  
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)  
CY7C1380DV25-167AI  
CY7C1382D-167AI  
Industrial  
CY7C1380DV25-167BGI  
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1382DV25-167BGI  
CY7C1380DV25-167BZI  
CY7C1382DV25-167BZI  
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
Shaded areas contain advance information.  
Please contact your local sales representative for availability of these parts.  
Document #: 38-05546 Rev. **  
Page 26 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Package Diagrams  
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101  
DIMENSIONS ARE IN MILLIMETERS.  
ꢁ6.00 0.20  
ꢁ4.00 0.ꢁ0  
ꢁ.40 0.05  
ꢁ00  
ꢀꢁ  
ꢀ0  
0.30 0.0ꢀ  
0.65  
TYP.  
ꢁ2° ꢁ°  
(ꢀX)  
SEE DETAIL  
A
30  
5ꢁ  
3ꢁ  
50  
0.20 MAX.  
ꢁ.60 MAX.  
R 0.0ꢀ MIN.  
0.20 MAX.  
0° MIN.  
STAND-OFF  
0.05 MIN.  
0.ꢁ5 MAX.  
SEATING PLANE  
0.25  
GAUGE PLANE  
R 0.0ꢀ MIN.  
0.20 MAX.  
0°-7°  
0.60 0.ꢁ5  
0.20 MIN.  
ꢁ.00 REF.  
51-85050-*A  
DETAIL  
A
Document #: 38-05546 Rev. **  
Page 27 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Package Diagrams (continued)  
119-Lead PBGA (14 x 22 x 2.4 mm) BG119  
51-85115-*B  
Document #: 38-05546 Rev. **  
Page 28 of 30  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Package Diagrams (continued)  
165 FBGA 13 x 15 x 1.40 MM BB165D  
51-85180-**  
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM  
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05546 Rev. **  
Page 29 of 30  
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CY7C1380DV25  
CY7C1382DV25  
PRELIMINARY  
Document History Page  
Document Title: CY7C1380DV25/CY7C1382DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM (Preliminary)  
Document Number: 38-05546  
Orig. of  
REV.  
ECN NO. Issue Date Change  
Description of Change  
**  
254515  
See ECN  
RKF  
New Data Sheet  
Document #: 38-05546 Rev. **  
Page 30 of 30  

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