CY7C1383BV25-100AI [CYPRESS]
Standard SRAM, 1MX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | CY7C1383BV25-100AI |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 1MX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总26页 (文件大小：799K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1383BV25
CY7C1381BV25
512K x 36 / 1M x 18 Flow-Thru SRAM
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), Burst Control
Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
BWc, BWd,and BWe), and Global Write (GW).
Features
• Fast access times: 7.5, 8.5, 10 ns
• Fast clock speed: 117, 100, 83 MHz
• Provide high-performance 2-1-1-1 access rate
• Optimal for depth expansion
Asynchronous inputs include the output enable (OE) and burst
mode control (MODE). The data outputs (Q), enabled by OE,
are also asynchronous.
• 2.5V ± 5% power supply
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down available using ZZ mode or CE
deselect
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQ1–DQ8 and DP1. BWb controls DQ9–DQ16 and
DP2. BWc controls DQ17–DQ24and DP3. BWd controls
DQ25–DQ32 and DP4. BWa, BWb BWc, and BWd can be
active only with BWe being LOW. GW being LOW causes all
bytes to be written. WRITE pass-through capability allows
written data available at the output for the immediately next
Read cycle. This device also incorporates pipelined enable
circuit for easy depth expansion without penalizing system
performance.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced single
layer polysilicon, three-layer metal technology. Each memory
cell consists of six transistors.
The CY7C1381BV25 and CY7C1383BV25 SRAMs integrate
524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
All inputs and outputs of the CY7C1381BV25 and the
CY7C1383BV25 are JEDEC standard JESD8-5-compatible.
Selection Guide
117 MHz
7.5
100 MHz
8.5
83 Mhz
10
Unit
ns
Maximum Access Time
Maximum Operating Current
Commercial
210
190
160
30
mA
mA
Maximum CMOS Standby Current
30
30
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05249 Rev. *A
Revised January 18, 2003
CY7C1383BV25
CY7C1381BV25
Functional Block Diagram
Logic Block Diagram ×18
MODE
(A0,A1)
2
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
18
20
ADDRESS
REGISTER
CE
D
1M × 18
A[19:0]
20
18
Memory
Array
GW
DQb[15:8],DP1
D
Q
Q
BYTEWRITE
REGISTERS
BWE
BWS
b
D DQa[7:0],DP0
BYTEWRITE
REGISTERS
BWS
a
18
18
CE
CE
CE
1
2
3
D
CE
ENABLE
Q
REGISTER
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ[15:0]
DP[1:0]
Logic Block Diagram ×36
MODE
(A0,A1)
2
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
Q
1
ADSP
Q
17
19
ADDRESS
REGISTER
CE
D
512K × 36
A[18:0]
19
17
Memory
Array
GW
DQd[31:24],DP3Q
D
D
BYTEWRITE
REGISTERS
BWE
BWS
d
DQc[23:16],DP2
Q
BYTEWRITE
REGISTERS
BWS
BWS
c
D
D
DQb[15:8],DP1
Q
BYTEWRITE
b
REGISTERS
DQa[7:0],DP0Q
BWS
BYTEWRITE
a
REGISTERS
36
36
CE
CE
CE
1
2
3
D
ENABLE
Q
CE REGISTER
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ[31:0]
DP[3:0]
Document #: 38-05249 Rev. *A
Page 2 of 26
CY7C1383BV25
CY7C1381BV25
Pin Configurations
100-pin TQFP Packages
NC
NC
NC
DPc
1
A
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
2
NC
NC
V
DQc
3
4
5
6
7
8
9
V
V
V
DDQ
DDQ
V
DDQ
DDQ
V
V
SSQ
NC
NC
DQb
DQb
SSQ
V
SSQ
SSQ
DQc
NC
DQb
DQb
DQb
DQb
DQc
DQc
DQc
DPa
DQa
DQa
9
V
V
V
V
SSQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSQ
V
SSQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSQ
V
V
DDQ
DDQ
V
DDQ
DDQ
DQb
DQb
NC
DQc
DQc
NC
DQa
DQa
DQb
DQb
V
V
SS
SS
V
CY7C1383B
(1M × 18)
V
DD
NC
CY7C1381B
(512K × 36)
DD
NC
NC
NC
V
V
DD
DD
V
V
SS
ZZ
DQa
DQa
SS
ZZ
DQa
DQa
DQb
DQb
DQd
DQd
V
V
V
V
V
DDQ
V
DDQ
DDQ
DDQ
SSQ
DQb
DQb
DPb
NC
V
SSQ
V
SSQ
SSQ
DQd
DQa
DQa
NC
DQa
DQa
DQa
DQa
DQd
DQd
DQd
V
V
DQd
DQd
DPd
NC
V
V
SSQ
V
SSQ
V
SSQ
SSQ
DDQ
NC
NC
NC
V
DDQ
V
DDQ
DDQ
NC
NC
NC
DQa
DQa
DPa
Document #: 38-05249 Rev. *A
Page 3 of 26
CY7C1383BV25
CY7C1381BV25
Pin Configurations (continued)
119-ball BGA
CY7C1381BV25 (512K × 36)
2
A
1
3
A
4
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
ADSP
ADSC
VDD
NC
VDDQ
NC
A
A
A
A
NC
A
A
A
A
NC
DQc
DQc
VDDQ
DQPc
DQc
DQc
VSS
VSS
VSS
VSS
VSS
VSS
DQPb
DQb
DQb
DQb
DQb
VDDQ
CE1
OE
G
H
J
DQc
DQc
VDDQ
DQc
DQc
VDD
BWc
VSS
NC
ADV
GW
VDD
BWb
VSS
NC
DQb
DQb
VDD
DQb
DQb
VDDQ
K
L
DQd
DQd
VDDQ
DQd
DQd
DQd
VSS
BWd
VSS
CLK
NC
VSS
BWa
VSS
DQa
DQa
DQa
DQa
DQa
VDDQ
M
BWE
N
P
R
T
DQd
DQd
NC
DQd
VSS
VSS
MODE
A
A1
A0
VSS
VSS
NC
A
DQa
DQPa
A
DQa
DQa
NC
DQPd
VDD
A
A
NC
64M
32M
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
VDDQ
CY7C1383BV25 (1M × 18)
2
A
1
3
A
4
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
ADSP
ADSC
VDD
NC
VDDQ
NC
A
A
A
A
NC
A
A
A
A
NC
DQb
NC
NC
DQb
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQPa
NC
DQa
NC
CE1
OE
DQa
VDDQ
VDDQ
G
H
J
NC
DQb
VDDQ
NC
DQb
NC
BWb
VSS
NC
ADV
GW
VSS
VSS
NC
NC
DQb
VDD
NC
DQa
NC
VDD
DQb
NC
VDD
CLK
NC
VDDQ
DQa
NC
K
L
VSS
VSS
VSS
VSS
BWa
VSS
DQb
VDDQ
DQa
NC
M
DQb
BWE
VDDQ
N
P
DQb
NC
NC
VSS
VSS
A1
A0
VSS
VSS
DQa
NC
NC
DQPb
DQa
R
T
NC
64M
VDDQ
A
A
MODE
A
VDD
32M
TCK
NC
A
A
A
NC
ZZ
U
TMS
TDI
TDO
NC
VDDQ
Document #: 38-05249 Rev. *A
Page 4 of 26
CY7C1383BV25
CY7C1381BV25
Pin Configurations (continued)
165-ball Bump FBGA
CY7C1381BV25 (512K × 36)–11 × 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWc
BWb
CE
BWE
A
ADSC
ADV
A
NC
1
2
3
NC
DPc
DQc
A
CE
BWd
BWa
CLK
GW
B
C
D
OE
ADSP
A
128M
DPb
NC
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DQc
DQc
DQc
DQc
V
V
V
V
V
V
DQb
DQb
DD
SS
SS
SS
DD
DDQ
DQc
DQc
DQc
NC
V
V
V
V
E
F
V
V
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
G
H
J
V
V
DD
SS
SS
SS
DD
DDQ
V
NC
V
V
V
V
V
NC
SS
DD
SS
SS
SS
DD
DQd
DQd
DQd
DQd
DPd
NC
DQd
DQd
DQd
DQd
NC
V
V
V
V
V
V
V
DQa
DQa
DQa
DQa
NC
DQa
DQa
DQa
DQa
DPa
A
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
V
V
K
L
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
M
N
P
V
V
DDQ
DD
SS
SS
SS
DD
DDQ
V
NC
TDI
A
NC
V
V
DDQ
SS
SS
DDQ
64M
A
A
A
A1
A0
TDO
TCK
A
A
A
A
A
MODE
32M
A
TMS
R
A
A
CY7C1383BV25 (1M x 18) - 11 x 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWb
NC
CE
BWE
A
ADSC
ADV
A
A
1
2
3
NC
NC
NC
A
CE
NC
BWa
CLK
GW
B
C
D
E
F
OE
ADSP
A
128M
DPa
NC
V
V
V
V
V
V
V
V
V
V
V
NC
NC
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DQb
V
V
V
V
V
V
DQa
DD
SS
SS
SS
DD
DDQ
NC
NC
DQb
DQb
DQb
V
V
V
V
V
V
NC
NC
DQa
DQa
DQa
ZZ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
NC
V
V
V
V
G
H
J
V
V
NC
DD
SS
SS
SS
DD
DDQ
NC
V
NC
V
V
V
V
V
NC
NC
SS
DD
SS
SS
SS
DD
DQb
DQb
DQb
DQb
DPb
NC
NC
NC
NC
NC
NC
64M
V
V
V
V
V
V
V
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
NC
A
DDQ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
V
V
K
L
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
M
N
P
V
V
DD
SS
SS
SS
DD
DDQ
V
NC
TDI
A
NC
V
V
DDQ
SS
SS
DDQ
A
A
A
A1
A0
TDO
TCK
A
A
A
A
A
MODE
32M
A
TMS
R
A
A
Document #: 38-05249 Rev. *A
Page 5 of 26
CY7C1383BV25
CY7C1381BV25
Pin Definitions
Pin Name
I/O
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed
the two-bit counter.
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
BWE
CLK
CE1
CE2
CE3
OE
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and BWE).
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. (TQFP Only)
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device. (TQFP Only)
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and
act as input data pins. OE is masked during the first clock of a read cycle when emerging from
a deselected state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
ments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A is
captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted
HIGH.
ADSC
MODE
ZZ
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[x:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized.
Input Pin
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDDQ or
left floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation.
Input-
ZZ “sleep” Input. This active HIGH input placesthe device in a non-time critical“sleep” condition
Asynchronous with data integrity preserved.
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A[x] during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQa–DQd and DQPa–DQPd are placed in a three-state condition.DQ a,b,c and d are eight bits
wide. DP a,b,c and d are one bit wide.
TDO
TDI
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
Synchronous
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA
Synchronous
only).
TCK
VDD
JTAG serial clock Serial clock to the JTAG circuit (BGA only).
Power Supply Power supply inputs to the core of the device. Should be connected to 2.5V +5% power
supply.
VSS
Ground
Ground for the core of the device. Should be connected to ground of the system.
Document #: 38-05249 Rev. *A
Page 6 of 26
CY7C1383BV25
CY7C1381BV25
Pin Definitions (continued)
Pin Name
VDDQ
I/O
Pin Description
I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.5V ± 5% power supply.
VSSQ
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
No Connects. Pins are not internally connected.
NC
–
–
32M
64M
128M
No connects. Reserved for address expansion.
Functional Description
Single Read Accesses
the RAM core. If a byte write is conducted, only the selected
bytes are written. Bytes not selected during a byte write
operation will remain unaltered. All I/Os are three-stated
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE1 is HIGH. The address presented to the address inputs
is stored into the address advancement logic and the Address
Register while being presented to the memory core. If the OE
input is asserted LOW, the requested data will be available at
the data outputs a maximum to tCDV after clock rise. ADSP is
ignored if CE1 is HIGH.
during
a
byte write because the CY7C1381BV25/
CY7C1383AV25 is a common I/O device, the Output Enable
(OE) must be deasserted HIGH before presenting data to the
DQx inputs. Doing so will three-state the output drivers. As a
safety precaution, DQx are automatically three-stated
whenever a write cycle is detected, regardless of the state of
OE.
Burst Sequences
Single Write Accesses Initiated by ADSP
The CY7C1381BV25/CY7C1383AV25 provides a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) chip enable asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BWx) and ADV inputs are
ignored during this first clock cycle. If the write inputs are
asserted active (see Write Cycle Descriptions table for appro-
priate states that indicate a write) on the next clock rise, the
appropriate data will be latched and written into the device.
The CY7C1381BV25/ CY7C1383AV25 provides byte write
capability that is described in the Write Cycle Description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write (BWa,b,c,d for CY7C1381BV25 and BWa,b
for CY7C1383AV25) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. All I/Os are three-stated during a byte
write.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Because the CY7C1381BV25/CY7C1383AV25 is a common
I/O device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQx inputs. Doing so will
three-state the output drivers. As a safety precaution, DQx are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
Single Write Accesses Initiated by ADSC
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BWx) are asserted active to conduct a write to the
desired byte(s). ADSC is ignored if ADSP is active LOW.
Sleep Mode
The address presented to A[17:0] is loaded into the address
register and the address advancement logic while being
delivered to the RAM core. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQx is written into the corresponding address location in
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Document #: 38-05249 Rev. *A
Page 7 of 26
CY7C1383BV25
CY7C1381BV25
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW. Leaving ZZ unconnected defaults the device into
an active state.
ZZ Mode Electrical Characteristics
Test
Parameter Description Conditions Min. Max. Unit
ICCZZ
Sleep mode
standby current
ZZ > VDD
−
20 mA
0.2V
tZZS
Device
ZZ > VDD
−
2tCY ns
operation to ZZ
0.2V
C
tZZREC
ZZ recovery
time
ZZ < 0.2V 2tCYC
ns
Cycle Descriptions[1, 2, 3]
Next Cycle
Unselected
Add. Used
None
ZZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
CE3
X
1
CE2
X
X
0
CE1
ADSP
X
0
ADSC
ADV
OE
X
X
X
X
X
X
X
1
DQ
Write
X
1
0
0
0
0
0
0
X
X
1
1
X
X
1
1
X
1
0
X
1
X
1
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
1
1
X
0
0
1
1
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Unselected
None
X
Unselected
None
X
1
0
X
Unselected
None
X
0
1
X
Unselected
None
X
0
1
X
Begin Read
External
External
Next
1
0
X
Begin Read
0
1
1
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
1
1
Next
1
0
Next
X
X
1
1
Hi-Z
DQ
Next
0
Current
Current
Current
Current
Current
Current
External
Next
1
Hi-Z
DQ
1
0
X
X
1
1
Hi-Z
DQ
0
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Begin Write
X
1
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
X
X
X
X
X
X
X
X
X
X
1
Next
X
1
Current
Current
None
X
X
ZZ “sleep”
Note:
1. X = ”Don't Care,” 1 = HIGH, 0 = LOW.
2. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a “Don't Care” for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ = High-Z when OE is inactive
or when the device is deselected, and DQ = data when OE is active.
Document #: 38-05249 Rev. *A
Page 8 of 26
CY7C1383BV25
CY7C1381BV25
Write Cycle Description[1, 2, 3]
Function (CY7C1381BV25)
Read
GW
1
BWE
1
BWd
X
1
BWc
X
1
BWb
X
1
BWa
X
1
Read
1
0
Write Byte 0 – DQa
Write Byte 1 – DQb
Write Bytes 1, 0
Write Byte 2 – DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 – DQd
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
1
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Function (CY7C1383BV25)
Read
Read
Write Byte 0 – DQa and DPa
Write Byte 1 – DQb and DPb
Write All Bytes
GW
BWE
BWb
BWa
1
1
1
1
1
0
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
Write All Bytes
Test Mode Select
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The CY7C1381BV25/CY7C1383AV25 incorporates a serial
boundary scan Test Access Port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1-1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
Test Access Port–Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05249 Rev. *A
Page 9 of 26
CY7C1383BV25
CY7C1381BV25
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data or control signals into the
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
EXTEST
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary "01" pattern to
allow for fault isolation of the board level serial test path.
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
Bypass Register
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a xx-bit-long
register, and the x18 configuration has a yy-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1-mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.
Identification (ID) Register
When the SAMPLE/PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
Document #: 38-05249 Rev. *A
Page 10 of 26
CY7C1383BV25
CY7C1381BV25
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (TCS and TCH). The SRAM clock input might not
be captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Bypass
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
Once the data is ca‘ptured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
AP Controller State Diagram
TEST-LOGIC
RESET
1[4]
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
1
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
4. The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05249 Rev. *A
Page 11 of 26
CY7C1383BV25
CY7C1381BV25
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
0
TDO
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[5, 6]
Parameter
VOH1
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Test Conditions
IOH = −4.0 mA
Min.
2.0
Max.
Unit
V
V
VOH2
VOL1
VOL2
VIH
IOH = −100 µA
IOL = 8.0 mA
IOL = 100 µA
VDD – 0.2
0.4
0.2
V
V
1.7
-0.3
−5
V
DD + 0.3
V
VIL
0.7
V
IX
GND ≤ VI ≤ VDDQ
5
µA
Notes:
5. All Voltage referenced to Ground.
6. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot:VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
Document #: 38-05249 Rev. *A
Page 12 of 26
CY7C1383BV25
CY7C1381BV25
TA P
TAP AC Switching Characteristics Over the Operating Range[7, 8]
Parameters
tTCYC
Description
Min.
Max.
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
tTF
10
MHz
ns
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock HIGH to TDO Invalid
20
ns
ns
tTDOX
0
TAP Timing and Test Conditions
ALL INPUT PULSES
DD
1.25V
V
1/2V
DD
50Ω
0V
TDO
Z = 50Ω
0
C = 20 pF
L
GND
tTL
(a)
tTH
tTCYC
tTMSS
Test Clock
TCK
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Notes:
7. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
8. Test conditions are specified using the load in TAP AC test conditions. TR/TF = 1 ns.
Document #: 38-05249 Rev. *A
Page 13 of 26
CY7C1383BV25
CY7C1381BV25
Identification Register Definitions
Instruction Field
Revision Number (31:28)
Device Depth (27:23)
512K × 36
1M × 18
xxxx
Description
xxxx
00111
00100
xxxxx
Reserved for version number.
Defines depth of SRAM. 512K or 1M
Defines with of the SRAM. x36 or x18
Reserved for future use.
01000
00011
xxxxx
Device Width (22:18)
Cypress Device ID (17:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
00011100100 00011100100 Allows unique identification of SRAM vendor.
1
1
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bypass
Bit Size (×18)
Bit Size (×36)
3
1
3
1
ID
32
51
32
70
Boundary Scan
Identification Codes
Instruction
EXTEST
Code
Description
000
001
010
011
Captures the Input/Output ring contents. Places the boundary scan register between the TDI
and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
RESERVED
Captures the Input/Output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD 100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use. This instruction is reserved for future use.
Do Not Use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document #: 38-05249 Rev. *A
Page 14 of 26
CY7C1383BV25
CY7C1381BV25
Boundary Scan Order (512K × 36)
Boundary Scan Order (1M × 18)
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Bit #
Bit #
36
Bit #
Bit #
36
1
A
2R
A
6B
1
A
2R
DQb
2E
2
A
3T
4T
5T
6R
3B
5B
6P
7N
6M
7L
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
BWa#
BWb#
BWc#
BWd#
A
5L
2
A
2T
3T
5T
6R
3B
5B
7P
6N
6L
7K
7T
6H
7G
6F
7E
6D
6T
6A
5A
4G
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
DQb
DQb
NC
2G
1H
5R
2K
1L
3
A
5G
3G
3L
3
A
4
A
4
A
5
A
5
A
DQb
DQb
DQb
DQb
DQb
MODE
A
6
A
2B
4E
3A
2A
2D
1E
2F
1G
1D
1D
2E
2G
1H
5R
2K
1L
6
A
7
A
CE#
A
7
A
2M
1N
2P
3R
2C
3C
5C
6C
4N
4P
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
8
DQa
DQa
DQa
DQa
ZZ
9
A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
6K
7P
6N
6L
A
DQa
DQa
DQa
DQa
DQa
A
A
A
A1
7K
7T
6H
7G
6F
7E
6D
7H
6G
6E
7D
6A
5A
4G
A0
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
A
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
A
ADV#
2M
1N
2P
1K
2L
ADSP# 4A
ADSC# 4B
OE#
BWE#
GW#
CLK
A
4F
4M
4H
4K
6B
5L
2N
1P
3R
2C
3C
5C
6C
4N
4P
A
ADV#
BWa#
BWb#
A
ADSP# 4A
ADSC# 4B
3G
2B
4E
3A
2A
1D
A
OE#
4F
4M
4H
4K
A
CE#
A
BWE#
GW#
CLK
A
A1
A
A0
DQb
Document #: 38-05249 Rev. *A
Page 15 of 26
CY7C1383BV25
CY7C1381BV25
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >1500V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Latch-up Current..................................................... >200 mA
Operating Range
[11]
Range
Commercial
Industrial
Ambient Temperature[10] VDD/VDDQ
Supply Voltage on VDD Relative to GND.........−0.3V to +3.6V
0°C to +70°C
2.5V ± 5%
DC Voltage Applied to Outputs
–40°C to +85°C
in High-Z State[9] .....................................−0.5V to VDDQ + 0.5V
DC Input Voltage[9]..................................−0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VDD = Min., IOH = −1.0 mA
Min.
Max.
Unit
V
VDD / VDDQ Power Supply Voltage
2.375
2.0
2.625
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[9]
Input Load Current
Input Current of MODE
Input Current of ZZ
V
VDD = Min., IOL = 1.0 mA
0.4
V
1.7
V
−0.3
0.7
5
V
GND ≤ VI ≤ VDDQ
µA
µA
µA
µA
−30
−30
30
30
5
Input = VSS
IOZ
IDD
Output Leakage
Current
GND ≤ VI ≤ VDDQ, Output Disabled
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
8.5-ns cycle, 117 MHz
210
190
160
85
mA
mA
mA
mA
mA
mA
mA
10-ns cycle, 100 MHz
12-ns cycle, 83MHz
ISB1
Automatic CS
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, 8.5-ns cycle, 117 MHz
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
10-ns cycle, 100 MHz
12-ns cycle, 83 MHz
All Speeds grade
70
65
ISB2
Automatic CS
Power-down
Max. VDD, Device
30
Deselected, VIN ≤ 0.3V or VIN
Current—CMOS Inputs > VDDQ – 0.3V, f = 0
ISB3
Automatic CS
Power-down
Current—CMOS Inputs VIN > VDDQ – 0.3V
Max. VDD, Device
Deselected, or VIN ≤ 0.3V or
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
12-ns cycle, 83 MHz
60
55
50
mA
mA
mA
f = fMAX = 1/tCYC
ISB4
Automatic CS
Power-down
Max. VDD, Device
Deselected,
All Speeds grade
40
mA
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL, f = 0
Capacitance[12]
Parameter
Description
Input Capacitance
Test Conditions
Max.
Unit
pF
CIN
3
3
3
TA = 25°C, f = 1 MHz,
DD = 3.3V,
DDQ = 2.5V
V
V
CCLK
Clock Input Capacitance
Input/Output Capacitance
pF
CI/O
pF
Notes:
9. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
10. TA is the temperature.
11. Power Supply ramp up should be monotonic.
Document #: 38-05249 Rev. *A
Page 16 of 26
CY7C1383BV25
CY7C1381BV25
AC Test Loads and Waveforms[13]
R = 1667Ω
V
DDQ
[12]
OUTPUT
ALL INPUT PULSES
90%
VDD
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
GND
R = 1538Ω
≤ 1V/ns
≤ 1V/ns
= 1.25V
VTH
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
Thermal Resistance[12]
ΘJA
ΘJC
Description
Test Conditions
Unit
°C/W
°C/W
°C/W
(Junction to Ambient)
(Junction to Case)
119-ball BGA
165-ball FBGA
100-pin TQFP
Still Air, soldered on a 114.3 x 101.6 x 1.57 mm3,
2-layer board
41.54
44.51
25
6.33
2.38
9
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer
printed circuit board
Switching Characteristics Over the Operating Range[14, 15, 16]
-117
Max.
-100
-83
Parameter
tCYC
Description
Clock Cycle Time
Min.
8.5
2.3
2.3
1.5
0.5
Min.
10.0
2.5
Max.
Min.
12.0
3.0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCH
Clock HIGH
tCL
Clock LOW
2.5
3.0
tAS
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWE, GW, BWx Set-Up Before CLK Rise
BWE, GW, BWx Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
1.5
1.5
tAH
0.5
0.5
tCO
7.5
8.5
10.0
tDOH
tADS
tADH
tWES
tWEH
tADVS
tADVH
tDS
1.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip enable Set-Up
tDH
tCES
tCEH
tCHZ
tCLZ
tEOHZ
tEOLZ
Chip enable Hold After CLK Rise
Clock to High-Z[15]
Clock to Low-Z[15]
OE HIGH to Output High-Z[15, 16]
OE LOW to Output Low-Z[15, 16]
OE LOW to Output Valid[15]
3.0
4.0
3.4
3.0
4.0
3.8
3.0
4.0
4.2
1.3
0
1.3
0
1.3
0
tEOV
Notes:
12. Tested initially and after any design or process changes that may affect these parameters.
13. Input waveform should have a slew rate of 1 V/ns.
14. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
15.
tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
16. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ
.
Document #: 38-05249 Rev. *A
Page 17 of 26
CY7C1383BV25
CY7C1381BV25
1
Switching Waveforms
Write Cycle Timing[17, 18]
Single Write
tCYC
tADH
Burst Write
Pipelined Write
tCH
Unselected
CLK
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADH
tADS
ADSC initiated write
tADVH
tADVS
tAS
ADV Must Be Inactive for ADSP Write
WD3
ADD
GW
WE
CE1
WD1
WD2
tAH
tWH
tWH
tWS
tWS
tCES
tCEH
CE1 masks ADSP
tCEH
tCES
Unselected with CE2
CE2
CE3
OE
tCES
tCEH
tDH
tDS
High-Z
High-Z
Data In
3a
2a
1a
2b
2c
2d
= UNDEFINED
= DON’T CARE
Notes:
17. WE is the combination of BWE, BWx, and GW to define a Write cycle (see Write Cycle Descriptions table).
18. WDx stands for Write Data to Address X.
Document #: 38-05249 Rev. *A
Page 18 of 26
CY7C1383BV25
CY7C1381BV25
Switching Waveforms (continued)
Read Cycle Timing[17, 19]
Burst Read
Single Read
Unselected
tCYC
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
ADV
tADVS
tADH
Suspend Burst
tADVH
tAS
ADD
GW
RD1
RD3
RD2
tAH
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
OE
tCEH
tEOV
tCES
tOEHZ
tDOH
tCDV
3a
Data Out
2d
2a
2b
2c
1a
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
19. RDx stands for Read Data from Address X.
Document #: 38-05249 Rev. *A
Page 19 of 26
CY7C1383BV25
CY7C1381BV25
Switching Waveforms (continued)
Read/Write Cycle Timing[ 17, 18, 19, 20]
Read/Write Timing
tCYC
tCL
tCH
CLK
tAH
tAS
A
D
B
C
ADD
tADH
tADS
ADSP
tADH
tADS
ADSC
tADVH
tADVS
ADV
tCEH
tCES
CE1
CE
tCEH
tCES
tWES
tWEH
WE
OE
ADSP ignored
with CE1 HIGH
tEOHZ
tCLZ
Data
Q
(B+3)
D
(C+1)
D
(C+2)
D
(C+3)
Q
(B+2)
Q
(B+1)
Q(B)
Q(B)
D(C)
Q(D)
Q(A)
In/Out
tCDV
tDOH
tCHZ
WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table).
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
Note:
20. Device originally deselected.
Document #: 38-05249 Rev. *A
Page 20 of 26
CY7C1383BV25
CY7C1381BV25
Switching Waveforms (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
Three-state
tEOLZ
I/Os
ZZ Mode Timing [20, 21]
CLK
ADSP
HIGH
ADSC
CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
ICC
ICC(active)
tZZREC
ICCZZ
I/Os
Three-state
Note:
21. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05249 Rev. *A
Page 21 of 26
CY7C1383BV25
CY7C1381BV25
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
117
100
83
Ordering Code
Package Type
CY7C1381BV25-117AC
CY7C1381BV25-100AC
CY7C1381BV25-83AC
CY7C1383BV25-117AC
CY7C1383BV25-100AC
CY7C1383BV25-183C
CY7C1381BV25-117BGC
CY7C1381BV25-100BGC
CY7C1381BV25-83BGC
CY7C1383BV25-117BGC
CY7C1383BV25-100BGC
CY7C1383BV25-83BGC
CY7C1381BV25-117BZC
CY7C1381BV25-100BZC
CY7C1381BV25-83BZC
CY7C1383BV25-117BZC
CY7C1383BV25-100BZC
CY7C1383BV25-83BZC
CY7C1381BV25-100AI
CY7C1381BV25-83AI
A101
BG119
BA165A
100-lead Thin Quad Flat Pack
Commercial
117
100
83
117
100
83
119-ball BGA
117
100
83
117
100
83
165-ball FBGA
117
100
83
100
83
A101
BG119
BA165A
100-lead Thin Quad Flat Pack
119-ball BGA
Industrial
100
83
CY7C1383BV25-100AI
CY7C1383BV25-83AI
100
83
CY7C1381BV25-100BGI
CY7C1381BV25-83BGI
CY7C1383BV25-100BGI
CY7C1383BV25-83BGI
CY7C1381BV25-100BZI
CY7C1381BV25-83BZI
CY7C1383BV25-100BZI
CY7C1383BV25-83BZI
100
83
100
83
165-ball FBGA
100
83
Shaded areas contain advance information.
Document #: 38-05249 Rev. *A
Page 22 of 26
CY7C1383BV25
CY7C1381BV25
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05249 Rev. *A
Page 23 of 26
CY7C1383BV25
CY7C1381BV25
Package Diagrams (continued)
119-lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*A
Document #: 38-05249 Rev. *A
Page 24 of 26
CY7C1383BV25
CY7C1381BV25
Package Diagrams (continued)
165-ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*B
All product and company names mentioned in this document are the trademarks of their repsective holders.
Document #: 38-05249 Rev. *A
Page 25 of 26
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1383BV25
CY7C1381BV25
Document Title: CY7C1381BV25/CY7C1383BV25 512K x 36 / 1M x 18 Flow-Thru SRAM
Document Number:38-05249
Orig. of
Change
REV.
ECN No.
Issue Date
Description of Change
**
113651
05/03/02
CJM
Changed Spec from: 38-01076 to 38-05249
Added ZZ pin functionality
Changed VOH and VOL values to reflect new char. values
Modified ESD voltage to 1500V
Changed tDOH to 1.3 ns
Added Thermal Resistance table
Changed IDD and ISB values to reflect new char values
Added 165-ball fBGA packaging
Added I-temp
Added 83 MHz
Changed tEOHZ from 3.5 to 4.0 ns for 117 MHz
Changed set-up time from 2.0 ns to 1.5 ns
Changed tEOV to char. values
*A
123851
01/18/03
RBI
Add power up requirements to operating range information
Document #: 38-05249 Rev. *A
Page 26 of 26
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