CY7C1386D_11 [CYPRESS]
18-Mbit (512 K x 36/1 M x 18) Pipelined DCD Sync SRAM; 18兆位（ 512K的X 36/1的M× 18 ）流水线DCD同步SRAM
| 型号： | CY7C1386D_11 |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit (512 K x 36/1 M x 18) Pipelined DCD Sync SRAM |
| 文件： | 总36页 (文件大小：1183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
18-Mbit (512 K × 36/1 M × 18) Pipelined
DCD Sync SRAM
18-Mbit (512
K × 36/1 M × 18) Pipelined DCD Sync SRAM
Features
Functional Description
■ Supports bus operation up to 250 MHz
The
CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
SRAM[1] integrates 512 K × 36/1 M × 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth expansion
chip enables (CE2 and CE3 [2]), burst control inputs (ADSC,
■ Available speed grades are 250, 200, and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ Optimal for performance (double-cycle deselect)
■ Depth expansion without wait state
■ 3.3 V core power supply (VDD
)
ADSP,
ADV), write enables (
, and BWE), and global
BWX
and
write (GW). Asynchronous inputs include the output enable (OE)
and the ZZ pin.
■ 2.5 V or 3.3 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 2.6 ns (for 250 MHz device)
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
■ Provides high performance 3-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium
Interleaved or linear burst sequences
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see on page 4 and Truth Table on page 11 for further
details). Write cycles can be one to four bytes wide as controlled
by the byte write control inputs. GW active LOW causes all bytes
to be written. This device incorporates an additional pipelined
enable register which delays turning off the output buffers an
additional cycle when a deselect is executed.This feature allows
depth expansion without penalizing system performance.
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ CY7C1386D/CY7C1387D available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA
package. CY7C1386F/CY7C1387F available in Pb-free and
non Pb-free 119-ball BGA package
The
CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
■ IEEE 1149.1 JTAG-compatible boundary scan
■ ZZ sleep mode option
operates from a +3.3 V core power supply while all outputs
operate with a +3.3 V or +2.5 V supply. All inputs and outputs are
JEDEC-standard and JESD8-5-compatible.
Selection Guide
Description
Maximum access time
250 MHz
2.6
200 MHz
3.0
167 MHz
3.4
Unit
ns
Maximum operating current
350
300
275
mA
mA
Maximum CMOS standby current
70
70
70
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE and CE are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in Single Chip Enable.
3
2
Cypress Semiconductor Corporation
Document Number: 38-05545 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 12, 2011
[+] Feedback
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Logic Block Diagram – CY7C1386D/CY7C1386F [3] (512 K × 36)
ADDRESS
REGISTER
A0,A1,A
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ D, DQP
BYTE
WRITE REGISTER
D
DQ D, DQP
BYTE
WRITE DRIVER
D
BW
BW
D
DQ
BYTE
WRITE DRIVER
c,DQP C
DQ
BYTE
WRITE REGISTER
c,DQP C
MEMORY
ARRAY
C
OUTPUT
OUTPUT
REGISTERS
SENSE
AMPS
DQs
DQP
DQP
DQP
DQP
BUFFERS
E
A
B
DQ
BYTE
WRITE DRIVER
B,DQP B
DQ
BYTE
WRITE REGISTER
B,DQP B
BW
BW
B
C
D
DQ A, DQP
BYTE
A
DQ A, DQP
BYTE
A
A
WRITE DRIVER
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
OE
1
2
3
ZZ
CONTROL
Logic Block Diagram – CY7C1387D/CY7C1387F [3] (1 M × 18)
ADDRESS
REGISTER
A0, A1, A
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
CLR
Q0
ADSC
ADSP
DQ B , DQP
BYTE
B
DQ B, DQP
BYTE
B
OUTPUT
BUFFERS
BW
B
OUTPUT
REGISTERS
DQ s,
DQP
DQP
WRITE REGISTER
SENSE
AMPS
MEMORY
ARRAY
A
B
DQ A, DQP
BYTE
A
E
DQ A , DQP
BYTE
WRITE REGISTER
BW
A
BWE
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
1
2
PIPELINED
ENABLE
CE
3
OE
SLEEP
CONTROL
Note
3. CY7C1386F and CY7C1387F have only 1 Chip Enable (CE ).
1
Document Number: 38-05545 Rev. *H
Page 2 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................7
Functional Overview ........................................................8
Single Read Accesses ................................................8
Single Write Accesses Initiated by ADSP ...................9
Single Write Accesses Initiated by ADSC ...................9
Burst Sequences .........................................................9
Sleep Mode .................................................................9
Interleaved Burst Address Table
(MODE = Floating or VDD) ...............................................10
Linear Burst Address Table (MODE = GND) .............10
ZZ Mode Electrical Characteristics ............................10
Truth Table ......................................................................11
Truth Table for Read/Write ............................................12
Truth Table for Read/Write ............................................12
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................13
Disabling the JTAG Feature ......................................13
Test Access Port (TAP) .............................................13
PERFORMING A TAP RESET ..................................13
TAP REGISTERS ......................................................13
TAP Instruction Set ...................................................13
TAP Controller State Diagram .......................................15
TAP Controller Block Diagram ......................................15
TAP Timing Diagram ......................................................15
TAP AC Switching Characteristics ...............................16
3.3 V TAP AC Test Conditions .......................................17
3.3 V TAP AC Output Load Equivalent .........................17
2.5 V TAP AC Test Conditions .......................................17
2.5 V TAP AC Output Load Equivalent .........................17
TAP DC Electrical Characteristics and
Operating Conditions .....................................................17
Identification Register Definitions ................................18
Scan Register Sizes .......................................................18
Identification Codes .......................................................18
Boundary Scan Order ....................................................19
Boundary Scan Order ....................................................20
Maximum Ratings ...........................................................21
Operating Range .............................................................21
Electrical Characteristics ...............................................21
Capacitance ....................................................................22
Thermal Resistance ........................................................22
AC Test Loads and Waveforms .....................................23
Switching Characteristics ..............................................24
Switching Waveforms ....................................................25
Ordering Information ......................................................29
Ordering Code Definitions .........................................29
Package Diagrams ..........................................................30
Acronyms ........................................................................33
Document Conventions .................................................33
Units of Measure .......................................................33
Document History Page .................................................34
Sales, Solutions, and Legal Information ......................36
Worldwide Sales and Design Support .......................36
Products ....................................................................36
PSoC Solutions .........................................................36
Document Number: 38-05545 Rev. *H
Page 3 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Pin Configurations
Figure 1. 100-pin TQFP (3 Chip Enable)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
NC
14
VDD
15
NC
VDD
ZZ
CY7C1387D
(1 M × 18)
CY7C1386D
(512 K × 36)
NC
16
VDD
ZZ
VSS
17
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
20
21
VDDQ
VSSQ
DQD
22
DQD
23
DQD
24
DQD
25
26
27
NC
VSSQ
VDDQ
DQD
DQD
29
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
28
DQPD
30
Document Number: 38-05545 Rev. *H
Page 4 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Pin Configurations (continued)
Figure 2. 119-ball BGA (1 Chip Enable)
CY7C1386F (512 K × 36)
1
2
3
4
5
6
7
A
VDDQ
A
A
A
A
VDDQ
ADSP
ADSC
VDD
A
A
B
C
NC/288M
NC/144M
A
A
A
A
A
A
NC/576M
NC/1G
D
E
F
DQC
DQC
VDDQ
DQPC
DQC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
VDDQ
CE1
DQB
OE
G
H
J
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
BWC
VSS
NC
BWB
VSS
NC
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
ADV
GW
VDD
K
DQD
VSS
CLK
NC
VSS
L
M
N
DQD
VDDQ
DQD
DQD
DQD
DQD
DQA
DQA
DQA
DQA
VDDQ
DQA
BWD
VSS
VSS
BWA
VSS
VSS
BWE
A1
DQD
NC
DQPD
A
VSS
A0
VSS
NC
DQPA
A
DQA
NC
P
R
MODE
VDD
T
NC
NC/72M
TMS
A
A
A
NC/36M
NC
ZZ
VDDQ
TDI
TCK
TDO
VDDQ
U
CY7C1387F (1 M × 18)
2
1
3
A
4
5
A
6
A
7
VDDQ
NC/576M
NC/1G
NC
VDDQ
A
A
A
B
C
D
E
F
ADSP
NC/288M
NC/144M
DQB
A
A
A
ADSC
VDD
A
A
A
A
NC
DQB
NC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPA
NC
DQA
NC
DQA
CE1
VDDQ
VDDQ
OE
NC
DQB
VDDQ
DQB
NC
VDD
NC
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
G
H
J
BWB
VSS
NC
ADV
GW
VDD
K
NC
DQB
VSS
CLK
NC
VSS
NC
DQA
L
M
N
P
DQB
VDDQ
DQB
NC
NC
DQB
NC
NC
VSS
VSS
VSS
DQA
NC
NC
VDDQ
NC
BWA
VSS
BWE
A1
VSS
VSS
DQA
NC
DQPB
A0
DQA
R
T
NC
A
A
MODE
A
VDD
NC/36M
TCK
NC
A
A
A
NC
ZZ
NC/72M
VDDQ
TMS
TDI
TDO
NC
VDDQ
U
Document Number: 38-05545 Rev. *H
Page 5 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Pin Configurations (continued)
Figure 3. 165-ball FBGA (3 Chip Enable)
CY7C1386D (512 K × 36)
1
2
A
3
4
5
6
7
8
9
10
A
11
NC
NC/288M
NC/144M
DQPC
A
B
C
D
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
OE
BWE
GW
ADV
ADSP
VDDQ
VDDQ
A
CE2
A
NC/512M
DQPB
DQB
NC
DQC
VDDQ
VDDQ
VSS
VSS
VSS
VDD
NC/1G
DQB
DQC
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE NC/36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1387D (1 M × 18)
1
2
A
3
4
5
NC
6
7
8
9
10
A
11
A
NC/288M
NC/144M
NC
A
B
C
D
BWB
NC
CE3
CLK
VSS
VSS
CE1
CE2
BWE
GW
VSS
VSS
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
A
BWA
VSS
VSS
A
NC/576M
DQPA
DQA
NC
VDDQ
VDDQ
VSS
VDD
VSS
NC/1G
NC
NC
DQB
VDD
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
‘VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
NC/72M
TDI
A1
A0
TDO
MODE NC/36M
A
A
TMS
TCK
A
A
A
A
R
Document Number: 38-05545 Rev. *H
Page 6 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK
if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [4] are sampled active. A1: A0 are fed to the
two-bit counter.
BWA,BWB,
BWC, BWD
Input-
Synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
on the rising edge of CLK.
GW
BWE
CLK
CE1
Input-
Synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
is conducted (all bytes are written, regardless of the values on BWX and BWE).
Input-
Synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
LOW to conduct a byte write.
Input-
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 [4] to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when
a new external address is loaded.
[4]
CE2
Input-
Synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3[4] to select or deselect the device. CE2 is sampled only when a new external address is loaded.
[4]
CE3
Input-
Synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select or deselect the device. Not connected for BGA. Where referenced, CE3 [4] is assumed
active throughout this document for BGA. CE3 is sampled only when a new external address is loaded.
OE
Input-
Asynchronous
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Synchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
ZZ
Input-
Synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input-
Asynchronous
ZZ sleep input, active HIGH. When asserted HIGH places the device in a non-time critical sleep
condition with data integrity preserved. For normal operation, this pin has to be LOW. ZZ pin has an
internal pull down.
I/O-
Synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
DQs,
DQPX
addresses presented during the previous
cycle. The direction of the pins is
clock rise of the read
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.
VDD
VSS
Power Supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
VSSQ
VDDQ
I/O Ground Ground for the I/O circuitry.
I/O Power Power supply for the I/O circuitry.
Supply
Note
4. CE and CE are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in Single Chip Enable.
3
2
Document Number: 38-05545 Rev. *H
Page 7 of 36
[+] Feedback
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Pin Definitions (continued)
Name
I/O
Description
MODE
Input-
Static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode pin has an internal pull up.
TDO
TDI
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
not used, this pin must be disconnected. This pin is not available on TQFP packages.
output
Synchronous
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
input
Synchronous
TMS
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
input
Synchronous
TCK
NC
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be connected to VSS.
This pin is not available on TQFP packages.
–
–
No Connects. Not internally connected to the die.
NC/(36 M,
72 M,
These pins are not connected. They are used for expansion up to 36 M, 72 M, 144 M, 288 M, 576 M,
and 1G densities.
144 M,
288 M,
576 M, 1 G)
Single Read Accesses
Functional Overview
This access is initiated when the following conditions are
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals (GW,
BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH.
The address presented to the address inputs is stored into the
address advancement logic and the address register while being
presented to the memory core. The corresponding data is
allowed to propagate to the input of the output registers. At the
rising edge of the next clock the data is allowed to propagate
through the output register and onto the data bus within tCO if OE
is active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its outputs
are always tristated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported.
The
CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
supports secondary cache in systems using either a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium® and i486 processors. The linear burst
sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can
either the processor address strobe (ADSP)
be initiated with
or the controller
address strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F is a
double cycle deselect part. After the SRAM is deselected at clock
rise by the chip select and either ADSP or ADSC signals, its
output tristates immediately after the next clock rise.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
[5]
Synchronous chip selects CE1, CE2, CE3
and an
asynchronous output enable (OE) provide for easy bank
output tristate control.
is ignored if
is
CE1
selection and
HIGH.
ADSP
Note
5. CE and CE are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in Single Chip Enable.
3
2
Document Number: 38-05545 Rev. *H
Page 8 of 36
[+] Feedback
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
core. If a byte write is conducted, only the selected bytes are
written. Bytes not selected during a byte write operation remains
unaltered. A synchronous self timed write mechanism has been
provided to simplify the write operations.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW and (2) chip
select is asserted active. The address presented is loaded into
the address register and the address advancement logic while
being delivered to the memory core. The write signals (GW,
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F is a
common I/O device, the output enable (OE) must be deasserted
HIGH before presenting data to the DQX inputs. This tristates the
output drivers. As a safety precaution, DQX are automatically
tristated whenever a write cycle is detected, regardless of the
state of OE.
BWE, and
cycle.
) and ADV inputs are ignored during this first
BWX
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the
corresponding address location in the memory core. If GW is
HIGH, the write operation is controlled by BWE and BWX signals.
Burst Sequences
The
CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
provides a two-bit wraparound counter, fed by A[1:0], that
implements either an interleaved or linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The linear burst sequence is
designed to support processors that follow a linear burst
sequence. The burst sequence is user selectable through the
MODE input.
The
CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
provides byte write capability that is described in the write cycle
description table. Asserting the byte write enable input (BWE)
with the selected byte write input, selectively writes to the desired
bytes. Bytes not selected during a byte write operation remains
unaltered. A synchronous self timed write mechanism has been
provided to simplify the write operations.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F is a
common I/O device, the output enable (OE) must be deasserted
HIGH before presenting data to the DQ inputs. This tristates the
output drivers. As a safety precaution, DQ are automatically
tristated whenever a write cycle is detected, regardless of the
state of OE.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CEs, ADSP, and
ADSC must remain inactive for the duration of tZZREC after the
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) chip select is asserted active, and (4) the appropriate
combination of the write inputs (GW, BWE, and
) are
BWX
ZZ input returns LOW.
asserted active to conduct a write to the desired byte(s). ADSC
triggered write accesses require a single clock cycle to complete.
The address presented is loaded into the address register and
the address advancement logic while being delivered to the
memory core. The ADV input is ignored during this cycle. If a
global write is conducted, the data presented to the DQX is
written into the corresponding address location in the memory
Document Number: 38-05545 Rev. *H
Page 9 of 36
[+] Feedback
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
)
DD
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
80
Unit
mA
ns
ZZ > VDD– 0.2 V
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
tZZS
–
2tCYC
–
2tCYC
–
tZZREC
tZZI
ns
ZZ Active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ Inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 38-05545 Rev. *H
Page 10 of 36
[+] Feedback
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Truth Table
The Truth Table for CY7C1386D, CY7C1386F, CY7C1387D, and CY7C1387F follow.[6, 7, 8, 9, 10]
Operation
Add. Used CE1 CE2 CE3 ZZ
ADSP
ADSC ADV WRITE OE CLK
DQ
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Sleep mode, power-down
Read cycle, begin burst
None
None
H
L
L
L
L
X
L
L
L
L
L
X
X
H
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L–H Tristate
L–H Tristate
L–H Tristate
L–H Tristate
L–H Tristate
None
X
L
L
None
H
H
X
L
None
X
X
H
H
H
H
H
X
X
X
L
None
X
X
X
L
X
Tristate
Q
External
External
External
External
External
Next
L–H
Read cycle, begin burst
L
L
H
X
L
L–H Tristate
Write cycle, begin burst
L
H
H
H
H
H
X
L–H
L–H
D
Q
Read cycle, begin burst
L
L
H
H
H
H
H
Read cycle, begin burst
L
L
H
L
L–H Tristate
L–H
L–H Tristate
L–H
L–H Tristate
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
X
X
X
H
H
H
Q
Next
L
H
L
Next
L
Q
Read cycle, continue burst
Write cycle, continue burst
Write cycle, continue burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Write cycle, suspend burst
Write cycle, suspend burst
Next
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
X
H
X
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
L
L
H
L
H
X
X
L
Next
L–H
L–H
L–H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L–H Tristate
L–H
L–H Tristate
Q
H
X
X
L–H
L–H
D
D
L
Notes
6. X = Do not care, H = Logic HIGH, L = Logic LOW.
7. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
9. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after
X
the ADSP or with the assertion of
. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care
ADSC
for the remainder of the write cycle.
10. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05545 Rev. *H
Page 11 of 36
[+] Feedback
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1386D and CY7C1386F follows.[11, 12]
Function (CY7C1386D/CY7C1386F)
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
X
H
H
L
BWA
X
H
L
Read
Read
Write byte A – (DQA and DQPA)
Write byte B – (DQB and DQPB)
Write bytes B, A
L
L
H
L
L
L
Write byte C – (DQC and DQPC)
Write bytes C, A
L
H
H
L
H
L
L
L
Write bytes C, B
L
L
H
L
Write bytes C, B, A
Write byte D – (DQD and DQPD)
Write bytes D, A
L
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
Write bytes D, B
L
L
H
L
Write bytes D, B, A
Write bytes D, C
L
L
L
L
L
H
H
L
H
L
Write bytes D, C, A
Write bytes D, C, B
Write all bytes
L
L
L
L
L
L
H
L
L
L
L
L
Write all bytes
X
X
X
X
X
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1387D and CY7C1387F follows.[11, 12]
Function (CY7C1387D/CY7C1387F)
GW
H
BWE
BWB
X
BWA
X
Read
Read
H
L
L
L
L
X
H
H
H
Write byte A – (DQA and DQPA)
Write byte B – (DQB and DQPB)
Write all bytes
H
H
L
H
L
H
H
L
L
Write all bytes
L
X
X
Notes
11. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
12. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid appropriate write is done based on which byte write is active.
X
Document Number: 38-05545 Rev. *H
Page 12 of 36
[+] Feedback
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The
CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
incorporates a serial boundary scan test access port (TAP). This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3 V or 2.5 V I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 15. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
The
CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
can be left unconnected. Upon power-up, the device comes up
in a reset state which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
Test Access Port (TAP)
SRAM with minimal delay. The bypass register is set LOW (VSS
when the BYPASS instruction is executed.
)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
Test Mode Select (TMS)
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The boundary scan order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register.
Identification (ID) Register
The ID register is loaded with a vendor specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 18.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register.
TAP Instruction Set
Performing a TAP Reset
Overview
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Identification
Codes on page 18. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
Document Number: 38-05545 Rev. *H
Page 13 of 36
[+] Feedback
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
the instruction after it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
IDCODE
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required; that is, while data captured is
shifted out, the preloaded data can be shifted in.
The IDCODE instruction causes a vendor specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
EXTEST Output Bus Tristate
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command places
all SRAM outputs into a high Z state.
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #85
(for 119-ball BGA package) or bit #89 (for 165-ball FBGA
package). When this scan cell, called the “extest output bus
tristate,” is latched into the preload register during the
Update-DR state in the TAP controller, it directly controls the
state of the output (Q-bus) pins, when the EXTEST is entered as
the current instruction. When HIGH, it enables the output buffers
to drive the output bus. When LOW, this bit places the output bus
into a high Z condition.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. As there is a
large difference in the clock frequencies, it is possible that during
the Capture-DR state, an input or output undergoes a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that is captured. Repeatable results
may not be possible.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered-up, and also when the TAP
controller is in the Test-Logic-Reset state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 38-05545 Rev. *H
Page 14 of 36
[+] Feedback
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
TAP Controller State Diagram
TAP Controller Block Diagram
TEST-LOGIC
1
0
RESET
0
Bypass Register
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
2
1
0
0
0
Selection
Circuitry
Instruction Register
S
election
TDI
TDO
1
1
CAPTURE-DR
CAPTURE-IR
Circuitr
y
31 30 29
.
.
.
2
1
0
0
0
0
Identification Register
SHIFT-DR
0
SHIFT-IR
0
x
.
.
.
.
. 2 1
1
1
Boundary Scan Register
TAP CONTROLLER
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
1
0
PAUSE-IR
1
0
TCK
TMS
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0 or 1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Timing Diagram
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 38-05545 Rev. *H
Page 15 of 36
[+] Feedback
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
TAP AC Switching Characteristics
Over the Operating Range
Parameter [13, 14]
Clock
Description
Min
Max
Unit
tTCYC
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
TCK clock LOW to TDO valid
TCK Clock LOW to TDO invalid
–
0
10
–
ns
ns
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
Notes
13. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
14. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document Number: 38-05545 Rev. *H
Page 16 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times ...................................................1 ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50 Ω
20pF
ZO= 50 Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter[15]
Description
Test Conditions
IOH = –4.0 mA, VDDQ = 3.3 V
IOH = –1.0 mA, VDDQ = 2.5 V
Min
2.4
2.0
2.9
2.1
–
Max
Unit
V
VOH1
Output HIGH voltage
–
–
V
VOH2
VOL1
VOL2
VIH
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input load current
IOH = –100 µA
VDDQ = 3.3 V
DDQ = 2.5 V
IOL = 8.0 mA, VDDQ = 3.3 V
OL = 8.0 mA, VDDQ = 2.5 V
–
V
V
–
0.4
V
V
I
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
VDDQ = 2.5 V
–
0.2
V
–
0.2
V
VDDQ = 3.3 V
2.0
1.7
–0.5
–0.3
–5
VDD + 0.3
VDD + 0.3
0.7
V
V
DDQ = 2.5 V
VDDQ = 3.3 V
DDQ = 2.5 V
GND < VIN < VDDQ
V
VIL
V
V
0.7
V
IX
5
µA
Note
15. All voltages referenced to V (GND).
SS
Document Number: 38-05545 Rev. *H
Page 17 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Identification Register Definitions
CY7C1386D/CY7C1386F CY7C1387D/CY7C1387F
Instruction Field
Description
(512 K × 36)
(1 M × 18)
Revision Number (31:29)
Device Depth (28:24) [16]
000
000
Describes the version number
Reserved for internal use.
01011
101110
01011
Device Width (23:18) 119-ball BGA
101110
Defines the memory type and
architecture.
Device Width (23:18) 165-ball FBGA
000110
000110
Defines the memory type and
architecture.
Cypress Device ID (17:12)
100101
010101
Defines the width and density.
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
Allows unique identification of SRAM
vendor.
ID Register Presence Indicator (0)
1
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (× 18)
Bit Size (× 36)
Instruction
Bypass
ID
3
3
1
1
32
85
89
32
85
89
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
Identification Codes
Instruction
EXTEST
Code
Description
000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
SRAM outputs to high Z state.
IDCODE
001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operations.
SAMPLE Z
010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
SRAM output drivers to a high Z state.
RESERVED
011 Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect SRAM operation.
RESERVED
RESERVED
BYPASS
101 Do Not Use. This instruction is reserved for future use.
110 Do Not Use. This instruction is reserved for future use.
111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
Note
16. Bit #24 is 1 in the register definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05545 Rev. *H
Page 18 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Boundary Scan Order
119-ball BGA [17, 18]
Bit #
1
Ball ID
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Ball ID
F6
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Ball ID
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
Bit #
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
L1
H4
T4
T5
T6
R5
L5
2
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M2
N1
3
4
P1
5
K1
6
L2
7
R6
U6
R7
T7
P6
N7
M6
L7
N2
P2
8
9
R3
10
11
12
13
14
15
16
17
18
19
20
21
22
T1
R1
T2
L3
R2
K6
P7
N6
L6
G1
H2
D1
E2
G2
H1
J3
T3
L4
N4
P4
K7
J5
M4
A5
K4
E4
Internal
H6
G7
2K
Notes
17. Balls that are NC (No Connect) are preset LOW.
18. Bit#85 is preset HIGH.
Document Number: 38-05545 Rev. *H
Page 19 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Boundary Scan Order
165-ball BGA [19, 20]
Bit #
1
Ball ID
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
N6
N7
2
3
N10
P11
P8
4
F2
5
G2
H1
H3
J1
6
R8
7
R9
8
P9
B9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
C10
A8
K1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
L1
B8
M1
J2
A7
B7
K2
B6
L2
A6
M2
N1
N2
P1
B5
A5
A4
B4
R1
R2
P3
B3
A3
A2
R3
P2
H10
G11
F11
E11
D11
G10
F10
E10
B2
C2
R4
P4
B1
A1
N5
P6
C1
D1
R6
Internal
E1
F1
Notes
19. Balls that are NC (No Connect) are preset LOW.
20. Bit#89 is preset HIGH.
Document Number: 38-05545 Rev. *H
Page 20 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Maximum Ratings
Operating Range
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Ambient
Temperature
Range
VDD
VDDQ
Storage temperature ................................ –65 °C to +150 °C
Commercial 0 °C to +70 °C
Industrial –40 °C to +85 °C
3.3 V– 5% / 2.5V–5%to
Ambient temperature
with power applied ................................... –55 °C to +125 °C
+10%
VDD
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
Neutron Soft Error Immunity
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
Test
Parameter Description
Conditions
Typ Max* Unit
DC input voltage .................................–0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
LSBU
LMBU
SEL
Logical
single-bit
upsets
25 °C
25 °C
85 °C
361 394
FIT/
Mb
Static discharge voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Logical
multi-bit
upsets
0
0
0.01 FIT/
Mb
Latch-up current ....................................................> 200 mA
Single event
latch-up
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation
of Terrestrial Failure Rates”
Electrical Characteristics
Over the Operating Range
Parameter [21, 22]
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
Unit
V
VDD
3.6
VDDQ
for 3.3 V I/O
for 2.5 V I/O
VDD
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH voltage [21]
Input LOW voltage [21]
for 3.3 V I/O, IOH = –4.0 mA
for 2.5 V I/O, IOH = –1.0 mA
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 3.3 V I/O
–
V
2.0
–
V
–
0.4
V
–
0.4
VDD + 0.3 V
VDD + 0.3 V
0.8
V
2.0
V
for 2.5 V I/O
1.7
V
for 3.3 V I/O
–0.3
–0.3
–5
V
for 2.5 V I/O
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
5
µA
Input current of MODE
Input = VSS
–30
–
–
5
µA
µA
µA
µA
µA
Input = VDD
Input current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
Output leakage current
GND VI VDDQ, Output Disabled
–5
Notes
21. Overshoot: V (AC) < V +1.5 V (pulse width less than t
/2), undershoot: V (AC) > –2 V (pulse width less than t
/2).
CYC
IH
DD
CYC
IL
22. T
: assumes a linear ramp from 0 V to V
within 200 ms. During this time V < V and V
< V
.
Power-up
DD(min)
IH
DD
DDQ
DD
Document Number: 38-05545 Rev. *H
Page 21 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Electrical Characteristics (continued)
Over the Operating Range
Parameter [21, 22]
Description
Test Conditions
4 ns cycle, 250 MHz
Min
–
Max
350
300
275
160
150
140
Unit
mA
mA
mA
mA
mA
mA
IDD
VDD operating supply current
VDD = Max.,
OUT = 0 mA,
I
5 ns cycle, 200 MHz
6 ns cycle, 167 MHz
4 ns cycle, 250 MHz
5 ns cycle, 200 MHz
6 ns cycle, 167 MHz
–
f = fMAX = 1/tCYC
–
ISB1
Automatic CE power-down
current—TTL inputs
VDD = Max,
–
device deselected,
VIN VIH or VIN VIL
f = fMAX = 1/tCYC
–
–
ISB2
Automatic CE power-down
current—CMOS inputs
VDD = Max,
All speeds
–
70
mA
device deselected,
VIN 0.3 V or
VIN > VDDQ – 0.3 V,
f = 0
ISB3
Automatic CE power-down
current—CMOS inputs
VDD = Max,
4 ns cycle, 250 MHz
5 ns cycle, 200 MHz
6 ns cycle, 167 MHz
–
–
–
135
130
125
mA
mA
mA
device deselected, or
VIN 0.3 V or
VIN > VDDQ – 0.3 V
f = fMAX = 1/tCYC
ISB4
Automatic CE power-down
current—TTL inputs
VDD = Max,
All speeds
–
80
mA
device deselected,
VIN VIH or VIN VIL,
f = 0
Capacitance
100-pin TQFP 119-ball BGA 165-ball FBGA
Parameter[23]
Description
Test Conditions
Unit
Max
Max
Max
CIN
Input capacitance
Clock input capacitance
I/O capacitance
TA = 25 C, f = 1 MHz,
5
5
5
8
8
8
9
9
9
pF
pF
pF
V
DD = 3.3 V, VDDQ = 2.5 V
CCLK
CIO
Thermal Resistance
100-pin TQFP 119-ball BGA 165-ball FBGA
Parameter[23]
Description
Test Conditions
Unit
Package
Package
Package
JA
Thermal resistance
(junction to ambient)
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, in
accordance with
28.66
23.8
20.7
°C/W
JC
Thermal resistance
(junction to case)
4.08
6.2
4.0
°C/W
EIA/JESD51.
Note
23. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05545 Rev. *H
Page 22 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
ALL INPUT PULSES
VDDQ
GND
OUTPUT
90%
Z = 50
90%
0
R = 50
10%
10%
1 ns
L
5 pF
R = 351
1 ns
V
= 1.5 V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50
0
R = 50
10%
L
5 pF
R = 1538
1 ns
1 ns
V
= 1.25 V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document Number: 38-05545 Rev. *H
Page 23 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Switching Characteristics
Over the Operating Range
-250
-200
-167
Parameter [24, 25]
Description
Unit
Min
Max
Min
Max
Min
Max
tPOWER
Clock
tCYC
VDD(Typical) to the first access [26]
1
–
1
–
1
–
ms
Clock cycle time
Clock HIGH
4.0
1.7
1.7
–
–
–
5.0
2.0
2.0
–
–
–
6.0
2.2
2.2
–
–
–
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCO
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z [27, 28, 29]
–
1.0
1.0
–
2.6
–
–
1.3
1.3
–
3.0
–
–
1.3
1.3
–
3.4
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
–
–
tCHZ
Clock to high Z [27, 28, 29]
2.6
2.6
–
3.0
3.0
–
3.4
3.4
–
tOEV
OE LOW to output valid
–
–
–
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to output low Z [27, 28, 29]
OE HIGH to output high Z [27, 28, 29]
0
0
0
–
2.6
–
3.0
–
3.4
Address setup before CLK rise
ADSC, ADSP setup before CLK rise
ADV setup before CLK rise
1.2
1.2
1.2
1.2
–
–
–
–
1.4
1.4
1.4
1.4
–
–
–
–
1.5
1.5
1.5
1.5
–
–
–
–
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX setup before CLK
rise
tDS
Data input setup before CLK rise
Chip enable setup before CLK rise
1.2
1.2
–
–
1.4
1.4
–
–
1.5
1.5
–
–
ns
ns
tCES
Hold Times
tAH
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
ADV hold after CLK rise
0.3
0.3
0.3
0.3
0.3
0.3
–
–
–
–
–
–
0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
tADVH
tWEH
tDH
GW, BWE, BWX hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
tCEH
Notes
24. Timing reference level is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
25. Test conditions shown in (a) of Figure 4 on page 23 unless otherwise noted.
26. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation can
POWER
DD
be initiated.
27. t
, t
,t
, and t
are specified with AC test conditions shown in (b) of Figure 4 on page 23. Transition is measured ±200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
28. At any voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data bus.
OEHZ
OELZ
CHZ
CLZ
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z
prior to low Z under the same system conditions.
29. This parameter is sampled and not 100% tested.
Document Number: 38-05545 Rev. *H
Page 24 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Switching Waveforms
Figure 5. Read Cycle Timing [30]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,BW
X
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
OEV
CO
t
t
CHZ
t
t
t
OELZ
OEHZ
DOH
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Q(A1)
Data Out (DQ)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
30.
Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BW LOW.
X
Document Number: 38-05545 Rev. *H
Page 25 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Switching Waveforms (continued)
Figure 6. Write Cycle Timing [31]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
BWE,
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
DH
t
DS
D(A2)
D(A2 + 1)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A1)
High-Z
Data in (D)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Single WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note
31.
Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BW LOW.
X
Document Number: 38-05545 Rev. *H
Page 26 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Switching Waveforms (continued)
Figure 7. Read/Write Cycle Timing [32, 33, 34]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Back-to-Back READs
Q(A2)
Q(A4)
Q(A4+3)
High-Z
BURST READ
Back-to-Back
WRITEs
Single WRITE
DON’T CARE
UNDEFINED
Notes
32.
Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BW LOW.
X
33. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
34. GW is HIGH.
Document Number: 38-05545 Rev. *H
Page 27 of 36
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CY7C1387D, CY7C1387F
Switching Waveforms (continued)
Figure 8. ZZ Mode Timing [35, 36]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
35. Device must be deselected when entering ZZ sleep mode. See cycle descriptions table for all possible signal conditions to deselect the device.
36. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05545 Rev. *H
Page 28 of 36
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CY7C1387D, CY7C1387F
Ordering Information
The table below contains only the parts that are currently available. If you do not see what you are looking for, please contact your
local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary
page at http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
CY7C1386D-167AXC
CY7C1387D-167AXC
CY7C1386D-200AXC
167
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
200
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY 7 C 13XX D - XXX A
X
C
Temperature Range:
C = Commercial = 0 C to +70 C
X = Pb-free; X Absent = Leaded
Package Type:
A = 100-pin TQFP
Speed Grade: XXX = 167 MHz / 200 MHz
Process Technology 90 nm
13XX = 1386 or 1387
1386 = DCD, 512 K × 36 (18 Mb)
1387 = DCD, 1 M × 18 (18 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05545 Rev. *H
Page 29 of 36
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CY7C1387D, CY7C1387F
Package Diagrams
Figure 10: 100-pin TQFP (14 × 20 × 1.4 mm) A100RA, 51-85050
51-85050 *D
Document Number: 38-05545 Rev. *H
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CY7C1387D, CY7C1387F
Package Diagrams (continued)
Figure 9. 119-ball PBGA (14 × 22 × 2.4 mm) BG119, 51-85115
51-85115 *C
Document Number: 38-05545 Rev. *H
Page 31 of 36
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CY7C1387D, CY7C1387F
Package Diagrams (continued)
Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter), 51-85180
51-85180 *C
Document Number: 38-05545 Rev. *H
Page 32 of 36
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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
BGA
CE
ball grid array
chip enable
Unit of Measure
°C
k
MHz
µA
µs
degree Celsius
CMOS
FBGA
I/O
complementary metal oxide semiconductor
fine-pitch ball grid array
input/output
kilo ohms
Mega Hertz
micro Amperes
micro seconds
milli Amperes
milli Volts
JTAG
LMBU
LSB
Joint Test Action Group
logical multiple-bit upsets
least significant bit
logical single-bit upsets
most significant bit
output enable
mA
mV
mm
ms
ns
LSBU
MSB
OE
milli meter
milli seconds
nano seconds
ohms
SEL
single event latch-up
static random access memory
test access port
SRAM
TAP
%
percent
pF
ps
pico Farad
pico seconds
Volts
TCK
TDI
test clock
test data-in
V
TDO
TMS
TQFP
TTL
test data-out
W
Watts
test mode select
thin quad flat pack
transistor-transistor logic
Document Number: 38-05545 Rev. *H
Page 33 of 36
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CY7C1387D, CY7C1387F
Document History Page
Document Title: CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F, 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM
Document Number: 38-05545
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
254550
288531
RKF
SYT
See ECN New data sheet
*A
See ECN Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 225 MHz Speed Bin
Added Pb-free information for 100-pin TQFP, 119 BGA and 165 FBGA
Packages.
Added comment of ‘Pb-free BG packages availability’ below the Ordering Infor-
mation
*B
326078
PCI
See ECN Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added description on EXTEST Output Bus Tristate
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000110 to 101110
Added separate row for 165 -FBGA Device Width (23:18)
Changed JA and JC for TQFP Package from 31 and 6 C/W to 28.66 and
4.08 C/W respectively
Changed JA and JC for BGA Package from 45 and 7 C/W to 23.8 and
6.2 C/W respectively
Changed JA and JC for FBGA Package from 46 and 3 C/W to 20.7 and
4.0 C/W respectively
Modified VOL, VOH test conditions
Removed comment of ‘Pb-free BG packages availability’ below the Ordering
Information
Updated Ordering Information Table
*C
418125
NXR
See ECN Converted from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 18.
Changed the IX current values of MODE on page # 18 from –5 A and 30 A
to –30 A and 5 A.
Changed the IX current values of ZZ on page # 18 from –30 A and 5 A to
–5 A and 30 A.
Changed VIH < VDD to VIH < VDDon page # 18.
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Updated Ordering Information Table.
*D
475009
VKN
See ECN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
*E
*F
*G
793579
2756940
3006369
VKN
VKN
NJY
See ECN Added Part numbers CY7C1386F and CY7C1387F
Added footnote# 3 regarding Chip Enable
Updated Ordering Information table
08/27/2009 Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information.
08/12/10
Template update.
Added Ordering Code Definitions.
Added Acronyms.
Document Number: 38-05545 Rev. *H
Page 34 of 36
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CY7C1387D, CY7C1387F
Document History Page (continued)
Document Title: CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F, 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM
Document Number: 38-05545
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*H
3309506
OSN
07/12/2011 Updated Package Diagrams.
Added Units of Measure.
Updated in new template.
Document Number: 38-05545 Rev. *H
Page 35 of 36
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CY7C1387D, CY7C1387F
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05545 Rev. *H
Revised July 12, 2011
Page 36 of 36
Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
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