CY7C138V-20JI
更新时间：2024-09-18 14:16:11
品牌：CYPRESS
描述：Dual-Port SRAM, 4KX8, 20ns, CMOS, PQCC68, PLASTIC, LCC-68
概述
规格参数
数据手册CY7C138V-20JI 概述
Dual-Port SRAM, 4KX8, 20ns, CMOS, PQCC68, PLASTIC, LCC-68 SRAM
CY7C138V-20JI 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | LCC | 包装说明： | PLASTIC, LCC-68 |
| 针数： | 68 | Reach Compliance Code： | compliant |
| ECCN代码： | EAR99 | HTS代码： | 8542.32.00.41 |
| 风险等级： | 5.86 | Is Samacsys： | N |
| 最长访问时间： | 20 ns | I/O 类型： | COMMON |
| JESD-30 代码： | S-PQCC-J68 | JESD-609代码： | e0 |
| 长度： | 24.2316 mm | 内存密度： | 32768 bit |
| 内存集成电路类型： | DUAL-PORT SRAM | 内存宽度： | 8 |
| 功能数量： | 1 | 端口数量： | 2 |
| 端子数量： | 68 | 字数： | 4096 words |
| 字数代码： | 4000 | 工作模式： | ASYNCHRONOUS |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 组织： | 4KX8 | 输出特性： | 3-STATE |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | QCCJ |
| 封装等效代码： | LDCC68,1.0SQ | 封装形状： | SQUARE |
| 封装形式： | CHIP CARRIER | 并行/串行： | PARALLEL |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 电源： | 3.3 V |
| 认证状态： | Not Qualified | 座面最大高度： | 5.08 mm |
| 最大待机电流： | 0.00005 A | 最小待机电流： | 2 V |
| 子类别： | SRAMs | 最大压摆率： | 0.195 mA |
| 最大供电电压 (Vsup)： | 3.6 V | 最小供电电压 (Vsup)： | 3 V |
| 标称供电电压 (Vsup)： | 3.3 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子面层： | Tin/Lead (Sn/Pb) | 端子形式： | J BEND |
| 端子节距： | 1.27 mm | 端子位置： | QUAD |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 24.2316 mm |
| Base Number Matches： | 1 |
CY7C138V-20JI 数据手册
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CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
• Fully asynchronous operation
• Automatic power-down
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 4K/8K/16K/32K x 8 organizations (CY7C0138V/144V/
006V/007V)
• 4K/8K/16K/32K x 9 organizations (CY7C0139V/145V/
016V/017V)
• 0.35-micron CMOS for optimum speed/power
• Expandable databusto16/18bitsormoreusingMaster/
Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 68-pin PLCC (all), 64-pin TQFP (7C006V &
7C144V)
[1]
• High-speed access: 15 /20/25 ns
• Low operating power
— Active: I = 115 mA (typical)
CC
— Standby: I
= 10 A (typical)
µ
• Pin-compatible and functionally equivalent to
IDT70V05, 70V06, and 70V07.
SB3
Logic Block Diagram
R/W
R/W
CE
L
R
R
R
CE
L
OE
OE
L
[2]
[2]
8/9
8/9
I/O –I/O
I/O –I/O
0L
7/8L
0R
7/8R
I/O
I/O
Control
Control
[3]
12–15
12–15
[3]
Address
Decode
Address
Decode
True Dual-Ported
A
A
–A
A
A
–A
–A
0L
11–14L
0R
11–14R
RAM Array
12–15
12–15
[3]
[3]
–A
0L
11–14L
0R
11–14R
CE
CE
Interrupt
Semaphore
Arbitration
L
R
OE
OE
L
R
R/W
SEM
R/W
SEM
L
R
R
L
[4]
L
[4]
BUSY
INT
BUSY
INT
R
R
L
M/S
Notes:
1. Call for availability
2. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
3. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K devices.
4. BUSY is an output in master mode and an input in slave mode.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 30, 1999
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
processor designs, communications status buffering, and
dual-port video/graphics memory.
Functional Description
The CY7C138V/144V/006V/007V and CY7C139V/145V/
016V/017V are low-power CMOS 4K, 8K, 16K, and 32K x8/9
dual-port static RAMs. Various arbitration schemes are includ-
ed on the devices to handle situations when multiple proces-
sors access the same piece of data. Two ports are provided,
permitting independent, asynchronous access for reads and
writes to any location in memory. The devices can be utilized
as standalone 8/9-bit dual-port static RAMs or multiple devices
can be combined in order to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi-
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a chip select (CE) pin.
.
Pin Configurations
PLCC
68-Pin
Top View
9
8
7
6
5 4 3 2 1 68 6766 65 64 63 62 61
I/O
I/O
I/O
2L
3L
4L
A
A
A
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
5L
4L
3L
I/O
5L
A
A
A
2L
GND
I/O
1L
6L
0L
I/O
7L
INT
L
V
CC
BUSY
L
CY7C138V (4K x 8)
CY7C139V (4K x 9)
GND
GND
M/S
I/O
I/O
0R
1R
2R
BUSY
R
I/O
INT
21
22
23
24
25
26
R
V
CC
A
0R
I/O
3R
4R
5R
A
A
47
46
45
44
1R
I/O
I/O
I/O
2R
A
3R
A
4R
6R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
Notes:
5. I/O8R on the CY7C139V.
6. I/O8L on the CY7C13V9.
2
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Pin Configurations (continued)
PLCC
68-Pin
Top View
9
8
7
6
5 4 3 2 1 68 6766 65 64 63 62 61
I/O
2L
3L
4L
A
A
A
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
5L
4L
3L
I/O
I/O
I/O
5L
A
A
A
2L
GND
I/O
1L
6L
0L
I/O
7L
INT
L
V
CC
BUSY
L
CY7C144V (8K x 8)
CY7C145V (8K x 9)
GND
GND
M/S
I/O
I/O
0R
1R
2R
BUSY
R
I/O
INT
21
22
23
24
25
26
R
V
CC
A
0R
I/O
3R
4R
5R
A
A
47
46
45
44
1R
I/O
I/O
I/O
2R
A
3R
A
4R
6R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
64-Pin TQFP
Top View
I/O
I/O
A
48
47
2L
1
2
4L
A
A
3L
3L
4L
I/O
I/O
2L
46
45
3
4
A
1L
A
0L
5L
GND
44
43
42
41
5
6
7
8
9
I/O
6L
INT
L
I/O
7L
BUSY
L
GND
M/S
V
CC
CY7C144V (8K x 8)
GND
40
39
BUSY
I/O
0R
10
R
I/O
1R
38
37
36
INT
R
11
12
13
I/O
2R
A
0R
A
1R
A
2R
A
3R
V
CC
I/O
3R
35
34
14
15
I/O
4R
I/O
5R
33
A
4R
16
Notes:
7. I/O8R on the CY7C145V.
8. I/O8L on the CY7C145V.
3
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Pin Configurations (continued)
80-Pin TQFP
Top View
NC
1
2
NC
60
59
I/O
I/O
I/O
I/O
2L
A
5L
A
4L
3
4
3L
4L
5L
58
57
A
A
3L
2L
5
6
7
8
56
55
54
53
A
1L
A
0L
GND
I/O
6L
I/O
7L
INT
L
BUSY
V
L
9
10
CC
52
51
GND
M/S
NC
CY7C145V (8K x 9)
GND
I/O
11
12
13
14
50
49
48
47
0R
BUSY
R
I/O
1R
INT
R
I/O
2R
CC
3R
4R
5R
6R
A
0R
A
1R
A
2R
A
3R
V
15
16
46
45
I/O
I/O
I/O
I/O
17
44
A
4R
18
19
20
43
42
41
NC
NC
NC
80-Pin TQFP
Top View
NC
1
2
NC
60
I/O
2L
A
A
5L
59
I/O
I/O
I/O
4L
3
4
3L
4L
5L
58
57
A
A
3L
2L
5
6
7
8
9
10
11
12
13
14
56
55
54
53
A
1L
A
0L
GND
I/O
6L
[1]
I/O
7L
INT
L
CY7C007V (32K x 8)
BUSY
V
L
CC
52
51
GND
M/S
CY7C016V (8K x 9)
CY7C017V (32K x 9)
NC
GND
50
49
48
47
I/O
0R
BUSY
R
I/O
1R
INT
R
I/O
2R
CC
3R
4R
5R
6R
A
0R
A
1R
A
2R
A
3R
V
15
16
46
45
I/O
I/O
I/O
I/O
17
44
A
4R
18
19
20
43
42
41
NC
NC
NC
Notes:
9. I/O for CY7C016V and CY7C017V only.
10. Address line for CY7C007V and CY7C01V7 only.
4
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Pin Configurations (continued)
68-Pin PLCC
Top View
60
59
A
A
10
11
12
13
I/O
I/O
I/O
5L
2L
3L
4L
4L
58
57
A
A
A
3L
I/O
5L
2L
56
55
GND
1L
14
15
A
0L
I/O
6L
54
53
52
INT
I/O
7L
L
16
17
CY7C006V (16K x 8)
CY7C007V (32K x 8)
CY7C016V (16K x 9)
CY7C017V (32K x 9)
BUSY
V
CC
L
GND
M/S
GND
18
19
20
21
I/O
0R
51
50
I/O
1R
BUSY
R
I/O
2R
INT
R
49
48
V
CC
A
0R
22
23
A
1R
I/O
3R
47
I/O
4R
24
25
26
A
A
46
45
2R
I/O
5R
3R
4R
I/O6
R
A
44
64-Pin TQFP
Top View
I/O
A
48
47
2L
1
2
4L
A
A
I/O
I/O
3L
3L
4L
2L
46
45
3
4
A
1L
A
0L
I/O
5L
GND
44
43
42
41
5
6
I/O
6L
INT
L
I/O
7L
BUSY
7
L
GND
M/S
V
CC
8
CY7C006V (16K x 8)
GND
40
39
9
BUSY
I/O
0R
10
11
12
R
I/O
1R
38
37
36
INT
R
I/O
2R
A
0R
A
1R
A
2R
A
3R
V
CC
13
I/O
3R
35
34
14
15
I/O
4R
I/O
5R
33
A
4R
16
5
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Selection Guide
CY7C138V/144V/006V/007V CY7C138V/144V/006V/007V CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V CY7C139V/145V/016V/017V CY7C139V/145V/016V/017V
[1]
-15
-20
-25
Maximum Access Time (ns)
15
20
25
Typical Operating Current (mA)
125
35
120
35
115
30
TypicalStandby CurrentforI
(mA) (Both Ports TTL level)
SB1
TypicalStandby CurrentforI
10 µA
10 µA
10 µA
SB3
(µA) (Both Ports CMOS level)
Shaded areas contain advance information.
Pin Definitions
Left Port
Right Port
Description
CE
CE
Chip Enable
L
R
R/W
R/W
Read/Write Enable
Output Enable
L
R
OE
OE
R
L
A
–A
A
–A
Address (A –A for 4K devices; A –A for 8K devices; A –A for 16K devices; A –A for 32K)
0 11 0 12 0 13 0 14
0L
14L
0R
14R
I/O –I/O
I/O –I/O
Data Bus Input/Output (I/O –I/O for x8 devices and I/O –I/O for x9)
0 7 0 8
0L
8L
0R
8R
SEM
SEM
Semaphore Enable
Interrupt Flag
Busy Flag
L
R
INT
INT
R
L
BUSY
M/S
BUSY
R
L
Master or Slave Select
Power
V
CC
GND
NC
Ground
No Connect
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
Latch-Up Current.................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Ambient
Power Applied.............................................–55°C to +125°C
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
3.3V ± 300 mV
3.3V ± 300 mV
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to V +0.5V
CC
[11]
Shaded areas contain advance information.
DC Input Voltage .................................–0.5V to V +0.5V
CC
Note:
11. Pulse width < 20 ns.
6
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Electrical Characteristics Over the Operating Range
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
[1]
-15
-20
-25
Parameter
Description
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
V
V
V
V
Output HIGH Voltage (V = 3.3V)
2.4
2.0
2.4
2.0
–10
2.4
2.0
V
OH
OL
IH
CC
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
0.4
0.4
0.4
V
V
0.8
10
0.8
10
0.8
10
V
IL
I
I
Output Leakage Current
–10
–10
µA
mA
mA
mA
mA
mA
mA
µA
µA
OZ
Operating Current (V = Max.,
Com’l.
Indust.
Com’l.
Indust.
Com’l.
Indust.
125 185
120 175
140 195
115 165
135 185
CC
CC
I
= 0 mA) Outputs Disabled
OUT
I
I
I
Standby Current (Both Ports TTL
Level) CE & CE ≥ V , f = f
35
80
10
50
35
45
75
85
10
10
45
55
30
40
65
75
10
10
40
50
SB1
SB2
SB3
L
R
IH
MAX
Standby Current (One Port TTL
Level) CE | CE ≥ V , f = f
MAX
120
500
110
130
500
500
95
L
R
IH
105
500
500
StandbyCurrent(Both Ports CMOS Com’l.
Level) CE & CE ≥ V – 0.2V,
L
R
CC
Indust.
f = 0
I
Standby Current (One Port CMOS Com’l.
75
105
70
80
95
60
70
80
90
mA
mA
SB4
[12]
Level) CE | CE ≥ V , f = f
L
R
IH
MAX
Indust.
105
Shaded areas contain advance information.
Capacitance[13]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
C
Input Capacitance
Output Capacitance
10
10
pF
pF
IN
A
V
= 3.3V
CC
OUT
AC Test Loads and Waveforms
3.3V
3.3V
R
TH
= 250
Ω
R1 = 590
Ω
Ω
OUTPUT
C = 30pF
OUTPUT
C = 30 pF
R1 = 590
Ω
OUTPUT
R2 = 435
C = 5 pF
R2 = 435
Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c)Three-State Delay(Load 2)
(b) ThéveninEquivalent (Load 1)
(Used for t , t , t
& t
LZ HZ HZWE
LZWE
including scope and jig)
ALL INPUTPULSES
3.0V
GND
90%
90%
10%
10%
3 ns
3 ns
≤
≤
Notes:
12. MAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3
f
.
13. Tested initially and after any design or process changes that may affect these parameters.
7
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
[14]
Switching Characteristics Over the Operating Range
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
[1]
–15
Min.
-20
-25
Parameter
READ CYCLE
tRC
Description
Max.
Min.
20
3
Max.
Min.
25
Max.
Unit
Read Cycle Time
15
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
15
20
25
AA
3
OHA
[15]
15
10
20
12
25
13
ACE
DOE
LZOE
[16, 17, 18]
[16, 17, 18]
3
3
0
3
3
0
3
3
0
OE HIGH to High Z
10
10
12
12
15
15
HZOE
[16, 17, 18]
CE LOW to Low Z
LZCE
[16, 17, 18]
CE HIGH to High Z
HZCE
[18]
[18]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
PU
15
15
20
20
25
25
PD
[15]
ABE
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
15
12
12
0
20
16
16
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
SCE
AW
HA
[15]
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
[15]
0
0
0
SA
12
10
0
16
12
0
20
15
0
PWE
SD
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
HD
[17, 18]
10
12
15
HZWE
[17, 18]
R/W HIGH to Low Z
3
3
3
LZWE
[19]
WDD
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
30
25
40
30
50
35
[19]
DDD
[20]
BUSY TIMING
t
t
t
t
t
t
t
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
15
15
15
15
20
20
20
16
20
20
20
17
ns
ns
ns
ns
ns
ns
ns
BLA
BHA
BLC
BHC
PS
BUSY HIGH from CE HIGH
Port Set-Up for Priority
5
0
5
0
5
0
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
WB
13
15
17
WH
Note:
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OI/IOH and 30-pF load capacitance.
I
15. To access RAM, CE=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
16. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE
.
17. Test conditions used are Load 3.
18. This parameter is guaranteed but not tested.For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing
with Busy waveform.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
20. Test conditions used are Load 2.
8
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
[14]
Switching Characteristics Over the Operating Range (continued)
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
[1]
–15
Min.
-20
-25
Parameter
Description
Max.
Min.
Max.
Min.
Max.
Unit
[21]
t
BUSY HIGH to Data Valid
15
20
25
ns
BDD
[20]
INTERRUPT TIMING
t
t
INT Set Time
15
15
20
20
20
20
ns
ns
INS
INR
INT Reset Time
SEMAPHORE TIMING
t
t
t
t
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
10
5
12
5
ns
ns
ns
ns
SOP
SWRD
SPS
5
5
5
15
20
25
SAA
Data Retention Mode
Timing
The CY7C0138V/144V/006V/007V and CY7C139V/145V/
016V/017V are designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over tem-
perature. The following rules ensure data retention:
Data Retention Mode
3.0V
V
CC
3.0V
V
CC
2.0V
>
t
RC
1. Chip enable (CE) must be held HIGH during data retention, with-
in V to V – 0.2V.
CC
CC
V
CC
to V – 0.2V
CC
V
IH
CE
2. CE must be kept between V – 0.2V and 70% of V
CC
CC
during the power-up and power-down transitions.
3. The RAM can begin operation >t after V reaches the
minimum operating voltage (3.0 volts).
RC
CC
[22]
Parameter
ICC
Test Conditions
@ VCC = 2V
Max.
Unit
µA
50
DR1
DR
Notes:
21.
t
BDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
22. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
9
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Switching Waveforms
[23, 24, 25]
Read Cycle No. 1 (Either Port Address Access)
t
RC
ADDRESS
t
AA
t
t
OHA
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
[23, 26, 27]
Read Cycle No .2 (Either Port CE/OE Access)
t
ACE
CE
OE
t
HZCE
t
DOE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
I
CC
CURRENT
I
SB
[23, 25, 26, 27]
Read Cycle No. 3 (Either Port)
t
RC
ADDRESS
t
AA
t
OHA
t
LZCE
t
ABE
CE
t
HZCE
t
ACE
t
LZCE
DATA OUT
Notes:
23. R/W is HIGH for read cycles.
24. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.
25. OE = VIL
.
26. Address valid prior to or coincident with CE transition LOW.
27. To access RAM, CE= VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = V .
IL
10
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Switching Waveforms (continued)
[28, 29, 30, 31]
Write Cycle No. 1: R/W Controlled Timing
t
WC
ADDRESS
OE
[33]
t
HZOE
t
AW
[32]
CE
[31]
PWE
t
SA
t
t
HA
R/W
DATA OUT
DATA IN
[33]
t
HZWE
t
LZWE
NOTE 34
NOTE 34
t
t
HD
SD
[28, 29, 30, 35]
Write Cycle No. 2: CE Controlled Timing
t
WC
ADDRESS
t
AW
[32]
CE
t
SA
t
t
HA
SCE
R/W
t
t
HD
SD
DATA IN
Notes:
28. R/W must be HIGH during all address transitions.
29. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
30. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
31. If OEis LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE
32. To access RAM, CE= VIL, SEM = VIH
.
.
33. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. During this period, the I/O pins are in the output state, and input signals must not be applied.
35. If the CEor SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
11
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Switching Waveforms (continued)
[36]
Semaphore Read After Write Timing, Either Side
t
t
OHA
SAA
A
–A
2
VALID ADRESS
VALID ADRESS
0
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
SA
t
PWE
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
[37, 38, 39]
READ CYCLE
Timing Diagram of Semaphore Contention
A
0L
–A
2L
MATCH
R/W
L
SEM
L
t
SPS
A
–A
MATCH
0R
2R
R/W
R
SEM
R
Notes:
36. CE = HIGH for the duration of the above timing (both write and read cycle).
37. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
38. Semaphores are reset (available to both ports) at cycle start.
39. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
12
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Switching Waveforms (continued)
[40]
Timing Diagram of Read with BUSY (M/S=HIGH)
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATA IN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note:
40. CEL = CER = LOW.
13
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Switching Waveforms (continued)
[41]
Busy Timing Diagram No.1 (CE Arbitration)
CE Valid First:
L
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CE Valid First:
R
ADDRESS
L,R
ADDRESS MATCH
CE
R
t
PS
CE
L
L
t
t
BHC
BLC
BUSY
[41]
Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
Right Address Valid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Note:
41. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
14
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INT :
R
t
WC
ADDRESS
WRITE FFF (See Functional Description)
[42]
L
t
HA
CE
L
R/W
INT
L
R
[43]
t
INS
Right Side Clears INT :
t
R
RC
READ FFF
(See Functional Description)
ADDRESS
R
CE
R
[43]
t
INR
R/W
R
OE
R
INT
R
:
Right SideSets INT
L
t
WC
ADDRESS
R
WRITE FFE (See Functional Description)
[42]
t
HA
CE
R
R
R/W
INT
L
[43]
INS
t
Left Side Clears INT :
L
t
RC
READ FFE
(See Functional Description)
ADDRESS
R
L
CE
[43]
INR
t
R/W
L
OE
INT
L
L
Notes:
42.
tHA depends on which enable pin (CEL or R/WL) is deasserted first.
43. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
15
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
access (contention). If both ports’ CEs are asserted and an address
Architecture
match occurs within t of each other, the busy logic will determine
PS
The CY7C138V/144V/006V/007V and CY7C139V/145V/
016V/017V consist of an array of 4K, 8K, 16K, and 32K words of 8
and 9 bits each of dual-port RAM cells, I/O and address lines, and
control signals (CE, OE, R/W). These control pins permit indepen-
dent access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is pro-
vided on each port. Two Interrupt (INT) pins can be utilized for port-
to-port communication. Two Semaphore (SEM) control pins are used
for allocating shared resources. With the M/S pin, the devices can
function as a master (BUSY pins are outputs) or as a slave (BUSY
pins are inputs). The devices also have an automatic power-down
feature controlled by CE. Each port is provided with its own output
enable control (OE), which allows data to be read from the device.
which port has access. If t is violated, one port will definitely gain
permission to the location, but it is not predictable which port will get
PS
that permission. BUSY will be asserted t
after an address match
BLA
or t
after CE is taken LOW.
BLC
Master/Slave
An M/S pin is provided in order to expand the word width by config-
uring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will allow
the device to interface to a master device with no external compo-
nents. Writing to slave devices must be delayed until after the BUSY
input has settled (t
or t ), otherwise, the slave chip may begin
BLC
BLA
a write cycle during a contention situation. When tied HIGH, the M/S
pinallowsthedevicetobe usedasamaster and, therefore, theBUSY
line is an output. BUSY can then be used to send the arbitration out-
come to a slave.
Functional Description
Write Operation
Semaphore Operation
Data must be set up for a duration of t before the rising edge
SD
of R/W in order to guarantee a valid write. A write operation is con-
trolled by either the R/W pin (see Write Cycle No. 1 waveform) or the
CE pin (see Write Cycle No. 2 waveform). Required inputs for non-
contention operations are summarized in Table 1.
The CY7C138V/144V/006V/007V and CY7C139V/145V/
016V/017V provide eight semaphore latches, which are sepa-
rate from the dual-port memory locations. Semaphores are
used to reserve resources that are shared between the two
ports. The state of the semaphore indicates that a resource is
in use. For example, if the left port wants to request a given
resource, it sets a latch by writing a zero to a semaphore loca-
tion. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output; other-
wise the data read is not deterministic. Data will be valid on the
port t
after the data is presented on the other port.
DDD
be deasserted for t
before attempting to read the semaphore.
SOP
Read Operation
The semaphore value will be available t
+ t
after the rising
SWRD
DOE
edge of the semaphore write. If the left port was successful (reads a
zero), it assumes control of the shared resource, otherwise (reads a
one) it assumes the right port has control and continues to poll the
semaphore. When the right side has relinquished control of the
semaphore (by writing a one), the left side will succeed in gaining
control of the semaphore. If the left side no longer requires the sema-
phore, a one is written to cancel its request.
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must also
be asserted.
after CE or t
after OE is
ACE
DOE
Interrupts
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE must
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C138V/9V, 1FFF for the CY7C144V/5V, 3FFF for the
CY7C006V/16V, 7FFF for the CY7C007V/17V) is the mailbox
for the right port and the second-highest memory location
(FFE for the CY7C138V/9V, 1FFE for the CY7C144V/5V, 3FFE
for the CY7C006V/16V, 7FFE for the CY7C007V/17V) is the
mailbox for the left port. When one port writes to the other
port’s mailbox, an interrupt is generated to the owner. The in-
terrupt is reset when the owner reads the contents of the mail-
box. The message is user-defined.
remain HIGH during SEM LOW). A
represents the semaphore
0–2
address. OE and R/W are used in the same manner as a normal
memory access. When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only I/O is used. If a zero is
0
written to the left port of an available semaphore, a one will appear at
the same semaphore address on the right port. That semaphore can
now only be modified by the side showing zero (the left port in this
case). If the left port now relinquishes control by writing a one to the
semaphore, thesemaphore will be set to onefor both sides. However,
if the right port had requested the semaphore (written a zero) while
the left port had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows sample
semaphore operations.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it. If an
application does not require message passing, do not connect
the interrupt pin to the processor’s interrupt request input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
When reading a semaphore, all data lines output the sema-
phore value. The read value is latched in an output register to
prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the sema-
phore within t
of each other, the semaphore will definitely be
SPS
Busy
obtained byone side or theother, but thereisnoguarantee whichside
will control the semaphore.
The CY7C138V/144V/006V/007V and CY7139V/145V/016V/017V
provide on-chip arbitration to resolve simultaneous memory location
16
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
H
R/W
X
OE
X
SEM
I/O –I/O
Operation
0
8
H
L
High Z
Deselected: Power-Down
H
H
L
Data Out
High Z
Read Data in Semaphore Flag
I/O Lines Disabled
X
X
H
X
L
H
X
Data In
Write into Semaphore Flag
L
L
L
H
L
L
X
X
H
H
L
Data Out
Data In
Read
Write
X
Not Allowed
Table 2. Interrupt Operation Example (assumes BUSY =BUSY =HIGH)
L
R
Left Port
Right Port
OE
Function
Set Right INT Flag
R/W
CE
L
OE
X
A
INT
X
R/W
X
CE
X
A
INT
L
L
L
0L–14L
L
R
R
R
0R–14R
R
[46]
[45]
L
X
X
X
FFF
X
L
X
L
R
[46]
[44]
Reset Right INT Flag
X
X
X
X
X
X
L
FFF
H
R
[44]
[46]
Set Left INT Flag
X
X
L
L
L
X
X
1FFE
X
X
X
L
[46]
[45]
Reset Left INT Flag
L
L
1FFE
H
X
X
L
Table 3. Semaphore Operation Example
Function I/O –I/O Left I/O –I/O Right
Status
0
8
0
8
No action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port has semaphore token
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left port writes 1 to semaphore
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Note:
44. If BUSYR = L, then no change.
45. If BUSYL = L, then no change.
46. See Functional Description for specific addresses by device part number.
17
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Ordering Information
Package Availability Guide
Device
Organization
4K x 8
68-Pin PLCC
64-Pin TQFP
CY7C138V
CY7C139V
CY7C144V
CY7C145V
CY7C006V
CY7C016V
CY7C007V
CY7C017V
X
X
X
X
X
X
X
X
4K x 9
8K x 8
X
X
8K x 9
16K x 8
16K x 9
32K x 8
32K x 9
4K x8 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
(ns)
Ordering Code
Package Type
Range
Commercial
Commercial
Industrial
[1]
15
CY7C138V-15JC
J81
J81
J81
J81
J81
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
20
CY7C138V–20JC
CY7C138V–20JI
CY7C138V–25JC
CY7C138V–25JI
25
Commercial
Industrial
Shaded areas contain advance information.
4K x9 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
[1]
15
CY7C139V-15JC
J81
J81
J81
J81
J81
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
Commercial
Commercial
Industrial
20
25
CY7C139V–20JC
CY7C139V–20JI
CY7C139V–25JC
CY7C139V–25JI
Commercial
Industrial
Shaded areas contain advance information.
8K x8 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
64-Pin Thin Quad Flat Pack
[1]
15
CY7C144V-15AC
A65
J81
A65
J81
A65
J81
A65
J81
A65
J81
Commercial
Commercial
Industrial
CY7C144V-15JC
CY7C144V–20AC
CY7C144V–20JC
CY7C144V–20AI
CY7C144V–20JI
CY7C144V–25AC
CY7C144V–25JC
CY7C144V–25AI
CY7C144V–25JI
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
20
25
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
Commercial
Industrial
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
68-Pin Plastic Leaded Chip Carrier
Shaded areas contain advance information.
18
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Ordering Information (continued)
8K x9 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
(ns)
Ordering Code
CY7C145V-15JC
Package Type
Range
Commercial
Commercial
Industrial
[1]
15
J81
J81
J81
J81
J81
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
20
CY7C145V–20JC
CY7C145V–20JI
CY7C145V–25JC
CY7C145V–25JI
25
Commercial
Industrial
Shaded areas contain advance information.
16K x8 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
64-Pin Thin Quad Flat Pack
[1]
15
CY7C006V-15AC
A65
J81
A65
J81
A65
J81
A65
J81
A65
J81
Commercial
Commercial
Commercial
CY7C006V-15JC
CY7C006V–20AC
CY7C006V–20JC
CY7C006V–20AI
CY7C006V–20JI
CY7C006V–25AC
CY7C006V–25JC
CY7C006V–25AI
CY7C006V–25JI
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
20
25
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
Industrial
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
Commercial
Industrial
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
68-Pin Plastic Leaded Chip Carrier
Shaded areas contain advance information.
16K x9 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
[1]
15
CY7C016V-15JC
J81
J81
J81
J81
J81
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
Commercial
Commercial
Industrial
20
CY7C016V–20JC
CY7C016V–20JI
CY7C016V–25JC
CY7C016V–25JI
25
Commercial
Industrial
Shaded areas contain advance information.
32K x8 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
[1]
15
CY7C007V-15JC
J81
J81
J81
J81
J81
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
Commercial
Commercial
Industrial
20
CY7C007V–20JC
CY7C007V–20JI
CY7C007V–25JC
CY7C007V–25JI
25
Commercial
Industrial
Shaded areas contain advance information.
19
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Ordering Information (continued)
32K x9 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
(ns)
Ordering Code
CY7C017V-15JC
Package Type
Range
Commercial
Commercial
Industrial
[1]
15
J81
J81
J81
J81
J81
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
20
CY7C017V–20JC
CY7C017V–20JI
CY7C017V–25JC
CY7C017V–25JI
25
Commercial
Industrial
Shaded areas contain advance information.
Document #: 38–00677–B
Package Diagrams
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046-B
20
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
Package Diagrams (continued)
68-Lead Plastic Leaded Chip Carrier J81
51-85005-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C138V/144V/006V/007V
CY7C139V/145V/016V/017V
PRELIMINARY
ramp rate (greater than 100 ns) in order to confirm that the
problem might be due to the POR circuit. If the dual-port func-
tions properly once the ramp rate is slowed to 100 ns or great-
er, then the POR circuit is at fault.
CY7C036 Dual Port Design Consideration –
Data Sheet Addendum
This design consideration applies to the Internal Power-On-
Reset (POR) circuit used on the CY7C036 and its derivatives
listed below.
Applicable devices—All speed/package/temperature combi-
nations of the following:
Power supply ramp—The devices will function properly and
meet all data sheet specifications if the power supply ramp rate
is greater than 100 ns. If ramp is less than 100 ns, you may
see a non-destructive failure in which the device will not re-
spond to changes in address or clock, but the I/Os will respond
to the output enable.
• CY7C138V
• CY7C139V
• CY7C144V
• CY7C145V
• CY7C006V
• CY7C016V
• CY7C007V
• CY7C017V
Applications consideration—If the power supply ramps in less
than 100 ns, a small resistor (20–50Ω), a large capacitor, or an
RC network can be connected at the output of the power sup-
ply to ground. The addition of a resistor will help clean up the
power lines, while the capacitor will slow down the ramp rate
without the loss of any power. Contact your local Cypress FAE
for assistance as needed.
Cypress design change—Cypress design team has identified
the root cause. A permanent circuit change and die revision
will be available beginning in October and will be identified by
the letter “A” in the part number.
Troubleshooting—If a problem occurs with the part, power
down the device to ground and then power up again at slower
22
CY7C138V-20JI 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CY7C138V-25JCT | CYPRESS | Dual-Port SRAM, 4KX8, 25ns, CMOS, PQCC68, PLASTIC, LCC-68 | 获取价格 |
|
| CY7C138_05 | CYPRESS | 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy | 获取价格 |
|
| CY7C138_09 | CYPRESS | 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy | 获取价格 |
|
| CY7C139 | CYPRESS | 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy | 获取价格 |
|
| CY7C139*BV18 | CYPRESS | RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata | 获取价格 |
|
| CY7C139-15 | CYPRESS | 4K x 8/9 Dual-Port Static RAM | 获取价格 |
|
| CY7C139-15JC | CYPRESS | 4K x 8/9 Dual-Port Static RAM | 获取价格 |
|
| CY7C139-15JCR | CYPRESS | Dual-Port SRAM, 4KX9, 15ns, CMOS, PQCC68, PLASTIC, LCC-68 | 获取价格 |
|
| CY7C139-15JCT | CYPRESS | 暂无描述 | 获取价格 |
|
| CY7C139-25 | CYPRESS | 4K x 8/9 Dual-Port Static RAM | 获取价格 |
|
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