CY7C1399BN-12VC [CYPRESS]
256K (32K x 8) Static RAM; 256K （ 32K ×8 ）静态RAM
| 型号： | CY7C1399BN-12VC |
| 厂家： | 
CYPRESS |
| 描述： | 256K (32K x 8) Static RAM |
| 文件： | 总8页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1399BN
256K (32K x 8) Static RAM
expansion is provided by an active LOW Chip Enable (CE) and
active LOW Output Enable (OE) and tri-state drivers. The
device has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
Features
• Temperature Ranges
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed: 12 ns
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins is present on the eight data input/output pins.
• Low active power
— 180 mW (max.)
• Low-power alpha immune 6T cell
• Available in Pb-free and non Pb-free Plastic SOJ and
TSOP I packages
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399BN is available in 28-pin
standard 300-mil-wide SOJ and TSOP Type I packages.
Functional Description[1]
The CY7C1399BN is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory
Logic Block Diagram
Pin Configurations
SOJ
Top View
A
A
6
V
CC
28
27
26
1
2
3
4
5
6
5
WE
A
7
A
4
A
3
A
8
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
25
24
INPUT BUFFER
A
9
A
2
A
10
23
22
A
0
A
1
A
1
A
11
7
8
9
10
11
12
13
OE
A
0
A
2
A
12
21
20
19
18
17
A
3
A
4
A
13
CE
I/O
32K x 8
ARRAY
A
5
A
A
14
6
A
7
7
A
I/O
I/O
6
0
8
A
9
I/O
I/O
5
1
16
15
I/O
GND
I/O
2
4
CE
WE
I/O
14
3
POWER
DOWN
COLUMN
DECODER
I/O
7
OE
Selection Guide
-12
12
-15
-20
Maximum Access Time (ns)
15
50
20
45
Maximum Operating Current (mA)
Maximum CMOS Standby Current (µA)
55
Commercial
500
50
500
50
500
50
Commercial (L)
Industrial
500
500
500
Automotive-A
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06490 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 31, 2006
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CY7C1399BN
Pin Configuration
TSOP
Top View
21
20
OE
1
22
23
A
CE
I/O
I/O
I/O
I/O
I/O
0
A
A
19
18
17
16
24
2
7
A
25
26
27
28
1
3
6
5
4
3
A
4
WE
15
14
13
V
CC
5
6
A
GND
I/O
A
2
3
2
A7
12
11
I/O
I/O
A
1
0
A
4
5
8
10
9
A
14
9
10
11
A
A
A
13
6
7
8
A
12
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V
Range
Commercial
Industrial
Temperature
VCC
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
3.3V ±300 mV
DC Voltage Applied to Outputs
in High Z State[2] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[2].................................–0.5V to VCC + 0.5V
Automotive-A
Electrical Characteristics Over the Operating Range[1]
-12
-15
-20
Parameter
VOH
Description
Test Conditions
Min. Max. Min. Max. Min. Max. Unit
Output HIGH Voltage VCC = Min., IOH = –2.0 mA
Output LOW Voltage VCC = Min., IOL = 4.0 mA
Input HIGH Voltage
2.4
2.4
2.4
V
V
V
VOL
0.4
2.2 VCC
0.3V
0.8 –0.3 0.8
0.4
2.2 VCC
0.3V
0.4
VIH
+
+
2.2 VCC +
0.3V
0.8
+1
VIL
IIX
Input LOW Voltage[2]
Input Leakage Current
–0.3
–1
–0.3
–1
V
+1
+5
–1
–5
+1
+5
µA
µA
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC
,
–5
–5
+5
Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
55
50
45
5
mA
ISB1
Automatic CE
Power-Down
Current—
Max. VCC, CE ≥ VIH,
VIN ≥ VIH, or VIN ≤ VIL,
f = fMAX
Comm’l
Comm’l (L)
Ind’l
5
4
5
5
4
mA
mA
TTL Inputs
5
Auto-A
5
ISB2
Automatic CE
Power-Down
Current— CMOS
Inputs[3]
Max. VCC, CE ≥ VCC – 0.3V, Comm’l
VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V,
500
50
500
50
500
500
500 µA
Comm’l (L)
µA
µA
µA
WE ≥VCC – 0.3V or WE ≤ 0.3V,
f = fMAX
Ind’l
500
Auto-A
Notes:
2. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns.
3. Device draws low standby current regardless of switching on the addresses.
Document #: 001-06490 Rev. *A
Page 2 of 8
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CY7C1399BN
Capacitance[4]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN: Addresses
CIN: Controls
COUT
Input Capacitance
TA = 25°C, f = 1 MHz,
CC = 3.3V
5
6
6
V
pF
Output Capacitance
pF
AC Test Loads and Waveforms[5]
R1 317Ω
ALL INPUT PULSES
90%
3.3V
Equivalent to: THÉVENINEQUIVALENT
3.0V
90%
10%
OUTPUT
167Ω
10%
OUTPUT
1.73V
GND
R2
351Ω
C
L
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
Switching Characteristics Over the Operating Range[5]
-12
-15
-20
Parameter
Read Cycle
tRC
Description
Min.
12
3
Max.
Min.
15
3
Max.
Min.
Max.
Unit
Read Cycle Time
20
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
12
15
20
tOHA
tACE
12
5
15
6
20
7
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
0
3
0
5
6
6
7
6
7
tPD
12
15
20
Write Cycle[8, 9]
tWC
tSCE
tAW
Write Cycle Time
12
8
15
10
10
0
20
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
tHA
0
tSA
0
0
0
tPWE
tSD
8
10
8
12
10
0
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[8]
7
tHD
0
0
tHZWE
7
7
7
tLZWE
WE HIGH to Low Z[6]
3
3
3
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
/I and capacitance C = 30 pF.
I
OL OH
L
6. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
7. t
, t
, t
are specified with C = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
HZOE HZCE HZWE L
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 001-06490 Rev. *A
Page 3 of 8
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CY7C1399BN
Data Retention Characteristics (Over the Operating Range - L version only)
Parameter
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
2.0
0
Max.
Unit
V
VDR
ICCDR
tCDR
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
IN > VCC – 0.3V or
IN < 0.3V
20
µA
ns
Chip Deselect to Data
Retention Time
0
V
V
tR
Operation Recovery Time
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2[11, 12]
t
RC
CE
OE
t
ACE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
ICC
ISB
CC
SUPPLY
CURRENT
50%
50%
Notes:
10. Device is continuously selected. OE, CE = V
11. WE is HIGH for read cycle.
.
IL
12. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06490 Rev. *A
Page 4 of 8
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CY7C1399BN
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[8, 13, 14]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
NOTE 15
DATA VALID
DATA I/O
IN
t
HZOE
Write Cycle No. 2 (CE Controlled)[8, 13, 14]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Write Cycle No. 3 (WE Controlled, OE LOW)[9, 14]
t
WC
ADDRESS
CE
t
t
AW
HA
t
SA
WE
t
t
HD
SD
DATA VALID
DATA I/O
NOTE 15
IN
t
t
LZWE
HZWE
Notes:
13. Data I/O is high impedance if OE = V
.
IH
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
15. During this period, the I/Os are in the output state and input signals should not be applied.
Document #: 001-06490 Rev. *A
Page 5 of 8
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CY7C1399BN
Truth Table
CE
H
L
WE
X
OE
X
Input/Output
High Z
Mode
Deselect/Power-Down
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
H
L
Data Out
Data In
High Z
Read
)
L
L
X
Write
)
L
H
H
Deselect, Output Disabled
)
Ordering Information
Speed
Package
Diagram
Operating
(ns)
Ordering Code
CY7C1399BN-12VC
CY7C1399BN-12VXC
CY7C1399BN-12ZC
CY7C1399BN-12ZXC
CY7C1399BNL-12ZC
CY7C1399BNL-12ZXC
CY7C1399BN-12VXI
CY7C1399BN-15VC
CY7C1399BN-15VXC
CY7C1399BN-15ZC
CY7C1399BN-15ZXC
CY7C1399BNL-15ZXC
CY7C1399BNL-15VXC
CY7C1399BN-15VI
CY7C1399BN-15VXI
CY7C1399BN-15ZI
Package Type
Range
12
51-85031 28-Lead Molded SOJ
28-Lead Molded SOJ (Pb-free)
51-85071 28-Lead TSOP I
28-Lead TSOP I (Pb-free)
Commercial
28-Lead TSOP I
28-Lead TSOP I (Pb-free)
51-85031 28-Lead Molded SOJ (Pb-free)
28-Lead Molded SOJ
Industrial
15
Commercial
28-Lead Molded SOJ (Pb-free)
51-85071 28-Lead TSOP I
28-Lead TSOP I (Pb-free)
28-Lead TSOP I (Pb-free)
51-85031 28-Lead Molded SOJ (Pb-free)
28-Lead Molded SOJ
Industrial
28-Lead Molded SOJ (Pb-free)
51-85071 28-Lead TSOP I
28-Lead TSOP I (Pb-free)
CY7C1399BN-15ZXI
CY7C1399BN-15VXA
CY7C1399BN-20ZXC
51-85031 28-Lead Molded SOJ (Pb-free)
51-85071 28-Lead TSOP I (Pb-free)
Automotive-A
Commercial
20
Please contact local sales representative regarding availability of these parts.
Document #: 001-06490 Rev. *A
Page 6 of 8
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CY7C1399BN
Package Diagrams
NOTE :
28-Lead (300-Mil) Molded SOJ (51-85031)
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
MIN.
3. DIMENSIONS IN INCHES
MAX.
DETAIL
A
PIN 1 ID
EXTERNAL LEAD DESIGN
14
1
0.291
0.300
0.330
0.350
0.026
0.032
0.013
0.019
15
28
0.014
0.020
OPTION 1
OPTION 2
0.697
0.713
SEATING PLANE
0.120
0.140
0.007
0.013
0.004
A
0.262
0.272
0.050
TYP.
51-85031-*C
0.025 MIN.
28-Lead TSOP 1 (8x13.4 mm) (51-85071)
51-85071-*G
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06490 Rev. *A
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1399BN
Document History Page
Document Title: CY7C1399BN 256K (32K x 8) Static RAM
Document Number: 001-06490
ISSUE
DATE
ORIG. OF
CHANGE
REV.
**
ECN NO.
423877
498575
DESCRIPTION OF CHANGE
See ECN
See ECN
NXR
NXR
New Data Sheet
Added Automotive-A range
*A
Removed IOS parameter from DC Electrical Characteristics table
Updated Ordering Information table.
Document #: 001-06490 Rev. *A
Page 8 of 8
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