CY7C1440AV25-250BZXIT [CYPRESS]
SRAM;
| 型号： | CY7C1440AV25-250BZXIT |
| 厂家： | 
CYPRESS |
| 描述： | SRAM 静态存储器 |
| 文件： | 总33页 (文件大小：611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1440AV25
CY7C1446AV25
36-Mbit (1 M × 36/512 K × 72)
Pipelined Sync SRAM
36-Mbit (1
M × 36/512 K × 72) Pipelined Sync SRAM
Features
Functional Description
■ Supports bus operation up to 250 MHz
■ Available speed grades are 250 and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ 2.5 V core power supply
The
CY7C1440AV25/CY7C1446AV25 SRAM
integrates
1 M × 36/512 K × 72 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and
ADV), Write Enables (BWX, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
■ 2.5 V power supply
■ Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
■ Provide high-performance 3-1-1-1 access rate
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
■ Asynchronous output enable
■ Single-cycle Chip Deselect
controlled by the byte write control inputs. GW when active
causes all bytes to be written.
LOW
■ CY7C1440AV25 available in Pb-free and non-Pb-free 165-ball
FBGA package. CY7C1446AV25 available in non-Pb-free
209-ball FBGA package
The CY7C1440AV25/CY7C1446AV25 operates from a +2.5 V
core power supply while all outputs may operate with a +2.5 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ “ZZ” Sleep Mode Option
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum Access Time
250 MHz
2.6
167 MHz Unit
3.4
335
120
ns
Maximum Operating Current
435
mA
mA
Maximum CMOS Standby Current
120
Cypress Semiconductor Corporation
Document Number: 001-70167 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 5, 2016
CY7C1440AV25
CY7C1446AV25
Logic Block Diagram – CY7C1440AV25
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND
CLR
Q0
LOGIC
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D ,DQPD
DQ
BYTE
WRITE DRIVER
D ,DQPD
BW
D
DQC ,DQP
BYTE
WRITE DRIVER
C
DQC ,DQP
BYTE
WRITE REGISTER
C
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
MEMORY
ARRAY
DQ s
SENSE
AMPS
DQPA
DQB ,DQP
BYTE
WRITE DRIVER
B
E
DQB ,DQP
BYTE
WRITE REGISTER
B
DQP
DQP
B
C
BW
BW
B
A
DQPD
DQ
BYTE
WRITE DRIVER
A ,DQPA
DQ
A ,DQPA
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Document Number: 001-70167 Rev. *E
Page 2 of 33
CY7C1440AV25
CY7C1446AV25
Logic Block Diagram – CY7C1446AV25
ADDRESS
REGISTER
A0, A1,A
A[1:0]
MODE
Q1
ADV
CLK
BINARY
COUNTER
CLR
Q0
ADSC
ADSP
DQH, DQPH
WRITE DRIVER
DQH, DQPH
WRITE DRIVER
BWH
BWG
DQG, DQPG
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
DQF, DQPF
DQF, DQPF
BWF
BWE
BWD
BWC
WRITE DRIVER
WRITE DRIVER
DQE, DQPE
WRITE DRIVER
DQE, DQPE
WRITE DRIVER
MEMORY
ARRAY
DQD, DQPD
WRITE DRIVER
DQD, DQPD
WRITE DRIVER
DQC, DQPC
WRITE DRIVER
DQC, DQPC
WRITE DRIVER
OUTPUT
BUFFERS
OUTPUT
REGISTERS
SENSE
AMPS
DQs
DQPA
DQPB
DQPC
DQPD
DQPE
DQPF
DQPG
DQPH
E
DQB, DQPB
WRITE DRIVER
DQB, DQPB
WRITE DRIVER
BWB
DQA, DQPA
WRITE DRIVER
DQA, DQPA
WRITE DRIVER
BWA
BWE
INPUT
GW
CE1
CE2
CE3
OE
REGISTERS
ENABLE
REGISTER
PIPELINED
ENABLE
SLEEP
CONTROL
ZZ
Document Number: 001-70167 Rev. *E
Page 3 of 33
CY7C1440AV25
CY7C1446AV25
Contents
Pin Configurations ...........................................................5
Pin Definitions ..................................................................7
Functional Overview ........................................................8
Single Read Accesses ................................................8
Single Write Accesses Initiated by ADSP ...................8
Single Write Accesses Initiated by ADSC ...................9
Burst Sequences .........................................................9
Sleep Mode .................................................................9
Interleaved Burst Address Table .................................9
Linear Burst Address Table .........................................9
ZZ Mode Electrical Characteristics ..............................9
Truth Table ......................................................................10
Truth Table for Read/Write ............................................11
Truth Table for Read/Write ............................................11
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................12
Disabling the JTAG Feature ......................................12
Test Access Port (TAP) .............................................12
PERFORMING A TAP RESET ..................................12
TAP REGISTERS ......................................................12
TAP Instruction Set ...................................................12
TAP Controller State Diagram .......................................14
TAP Controller Block Diagram ......................................15
TAP Timing ......................................................................15
TAP AC Switching Characteristics ...............................16
2.5 V TAP AC Test Conditions .......................................17
2.5 V TAP AC Output Load Equivalent .........................17
TAP DC Electrical Characteristics
Scan Register Sizes .......................................................18
Instruction Codes ...........................................................18
Boundary Scan Order ....................................................19
Boundary Scan Order ....................................................20
Maximum Ratings ...........................................................21
Operating Range .............................................................21
Electrical Characteristics ...............................................21
DC Electrical Characteristics .....................................21
Capacitance ....................................................................22
Thermal Resistance ........................................................22
AC Test Loads and Waveforms .....................................22
Switching Characteristics ..............................................23
Switching Waveforms ....................................................24
Ordering Information ......................................................28
Ordering Code Definitions .........................................28
Package Diagrams ..........................................................29
Acronyms ........................................................................31
Document Conventions .................................................31
Units of Measure .......................................................31
Document History Page .................................................32
Sales, Solutions, and Legal Information ......................33
Worldwide Sales and Design Support .......................33
Products ....................................................................33
PSoC® Solutions ......................................................33
Cypress Developer Community .................................33
Technical Support .....................................................33
and Operating Conditions .............................................17
Identification Register Definitions ................................18
Document Number: 001-70167 Rev. *E
Page 4 of 33
CY7C1440AV25
CY7C1446AV25
Pin Configurations
Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1440AV25 (1 M × 36)
1
2
3
4
5
6
7
8
9
10
A
11
NC
NC/288M
NC/144M
DQPC
A
B
C
D
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
A
BWE
GW
VSS
VSS
ADV
ADSP
VDDQ
VDDQ
A
CE2
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
OE
VSS
VDD
NC
NC/1G
DQB
DQC
DQC
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
Document Number: 001-70167 Rev. *E
Page 5 of 33
CY7C1440AV25
CY7C1446AV25
Pin Configurations (continued)
Figure 2. 209-ball FBGA (14 × 22 × 1.76 mm) pinout
CY7C1446AV25 (512 K × 72)
1
2
3
4
5
6
7
8
9
10
11
DQG
DQG
DQG
A
B
C
D
E
F
DQG
DQG
A
ADSP
ADV
A
CE3
BWSB
BWSE
NC
DQB
DQB
CE2
ADSC
BW
A
DQB
DQB
NC/288M
NC/144M
BWSC
BWSH
VSS
BWSF
BWSG
BWSD
DQG
DQG
NC/576M
GW
CE1
BWSA DQB
DQB
DQB
DQG
NC/1G OE
VSS
NC
DQB
DQPG DQPC
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VDD
VSS
VDD
DQPF DQPB
DQC
DQC
VSS
DQF
DQF
VSS
VDDQ
VSS
NC
NC
NC
NC
VSS
NC
NC
VSS
G
H
J
DQC
DQC
DQC VDDQ
VDDQ
VSS
VDDQ
VSS
DQF
DQF
DQF
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
VSS
VDDQ
CLK
VDDQ
VSS
DQC
DQC
NC
DQF
DQF
NC
VDDQ
DQC
NC
VDDQ
VDDQ
NC
DQF
NC
K
L
NC
NC
DQH
DQH
DQH
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
DQA
DQA
DQA
M
N
P
R
T
VSS
VDDQ
VSS
VDDQ
NC
DQH
DQH
DQH
VSS
VDD
VSS
DQA
DQA
DQA
VDDQ
DQH
DQH
DQPD
DQD
DQD
VDDQ
VSS
VDDQ
NC
ZZ
DQA
DQA
DQPA
DQE
DQE
VSS
VDDQ
VSS
A
VDD
NC
A
DQPH
DQD
DQD
DQD
DQD
VDDQ
VDD
MODE
A
DQPE
DQE
DQE
DQE
DQE
VSS
NC
A
U
V
W
A
NC/72M
A
A
A1
A
DQD
DQD
A
A
A
A
DQE
DQE
TDI
TDO
TCK
A0
A
TMS
Document Number: 001-70167 Rev. *E
Page 6 of 33
CY7C1440AV25
CY7C1446AV25
Pin Definitions
Name
I/O
Description
Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK
A0, A1, A
Input-
Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the two-bit
counter.
BWA, BWB,
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
BWC, BWD, Synchronous on the rising edge of CLK.
BWE, BWF,
BWG, BWH
GW
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
BWE
CLK
CE1
Input- Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new
external address is loaded.
CE2
CE3
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded.
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous andCE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is assumed active
throughout this document for BGA. CE3 is sampled only when a new external address is loaded.
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull-down.
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
DQs, DQPs
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed
in a tri-state condition.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
VSSQ
VDDQ
I/O Ground Ground for the I/O circuitry.
I/O Power Power supply for the I/O circuitry.
Supply
Document Number: 001-70167 Rev. *E
Page 7 of 33
CY7C1440AV25
CY7C1446AV25
Pin Definitions (continued)
Name
MODE
I/O
Description
Input-Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode Pin has an internal pull-up.
TDO
TDI
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
output
not being utilized, this pin should be disconnected.
Synchronous
JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
utilized, this pin can be disconnected or connected to VDD.
Synchronous
TMS
JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
utilized, this pin can be disconnected or connected to VDD.
Synchronous
TCK
NC
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected
to VSS
.
–
–
No Connects. Not internally connected to the die
NC/72M,
NC/144M,
NC/288M,
NC/576,
NC/1G
No Connects. Not internally connected to the die. 72M, 144M, 288M, 576M and 1G are address
expansion pins are not internally connected to the die.
HIGH. The address presented to the address inputs (A) is stored
Functional Overview
into the address advancement logic and the Address Register
while being presented to the memory array. The corresponding
data is allowed to propagate to the input of the Output Registers.
At the rising edge of the next clock the data is allowed to
propagate through the output register and onto the data bus
within 2.6 ns (250-MHz device) if OE is active LOW. The only
exception occurs when the SRAM is emerging from a deselected
state to a selected state, its outputs are always tri-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive single
Read cycles are supported. Once the SRAM is deselected at
clock rise by the chip select and either ADSP or ADSC signals,
its output will tri-state immediately.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 2.6 ns (250-MHz
device).
The CY7C1440AV25/CY7C1446AV25 supports secondary cache
in systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is controlled
by the ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the memory array. The Write
signals (GW, BWE, and BWX) and ADV inputs are ignored during
this first cycle.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchronous
self-timed Write circuitry.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the Write operation is controlled by BWE and BWX
signals.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
The CY7C1440AV25/CY7C1446AV25 provides Byte Write
capability that is described in the Write Cycle Descriptions table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BWX) input, will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write signals
(GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is
Document Number: 001-70167 Rev. *E
Page 8 of 33
CY7C1440AV25
CY7C1446AV25
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Asserting ADV LOW at clock rise will automatically increment the
burst counter to the next address in the burst sequence. Both
Read and Write burst operations are supported.
Because CY7C1440AV25/CY7C1446AV25 is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQs inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQs are automatically
tri-stated whenever a Write cycle is detected, regardless of the
state of OE.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
CE3, ADSP, and ADSC must remain inactive for the duration of
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the Write inputs (GW, BWE, and
BWX) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a Byte Write is conducted, only the selected
bytes are written. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed Write
mechanism has been provided to simplify the Write operations.
tZZREC after the ZZ input returns LOW
.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Because CY7C1440AV25/CY7C1446AV25 is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQs inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQs are automatically
tri-stated whenever a Write cycle is detected, regardless of the
state of OE.
Linear Burst Address Table
(MODE = GND)
Burst Sequences
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
The CY7C1440AV25/CY7C1446AV25 provides
a
two-bit
wraparound counter, fed by A1:A0, that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium appli-
cations. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
100
2tCYC
–
Unit
mA
ns
ZZ > VDD– 0.2 V
–
tZZS
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
2tCYC
–
tZZREC
tZZI
ns
ZZ Active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ Inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 001-70167 Rev. *E
Page 9 of 33
CY7C1440AV25
CY7C1446AV25
Truth Table
The truth table for CY7C1440AV25/CY7C1446AV25 follows. [1, 2, 3, 4, 5, 6]
Operation
Address Used CE1 CE2
ZZ ADSP ADSC ADV WRITE OE CLK
DQ
CE3
X
X
H
X
H
X
L
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
None
None
H
L
L
L
L
X
L
L
L
L
L
X
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L–H Tri-State
L–H Tri-State
L–H Tri-State
L–H Tri-State
L–H Tri-State
None
X
L
L
None
H
H
X
L
None
X
X
H
H
H
H
H
X
X
X
L
None
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L–H
L
L
H
X
L
L–H Tri-State
L
H
H
H
H
H
X
L–H
L–H
D
Q
L
L
H
H
H
H
H
L
L
H
L
L–H Tri-State
L–H
L–H Tri-State
L–H
L–H Tri-State
X
X
X
H
H
H
Q
Next
L
H
L
Next
L
Q
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Next
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
X
H
X
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
L
L
H
L
H
X
X
L
Next
L–H
L–H
L–H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L–H Tri-State
L–H
L–H Tri-State
Q
H
X
X
L–H
L–H
D
D
L
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. BGA package has only two chip selects CE and CE .
1
2
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after
X
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care
for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-70167 Rev. *E
Page 10 of 33
CY7C1440AV25
CY7C1446AV25
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1440AV25 follows. [7, 8, 9]
Function (CY7C1440AV25)
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
X
H
H
L
BWA
X
H
L
Read
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
L
L
H
L
L
L
Write Byte C – (DQC and DQPC)
Write Bytes C, A
L
H
H
L
H
L
L
L
Write Bytes C, B
L
L
H
L
Write Bytes C, B, A
Write Byte D – (DQD and DQPD)
Write Bytes D, A
L
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
Write Bytes D, B
L
L
H
L
Write Bytes D, B, A
Write Bytes D, C
L
L
L
L
L
H
H
L
H
L
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes
X
X
X
X
X
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1446AV25 follows. [7, 8, 9]
Function (CY7C1446AV25)
GW
H
BWE
BWx
Read
Read
H
L
L
L
X
H
All BW = H
L
Write Byte x – (DQx and DQPx)
Write All Bytes
H
H
All BW = L
Notes
7. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
8. BWx represents any byte write signal. To enable any byte write BW a Logic LOW signal should be applied at clock rise. Any number of bye writes can be enabled
x,
at the same time for any given write.
9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document Number: 001-70167 Rev. *E
Page 11 of 33
CY7C1440AV25
CY7C1446AV25
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1440AV25/CY7C1446AV25 incorporates a serial
boundary scan test access port (TAP). This part is fully compliant
with IEEE Standard 1149.1.The TAP operates using
JEDEC-standard 2.5 V I/O logic level.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 15. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
The CY7C1440AV25/CY7C1446AV25 contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 14. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
The Boundary Scan Order on page 19 and Boundary Scan Order
on page 20 show the order in which the bits are connected. Each
bit corresponds to one of the bumps on the SRAM package. The
MSB of the register is connected to TDI, and the LSB is
connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 18.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Overview
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes on page 18. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Document Number: 001-70167 Rev. *E
Page 12 of 33
CY7C1440AV25
CY7C1446AV25
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required — that is, while data captured
is shifted out, the preloaded data can be shifted in.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High Z state until the next command is given
during the “Update IR” state.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package) or bit #138 (for 209-ball FBGA
package). When this scan cell, called the “extest output bus
tri-state”, is latched into the preload register during the
“Update-DR” state in the TAP controller, it will directly control the
state of the output (Q-bus) pins, when the EXTEST is entered as
the current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place the
output bus into a High Z condition.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is pre-set
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK# captured in the boundary
scan register.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-70167 Rev. *E
Page 13 of 33
CY7C1440AV25
CY7C1446AV25
TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
Document Number: 001-70167 Rev. *E
Page 14 of 33
CY7C1440AV25
CY7C1446AV25
TAP Controller Block Diagram
0
Bypass Register
2 1 0
Selection
Circuitry
Instruction Register
Selection
TDI
TDO
Circuitr
y
31 30 29 .
.
. 2 1 0
Identification Register
2 1 0
x
.
.
.
.
.
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
TAP Timing
Figure 3. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 001-70167 Rev. *E
Page 15 of 33
CY7C1440AV25
CY7C1446AV25
TAP AC Switching Characteristics
Over the Operating Range
Parameter [10, 11]
Clock
Description
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
tTDOX
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
–
–
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes
10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document Number: 001-70167 Rev. *E
Page 16 of 33
CY7C1440AV25
CY7C1446AV25
2.5 V TAP AC Test Conditions
2.5 V TAP AC Output Load Equivalent
1.25V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)
Parameter [12]
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Test Conditions
VDDQ = 2.5 V
Min
2.0
2.1
–
Max
–
Unit
V
VOH1
VOH2
VOL1
VOL2
VIH
IOH = –1.0 mA
IOH = –100 µA
IOL = 1.0 mA
IOL = 100 µA
VDDQ = 2.5 V
VDDQ = 2.5 V
VDDQ = 2.5 V
VDDQ = 2.5 V
VDDQ = 2.5 V
–
V
0.4
0.2
V
–
V
1.7
–0.3
–5
VDD + 0.3
V
VIL
0.7
5
V
IX
GND < VIN < VDDQ
µA
Note
12. All voltages referenced to V (GND).
SS
Document Number: 001-70167 Rev. *E
Page 17 of 33
CY7C1440AV25
CY7C1446AV25
Identification Register Definitions
CY7C1440AV25
CY7C1446AV25
(512 K × 72)
Instruction Field
Description
(1 M × 36)
Revision Number (31:29)
000
000
01011
Describes the version number.
Device Depth (28:24)
01011
Reserved for Internal Use
Architecture/Memory Type (23:18)
Bus Width/Density (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
000000
100111
00000110100
1
000000
110111
00000110100
1
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Bit Size (× 72)
Instruction
Bypass
ID
3
1
3
1
32
89
–
32
–
Boundary Scan Order (165-ball FBGA package)
Boundary Scan Order (209-ball FBGA package)
138
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 001-70167 Rev. *E
Page 18 of 33
CY7C1440AV25
CY7C1446AV25
Boundary Scan Order
165-ball FBGA [13, 14]
CY7C1440AV25 (1 M × 36)
Bit #
1
Ball ID
Bit #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ball ID
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
Bit #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
Bit #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
N1
N6
N7
2
N2
3
N10
P11
P8
P1
4
R1
5
R2
6
R8
P3
7
R9
R3
8
P9
P2
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
R4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P4
G1
D2
E2
F2
N5
P6
B9
R6
C10
A8
Internal
G2
H1
H3
J1
B8
A7
B7
B6
K1
L1
A6
M1
J2
B5
A5
A4
B4
B3
H10
G11
F11
K2
L2
M2
Notes
13. Balls which are NC (No Connect) are Pre-Set LOW.
14. Bit# 89 is Pre-Set HIGH.
Document Number: 001-70167 Rev. *E
Page 19 of 33
CY7C1440AV25
CY7C1446AV25
Boundary Scan Order
209-ball FBGA [15, 16]
CY7C1446AV25 (512 K × 72)
Bit #
1
Ball ID
Bit #
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Ball ID
F6
Bit #
71
Ball ID
Bit #
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Ball ID
K3
W6
V6
H6
C6
B6
A6
A5
B5
C5
D5
D4
C4
A4
B4
C3
B3
A3
A2
A1
B2
B1
C2
C1
D2
D1
E1
E2
F2
F1
G1
G2
H2
H1
J2
2
K8
72
K4
3
U6
K9
73
K6
4
W7
V7
K10
J11
J10
H11
H10
G11
G10
F11
F10
E10
E11
D11
D10
C11
C10
B11
B10
A11
A10
C9
74
K2
5
75
L2
6
U7
76
L1
7
T7
77
M2
M1
N2
N1
P2
8
V8
78
9
U8
79
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
T8
80
V9
81
U9
82
P1
P6
83
R2
R1
T2
W11
W10
V11
V10
U11
U10
T11
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
L10
K11
M6
84
85
86
T1
87
U2
U1
V2
88
89
90
V1
91
W2
W1
T6
92
93
B9
94
U3
V3
A9
95
D7
96
T4
C8
97
T5
B8
98
U4
V4
A8
99
D8
100
101
102
103
104
105
5W
5V
C7
B7
5U
Internal
A7
J1
L6
D6
K1
N6
J6
G6
Notes
15. Balls which are NC (No Connect) are Pre-Set LOW.
16. Bit# 138 is Pre-Set HIGH.
Document Number: 001-70167 Rev. *E
Page 20 of 33
CY7C1440AV25
CY7C1446AV25
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Storage Temperature ............................... –65 °C to +150 °C
Latch-up Current ................................................... > 200 mA
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Operating Range
Supply Voltage on VDD Relative to GND .....–0.3 V to +3.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
Ambient
Range
VDD
VDDQ
Temperature
0 °C to +70 °C
–40 °C to +85 °C
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
Commercial
Industrial
2.5 V+ 5% 1.7 V to VDD
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [17, 18]
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
2.375
2.375
2.0
Max
2.625
2.625
–
Unit
V
VDD
VDDQ
VOH
VOL
VIH
for 2.5 V I/O
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[17]
Input LOW Voltage[17]
for 2.5 V I/O, IOH = –1.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 2.5 V I/O
V
–
0.4
V
1.7
VDD + 0.3
0.7
V
VIL
for 2.5 V I/O
–0.3
–5
V
IX
Input Leakage Current except ZZ GND VI VDDQ
and MODE
5
A
Input Current of MODE
Input = VSS
–30
–
–
5
A
A
A
A
A
mA
Input = VDD
Input Current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
IDD
Output Leakage Current
GND VI VDDQ, Output Disabled
–5
–
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
435
6-ns cycle,
167 MHz
335
185
mA
mA
ISB1
ISB2
ISB3
ISB4
Automatic CE Power-down
Current – TTL Inputs
VDD = Max, Device Deselected, All speeds
VIN VIH or VIN VIL,
–
–
–
–
f = fMAX = 1/tCYC
Automatic CE Power-down
Current – CMOS Inputs
VDD = Max, Device Deselected, All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V,
f = 0
120
160
135
mA
mA
mA
Automatic CE Power-down
Current – CMOS Inputs
VDD = Max, Device Deselected, All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V,
f = fMAX = 1/tCYC
Automatic CE Power-down
Current – TTL Inputs
VDD = Max, Device Deselected, All speeds
VIN VIH or VIN VIL, f = 0
Notes
17. Overshoot: V
18. TPower-up: Assumes a linear ramp from 0 V to V
< V + 1.5 V (Pulse width less than t
/2), undershoot: V
> –2 V (Pulse width less than t
/2).
IH(AC)
DD
CYC
IL(AC)
CYC
.
within 200 ms. During this time V < V and V
< V
DD(min)
IH
DD
DDQ DD
Document Number: 001-70167 Rev. *E
Page 21 of 33
CY7C1440AV25
CY7C1446AV25
Capacitance
165-ball FBGA 209-ball FBGA
Parameter [19]
Description
Input Capacitance
Test Conditions
Unit
Max
Max
CIN
TA = 25 °C, f = 1 MHz, VDD/VDDQ = 2.5 V
7
7
6
5
5
7
pF
pF
pF
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
Thermal Resistance
165-ballFBGA 209-ballFBGA
Parameter [19]
Description
Test Conditions
Unit
Package
Package
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
20.8
25.31
°C/W
JC
Thermal resistance
(junction to case)
3.2
4.48
°C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
10%
L
GND
5 pF
R = 1538
1 ns
1 ns
INCLUDING
JIG AND
SCOPE
V = 1.25 V
T
(a)
(b)
(c)
Note
19. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-70167 Rev. *E
Page 22 of 33
CY7C1440AV25
CY7C1446AV25
Switching Characteristics
Over the Operating Range
-250
-167
Unit
Parameter [20, 21]
Description
Min
Max
Min
Max
tPOWER
Clock
tCYC
VDD(typical) to the first Access[22]
1
–
1
–
ms
Clock Cycle Time
Clock HIGH
4.0
1.5
1.5
–
–
–
6.0
2.4
2.4
–
–
–
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCO
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low Z [23, 24, 25]
–
1.0
1.0
–
2.6
–
–
1.5
1.5
–
3.4
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
–
tCHZ
Clock to High Z [23, 24, 25]
2.6
2.6
–
3.4
3.4
–
tOEV
OE LOW to Output Valid
–
–
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low Z [23, 24, 25]
OE HIGH to Output High Z [23, 24, 25]
0
0
–
2.6
–
3.4
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
1.2
1.2
1.2
1.2
1.2
1.2
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
tDS
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
tADVH
tWEH
GW, BWE, BWX Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tDH
tCEH
Notes
20. Timing reference level is 1.25 V when V
= 2.5 V.
DDQ
21. Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted.
22. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V
initially before a read or write operation can
POWER
DD(minimum)
be initiated.
23. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of Figure 4 on page 22. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
24. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
OEHZ
OELZ
CHZ
CLZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document Number: 001-70167 Rev. *E
Page 23 of 33
CY7C1440AV25
CY7C1446AV25
Switching Waveforms
Figure 5. Read Cycle Timing [26]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BWx
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
t
CHZ
OELZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
26. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document Number: 001-70167 Rev. *E
Page 24 of 33
CY7C1440AV25
CY7C1446AV25
Switching Waveforms (continued)
Figure 6. Write Cycle Timing [27, 28]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
ADDRESS
BWE,
t
t
AH
AS
A1
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
Notes
27. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
28.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document Number: 001-70167 Rev. *E
Page 25 of 33
CY7C1440AV25
CY7C1446AV25
Switching Waveforms (continued)
Figure 7. Read/Write Cycle Timing [29, 30, 31]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE,
BWX
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes
29. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
30. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
31. GW is HIGH.
Document Number: 001-70167 Rev. *E
Page 26 of 33
CY7C1440AV25
CY7C1446AV25
Switching Waveforms (continued)
Figure 8. ZZ Mode Timing [32, 33]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
32. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
33. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-70167 Rev. *E
Page 27 of 33
CY7C1440AV25
CY7C1446AV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
250 CY7C1440AV25-250BZXI
CY7C1446AV25-250BGI
51-85195 165-ball FBGA (15 × 17 × 1.4mm) Pb-free
51-85167 209-ball FBGA (14 × 22 × 1.76mm)
51-85195 165-ball FBGA (15 × 17 × 1.4mm) Pb-free
Industrial
167 CY7C1440AV25-167BZXC
Commercial
Ordering Code Definitions
- XXX
X
XX
X
CY 7 C 144X A V25
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C
Pb-free
Package Type: XX = BZ or BG
BZ = 165-ball FBGA; BG = 209-ball FBGA
Speed grade: XXX = 250 or 167 MHz
V25 = 2.5 V
Process Technology: A = greater than or equal to 90 nm
Part Identifier: 144X = 1440 or 1446
1440 = SCD 1 Mb × 36 (36 Mb); 1446 = SCD 512 K × 72 (36 MB)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-70167 Rev. *E
Page 28 of 33
CY7C1440AV25
CY7C1446AV25
Package Diagrams
Figure 9. 165-ball FBGA (15 × 17 × 1.40 mm) (0.50 ball diameter) Package Outline, 51-85195
51-85195 *D
Document Number: 001-70167 Rev. *E
Page 29 of 33
CY7C1440AV25
CY7C1446AV25
Package Diagrams (continued)
Figure 10. 209-ball FBGA (14 × 22 × 1.76 mm) BB209A Package Outline, 51-85167
51-85167 *C
Document Number: 001-70167 Rev. *E
Page 30 of 33
CY7C1440AV25
CY7C1446AV25
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CMOS
CE
Complementary Metal Oxide Semiconductor
Chip Enable
Symbol
°C
Unit of Measure
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
millisecond
millivolt
MHz
µA
µs
FBGA
I/O
Fine-Pitch Ball Grid Array
Input/Output
JTAG
LSB
MSB
OE
Joint Test Action Group
Least Significant Bit
Most Significant Bit
Output Enable
mA
mm
ms
mV
ns
SRAM
TCK
TDI
Static Random Access Memory
Test Clock
nanosecond
percent
%
Test Data-In
pF
V
picofarad
volt
TDO
TMS
TTL
Test Data-Out
Test Mode Select
W
watt
Transistor-Transistor Logic
Write Enable
WE
Document Number: 001-70167 Rev. *E
Page 31 of 33
CY7C1440AV25
CY7C1446AV25
Document History Page
Document Title:CY7C1440AV25/CY7C1446AV25, 36-Mbit (1 M × 36/512 K × 72) Pipelined Sync SRAM
Document Number: 001-70167
Orig. of
Change
Rev.
ECN No.
Issue Date
Description of Change
**
3281372
3508385
4234753
01/17/2012
01/25/2012
01/07/2014
NJY
New data sheet.
*A
*B
NJY
Changed status from Preliminary to Final.
PRIT
Updated Package Diagrams:
Replaced spec 51-85165 with spec 51-85195.
spec 51-85167 – Changed revision from *B to *C.
Updated to new template.
Completing Sunset Review.
*C
*D
4575228
4905904
11/20/2014
09/02/2015
PRIT
PRIT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Removed 1.8 V TAP AC Test Conditions.
Removed 1.8 V TAP AC Output Load Equivalent.
Updated TAP DC Electrical Characteristics and Operating Conditions:
Removed details corresponding to Test Condition “VDDQ = 1.8 V” for all
parameters.
Updated Electrical Characteristics:
Removed details corresponding to Test Condition “for 1.8 V I/O” for all
parameters.
Updated Package Diagrams:
spec 51-85195 – Changed revision from *C to *D.
Updated to new template.
*E
5072691
01/05/2016
PRIT
No technical updates.
Completing Sunset Review.
Document Number: 001-70167 Rev. *E
Page 32 of 33
CY7C1440AV25
CY7C1446AV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
cypress.com/go/psoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Lighting & Power Control
Memory
Community | Forums | Blogs | Video | Training
Technical Support
PSoC
cypress.com/go/support
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2012-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-70167 Rev. *E
Revised January 5, 2016
Page 33 of 33
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
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