CY7C1441V33-150BGC
更新时间：2024-10-29 18:13:23
品牌：CYPRESS
描述：Standard SRAM, 1MX36, 5.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
概述
规格参数
数据手册CY7C1441V33-150BGC 概述
Standard SRAM, 1MX36, 5.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 SRAM
CY7C1441V33-150BGC 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | BGA | 包装说明： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 针数： | 119 | Reach Compliance Code： | compliant |
| ECCN代码： | 3A991.B.2.A | HTS代码： | 8542.32.00.41 |
| 风险等级： | 5.92 | 最长访问时间： | 5.5 ns |
| 其他特性： | FLOW-THROUGH ARCHITECTURE | 最大时钟频率 (fCLK)： | 150 MHz |
| I/O 类型： | COMMON | JESD-30 代码： | R-PBGA-B119 |
| JESD-609代码： | e0 | 长度： | 22 mm |
| 内存密度： | 37748736 bit | 内存集成电路类型： | STANDARD SRAM |
| 内存宽度： | 36 | 功能数量： | 1 |
| 端子数量： | 119 | 字数： | 1048576 words |
| 字数代码： | 1000000 | 工作模式： | SYNCHRONOUS |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 组织： | 1MX36 | 输出特性： | 3-STATE |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | BGA |
| 封装等效代码： | BGA119,7X17,50 | 封装形状： | RECTANGULAR |
| 封装形式： | GRID ARRAY | 并行/串行： | PARALLEL |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 电源： | 2.5/3.3,3.3 V |
| 认证状态： | Not Qualified | 座面最大高度： | 2.4 mm |
| 最小待机电流： | 3.14 V | 子类别： | SRAMs |
| 最大供电电压 (Vsup)： | 3.465 V | 最小供电电压 (Vsup)： | 3.135 V |
| 标称供电电压 (Vsup)： | 3.3 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | COMMERCIAL |
| 端子面层： | TIN LEAD | 端子形式： | BALL |
| 端子节距： | 1.27 mm | 端子位置： | BOTTOM |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 14 mm |
| Base Number Matches： | 1 |
CY7C1441V33-150BGC 数据手册
通过下载CY7C1441V33-150BGC数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
1M x 36/2M x 18/512K x 72
Flow-through SRAM
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE), Burst Control Inputs (ADSC, ADSP, and
ADV), Write Enables (BWa, BWb, BWc, BWd, BWe, BWf, BWg,
BWh, and BWe), and Global Write (GW).
Features
• Supports 133-MHz bus operations
• 1M x 36/2M x 18/512K x 72 common I/O
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (DQ), enabled
by OE, are also asynchronous.
• Single 3.3V –5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V
• Byte Write Enable and Global Write control
• Burst Capability – linear or interleaved burst order
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or address status controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQ1–DQ8 and DP1. BWb controls DQ9–DQ16 and
DP2. BWc controls DQ17–DQ24 and DP3. BWd controls
DQ25–DQ32 and DP4. BWe controls DQ33–DQ40 and DP5.
BWf controls DQ41–DQ48 and DP6. BWg controls
DQ49–DQ56 and DP7. BWh controls DQ57–DQ64 and DP8.
BWa, BWb, BWc, BWd, BWe, BWf, BWg, and BWh can be
active only with BWE being LOW. GW being LOW causes all
bytes to be written. Write pass-through capability allows
written data available at the output for the immediately next
Read cycle. This device also incorporates pipelined enable
circuit for easy depth expansion without penalizing system
performance.
• Automatic power down available using ZZ mode or CE
deselect
• JTAG boundary scan for BGA packaging version
• Available in 119-ball bump BGA, 165-ball FBGA, and
100-pin TQFP packages (CY7C1441V33 and
CY7C1443V33). 209 FBGA package for CY7C1447V33.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced
single-layer polysilicon, triple-layer metal technology. Each
memory cell consists of six transistors.
The CY7C1441V33/CY7C1443V33/CY7C1447V33 SRAMs
integrate 1,048,576 x 36/2,097,152 x18 and 524,288 x 72
SRAM cells with advanced synchronous peripheral circuitry
and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
All inputs and outputs of theCY7C1441V33/CY7C1443V33/
CY7C1447V33 are JEDEC-standard JESD8-5-compatible.
Logic Block Diagram CY7C1441V33 – 1M × 36
MODE
2
(A[1;0]
)
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
18
20
ADDRESS
REGISTER
CE
D
1M X36
A[19:0]
GW
20
18
MEMORY
ARRAY
DQd, DPd
BYTEWRITE
REGISTERS
D
Q
BWE
BW
d
DQc, DPc
BYTEWRITE
REGISTERS
D
D
D
Q
Q
Q
BW
c
DQb, DPb
BYTEWRITE
REGISTERS
BW
b
DQa, DPa
BYTEWRITE
REGISTERS
BW
a
36
36
CE
CE
1
2
D
D
Q
ENABLE CE
REGISTER
CE
3
Q
OUTPUT
REGISTERS
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
CLK
OE
ZZ
SLEEP
CONTROL
DQa,b,c,d
DPa,b,c,d
Cypress Semiconductor Corporation
Document #: 38-05185 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 13, 2002
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Logic Block Diagram CY7C1443V33–2M × 8
MODE
2
(A
)
[1;0]
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
19
21
ADDRESS
REGISTER
CE
D
2M X 18
MEMORY
ARRAY
A
[20:0]
21
19
GW
DQ , DP
BYTEWRITE
REGISTERS
D
Q
b
b
BWE
BW
b
DQ , DP
BYTEWRITE
REGISTERS
D
Q
a
a
BW
a
18
18
CE
2
1
CE
D
CE
Q
ENABLE CE
REGISTER
CE
3
D
Q
OUTPUT
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
a,b
DP
a,b
Logic Block Diagram CY7C1447V33–512K × 72
MODE
2
(A
)
[1;0]
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
17
19
ADDRESS
REGISTER
CE
D
512KX72
MEMORY
ARRAY
A
[18:0]
19
17
GW
DQ , DP
BYTEWRITE
REGISTERS
D
Q
h
h
BWE
BW
h
DQ , DP
BYTEWRITE
REGISTERS
D
D
D
Q
Q
Q
g
g
BW
g
DQ , DP
f
f
BYTEWRITE
REGISTERS
BW
f
DQ , DP
e
e
BYTEWRITE
REGISTERS
BW
e
DQ , DP
BYTEWRITE
REGISTERS
D
D
D
D
Q
Q
Q
Q
d
d
BW
BW
d
DQ , DP
c
c
BYTEWRITE
REGISTERS
c
DQ , DP
b
b
BYTEWRITE
REGISTERS
BW
b
DQ , DP
a
a
BYTEWRITE
REGISTERS
BW
a
72
72
CE
2
1
CE
D
D
Q
Q
ENABLE CE
REGISTER
CE
3
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
OE
ZZ
SLEEP
CONTROL
DQ
a,b,c,d,e,f,g,h
DP
a,b,c,d,e,f,g,h
Document #: 38-05185 Rev. *B
Page 2 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Selection Guide
CY7C1441V33
CY7C1443V33
CY7C1447V33
-150
CY7C1441V33
CY7C1443V33
CY7C1447V33
-133
CY7C1441V33
CY7C1443V33
CY7C1447V33
-117
Unit
ns
Maximum Access Time
5.5
6.5
7.5
Maximum Operating Current
Com’l
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
Maximum CMOS Standby Current
Shaded areas contain advance information.
Pin Configurations
100-pin TQFP
DQPc
1
NC
NC
NC
VDDQ
VSSQ
NC
DQPb
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
A
NC
NC
VDDQ
VSSQ
NC
DPa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
2
DQc
VDDQ
VSSQ
DQc
3
4
5
6
DQc
7
NC
DQc
8
DQb
DQb
VSSQ
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DPb
NC
DQc
9
9
VSSQ
10
10
11
12
13
VDDQ
11
DQc
12
DQc
13
NC
14
CY7C1443V33
(2M x 18)
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1441V33
(1M X 36)
VDD
NC
NC
VDD
ZZ
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
NC
VSSQ
VDDQ
NC
VSSQ
VDDQ
NC
NC
NC
NC
DQPa NC
Document #: 38-05185 Rev. *B
Page 3 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Pin Configurations (continued)
CY7C1441V33 (1M x 36)
1
3
2
4
5
6
7
A
A
A
VDDQ
NC
A
VDDQ
A
A
ADSP
ADSC
VDD
A
A
B
C
D
E
F
NC
NC
A
NC
A
A
A
A
DQPb
DQb
DQb
VSS
VSS
VSS
VSS
DQPc
NC
DQb
DQb
DQc
DQc
DQc
CE1
OE
VSS
VDDQ
DQc
VDDQ
DQb
DQb
VDDQ
DQa
VSS
BWb
VSS
NC
DQb
ADV
GW
VDD
G
H
J
DQc
DQc
VDD
DQd
DQd
BWc
VSS
NC
DQc
DQc
DQb
VDD
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
K
L
VSS
DQa
DQa
DQa
DQa
DQPa
A
VSS
CLK
NC
BWd
BWa
VSS
VSS
DQa
M
VDDQ
DQa
DQd
DQd
BWE
A1
VSS
VSS
N
P
R
T
DQPd
DQa
VSS
MODE
A
A0
VSS
NC
A
A
NC
ZZ
VDD
A
72M
A
NC
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
CY7C1443V33 (2M x 18)
1
2
3
4
5
6
7
A
B
C
D
E
F
A
A
VDDQ
NC
A
A
A
VDDQ
NC
A
A
ADSP
ADSC
VDD
A
NC
NC
A
A
A
A
VSS
VSS
VSS
VSS
DQb
NC
NC
DQb
NC
DQPa
NC
NC
DQa
CE1
OE
VSS
DQa
VDDQ
NC
VDDQ
DQa
NC
VSS
VSS
VSS
NC
NC
ADV
GW
VDD
G
H
J
NC
DQb
DQb
NC
BWb
VSS
NC
DQa
VDD
VDDQ
DQa
VDDQ
NC
VDD
DQb
NC
K
L
VSS
NC
DQa
NC
DQa
NC
A
VSS
VSS
CLK
NC
DQb
VDDQ
DQb
NC
BWa
VSS
VSS
NC
M
VDDQ
NC
DQb
NC
BWE
A1
VSS
VSS
N
P
R
T
DQPb
DQa
VSS
MODE
A
A0
VSS
NC
A
NC
A
A
NC
ZZ
Vdd
A
A
72M
VDDQ
U
TMS
TDI
TCK
TDO
NC
VDDQ
Document #: 38-05185 Rev. *B
Page 4 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Pin Configurations (continued)
165-ball Bump FBGA
CY7C1441V33 (1M x 36) - 11 x 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWc
BWb
CE
BWE
A
ADSC
ADV
A
NC
1
2
3
NC
DPc
DQc
A
CE
BWd
BWa
CLK
GW
B
C
D
OE
ADSP
A
NC
DPb
DQb
NC
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DQc
DQc
DQc
DQc
V
V
V
V
V
V
DQb
DD
SS
SS
SS
DD
DDQ
DQc
DQc
DQc
NC
V
V
V
V
E
F
V
V
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
G
H
J
V
V
DD
SS
SS
SS
DD
DDQ
V
NC
V
V
V
V
V
NC
SS
DD
SS
SS
SS
DD
DQd
DQd
DQd
DQd
DPd
NC
DQd
DQd
DQd
DQd
NC
V
V
V
V
V
V
V
DQa
DQa
DQa
DQa
NC
DQa
DQa
DQa
DQa
DPa
A
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
V
V
K
L
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
M
N
P
V
V
DDQ
DD
SS
SS
SS
DD
DDQ
V
NC
TDI
A
V
V
V
DDQ
SS
SS
SS
DDQ
72M
A
A
A
A1
A0
TDO
TCK
A
A
A
A
A
MODE
A
A
TMS
R
A
A
CY7C1443V33 (2M x 18) - 11 x 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWb
NC
CE
BWE
A
ADSC
ADV
A
A
1
2
3
NC
NC
NC
A
CE
NC
BWa
CLK
GW
B
C
D
E
F
OE
ADSP
A
NC
DPa
DQa
NC
V
V
V
V
V
V
V
V
V
V
V
NC
NC
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DQb
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
NC
NC
DQb
DQb
DQb
V
V
V
V
V
V
NC
NC
DQa
DQa
DQa
ZZ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
NC
V
V
V
V
G
H
J
V
V
NC
DD
SS
SS
SS
DD
DDQ
NC
V
NC
V
V
V
V
V
NC
NC
SS
DD
SS
SS
SS
DD
DQb
DQb
DQb
DQb
DPb
NC
NC
NC
NC
NC
NC
72M
V
V
V
V
V
V
V
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
NC
A
DDQ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
V
V
K
L
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
M
N
P
V
V
DD
SS
SS
SS
DD
DDQ
V
NC
TDI
A
V
V
V
DDQ
SS
SS
SS
DDQ
A
A
A
A1
A0
TDO
TCK
A
A
A
A
A
MODE
A
A
TMS
R
A
A
Document #: 38-05185 Rev. *B
Page 5 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Pin Configurations (continued)
CY7C1447V33 (512K x72)
1
DQg
DQg
DQg
2
3
4
5
6
7
8
9
10
DQb
11
A
B
C
D
E
F
DQg
DQg
CE
CE
ADSC
BW
DQb
DQb
3
2
A
ADSP
NC
ADV
A
A
BWS
DQb
DQb
BWS
BWS
f
BWS
b
c
g
DQg
DQg
DPc
DQc
DQc
NC
NC
NC
BWS
NC
BWS
CE
BWS
a
BWS
e
DQb
DQb
DPb
DQf
DQf
d
1
h
DQg
V
OE
GW
V
NC
V
SS
DQb
SS
DPg
DQc
V
V
V
V
V
V
DD
DDQ
DDQ
DDQ
SS
DDQ
DD
DD
DPf
DQf
V
V
V
V
V
NC
NC
NC
NC
V
V
SS
SS
DD
SS
SS
DD
SS
G
H
J
DQc
DQc
V
V
V
DDQ
V
V
V
DDQ
DQf
DQf
DDQ
DDQ
V
V
V
V
V
V
SS
V
DQc
DQc
NC
SS
SS
SS
SSQ
DDQ
SS
DQf
DQf
NC
DQc
NC
V
V
V
V
V
V
DDQ
DD
DD
DDQ
DDQ
DQf
NC
K
L
CLK
V
NC
V
SS
SS
SS
NC
NC
DQh
DQh
DQh
V
V
V
V
NC
NC
NC
ZZ
V
DDQ
DD
SS
DD
SS
DDQ
DDQ
DQa
DQa
DQa
DDQ
M
N
P
R
T
V
V
V
V
DQh
DQh
DQh
V
V
SS
SS
SS
SS
DQa
DQa
DQa
V
V
V
V
V
DDQ
DQh
DQh
DPd
DQd
DQd
V
V
V
V
V
V
DD
DD
SS
DDQ
DDQ
SS
DDQ
DQa
DQa
DPa
DQe
DQe
V
V
V
V
V
V
SS
SS
SS
SS
V
DPh
DQd
DQd
DQd
DQd
V
DDQ
V
DDQ
DD
DD
DDQ
DDQ
SS
DD
DPe
DQe
DQe
DQe
DQe
NC
V
NC
NC
NC
A
MODE
A
SS
U
V
W
A
A
A
A
NC
A
A
A1
A
DQd
DQd
A
A
A
DQe
DQe
TDI
TDO
TCK
A
A0
A
TMS
Pin Definition
Pin Name
I/O
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0]
feed the 2-bit counter.
BWa
BWb
BWc
BWd
BWe
BWf
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
BWg
BWh
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d,e,f,g,h
and BWE).
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
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CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Pin Definition (continued)
Pin Name
I/O
Pin Description
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE1
CE2
CE3
OE
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.(TQFP Only)
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.(TQFP Only)
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address StrobefromProcessor, sampledontherisingedgeof CLK. WhenassertedLOW,
A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
ADSC
MODE
ZZ
Input-
Synchronous
Address Strobe fromController, sampled onthe rising edgeof CLK. Whenasserted LOW,
A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When
ADSP and ADSC are both asserted, only ADSP is recognized.
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or
left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation.
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
Asynchronous condition with data integrity preserved.This pin can also be left as a NC.
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
DQe, DPe
DQf, DPf
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx
and DPx are placed in a three-state condition.DQ a,b,c,d,e,f,g and h are 8 bits wide. DP
a,b,c,d,e,f,g and h are 1 bit wide.
DQg, DPg
DQh, DPh
TDO
TDI
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA Only).
Synchronous This pin can be left as a floating pin if JTAG is not used.
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. (BGA Only). This pin
Synchronous can be left as a floating pin if JTAG is not used.
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous (BGA Only). This pin can be left as a floating pin if JTAG is not used.
TMS
TCK
VDD
JTAG serial clock Serial clock to the JTAG circuit. (BGA Only). This pin can be left as a floating pin if JTAG is
not used.
Power Supply
Ground
Power supply inputs to the core of the device. Should be connected to 3.3V ±5% power
supply.
VSS
Ground for the core of the device. Should be connected to ground of the system.
VDDQ
VSSQ
72M
NC
I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.375(min) to Vdd(max).
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
No connects. Reserved for address expansion.
No connects.
–
–
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CY7C1441V33
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PRELIMINARY
precaution, DQx are automatically three-stated whenever a
write cycle is detected, regardless of the state of OE.
Functional Description
Single Read Accesses
Single Write Accesses Initiated by ADSC
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip enable (CE1, CE2, CE3 on TQFP, CE1 on BGA)
asserted active, and (3) the write signals (GW, BWE) are all
deasserted HIGH. ADSP is ignored if CE1 is HIGH. The
address presented to the address inputs is stored into the
address advancement logic and the Address Register while
being presented to the memory core. If the OE input is
asserted LOW, the requested data will be available at the data
outputs a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) Chip Enable (CE1, CE2, CE3 on TQFP,
165FBGA and 209BGA, CE1 on 119BGA) asserted active, and
(4) the appropriate combination of the write inputs (GW, BWE,
and BWx) are asserted active to conduct a write to the desired
byte(s). ADSC is ignored if ADSP is active LOW.
The address presented to A[17:0] is loaded into the address
register and the address advancement logic while being
delivered to the RAM core. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQx is written into the corresponding address location in
the RAM core. If a byte write is conducted, only the selected
bytes are written. Bytes not selected during a byte write
operation will remain unaltered. All I/Os are three-stated
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) Chip Enable asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BWx) and ADV inputs are
ignored during this first clock cycle. If the write inputs are
asserted active (see Write Cycle Descriptions table for appro-
priate states that indicate a write) on the next clock rise, the
appropriate data will be latched and written into the device.
The CY7C1441V33/CY7C1443V33/CY7C1447V33 provides
byte write capability that is described in the Write Cycle
Description table. Asserting the Byte Write Enable input
(BWE) with the selected Byte Write (BWa,b,c,d,e,f,g,h for
CY7C1447V33 , BWa,b,c,d for CY7C1441V33 and BWa,b for
CY7C1443V33) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. All I/Os are three-stated during a byte write.
during
a
byte write because the CY7C1441V33/
CY7C1443V33/CY7C1447V33 is a common I/O device, the
Output Enable (OE) must be deasserted HIGH before
presenting data to the DQx inputs. Doing so will three-state the
output drivers. As a safety precaution, DQx are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Burst Sequences
The CY7C1441V33/CY7C1443V33/CY7C1447V33 provides
a two-bit wraparound counter, fed by A[1:0], that implements
either an interleaved or linear burst sequence. to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Because the CY7C1441V33/CY7C1443V33/CY7C1447V33
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQx inputs.
Doing so will three-state the output drivers. As a safety
[1, 2, 3, 4]
Cycle Descriptions
Next Cycle
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Add. Used
None
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
CE3
X
1
CE2
X
X
0
CE1
1
ADSP
ADSC
ADV
X
OE
X
X
X
X
X
X
X
1
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Write
X
X
0
0
1
1
0
1
1
1
X
X
1
0
X
X
0
0
X
0
1
1
1
1
1
None
0
X
X
None
X
1
0
X
X
None
X
0
0
X
X
None
X
0
0
X
X
External
External
1
0
X
X
0
1
0
X
Read
Read
Read
Read
Read
Read
Continue Read Next
Continue Read Next
Continue Read Next
Continue Read Next
Suspend Read Current
X
X
X
X
X
X
X
X
X
X
X
X
1
0
0
0
0
1
Hi-Z
DQ
1
0
0
X
1
1
Hi-Z
Notes:
1. X = “Don’t Care.” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has a single chip select CE1.
Document #: 38-05185 Rev. *B
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CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Cycle Descriptions (continued)[1, 2, 3, 4]
Suspend Read Current
Suspend Read Current
Suspend Read Current
L
L
L
L
L
L
L
L
L
L
H
X
X
X
X
X
0
X
X
X
X
X
1
X
1
1
X
1
0
X
1
X
1
X
1
X
X
1
1
1
1
1
1
0
1
1
1
1
X
1
1
1
1
1
X
0
0
1
1
X
0
1
DQ
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Hi-Z
0
DQ
Begin Write
Begin Write
Begin Write
Current
Current
External
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X
1
Continue Write Next
Continue Write Next
Suspend Write Current
Suspend Write Current
X
X
X
X
X
X
X
X
X
X
1
X
1
X
X
ZZ “sleep”
None
Sleep Mode
Interleaved Burst Sequence
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
First
Second
Third
Fourth
Address
Address
Address
Address
A[1:0]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
15
Unit
mA
ns
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
ZZ < 0.2V
2tCYC
ns
Write Cycle Descriptions[1, 2]
Function (CY7C1441V33)
Read
GW
1
BWE
BWd
BWc
BWb
BWa
1
0
0
0
0
0
0
X
1
1
1
1
1
1
X
1
1
1
1
0
0
X
1
1
0
0
1
1
X
1
0
1
0
1
0
Read
1
Write Byte 0 – DQa
Write Byte 1 – DQb
Write Bytes 1, 0
Write Byte 2 – DQc
Write Bytes 2, 0
1
1
1
1
1
Document #: 38-05185 Rev. *B
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CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Write Cycle Descriptions[1, 2]
Function (CY7C1441V33)
Write Bytes 2, 1
GW
1
BWE
BWd
BWc
BWb
BWa
1
0
0
0
0
0
0
0
0
0
0
X
1
1
0
0
0
0
0
0
0
0
X
0
0
1
1
1
1
0
0
0
0
X
0
0
1
1
0
0
1
1
0
0
X
Write Bytes 2, 1, 0
Write Byte 3 – DQd
Write Bytes 3, 0
1
0
1
1
1
0
Write Bytes 3, 1
1
1
Write Bytes 3, 1, 0
Write Bytes 3, 2
1
0
1
1
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
1
0
1
1
1
0
Write All Bytes
0
X
Function (CY7C1443V33)
Read
GW
1
BWE
BWb
BWa
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
Read
1
Write Byte 0 – DQ[7:0] and DP0
Write Byte 1 – DQ[15:8] and DP1
Write All Bytes
1
1
1
Write All Bytes
0
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1443V33/CY7C1441V33 incorporates a serial
boundary scan Test Access Port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1-1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Test Data Out (TDO)
Disabling the JTAG Feature
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
Test Access Port–Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
TAP Registers
Test Mode Select
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
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CY7C1441V33
CY7C1443V33
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PRELIMINARY
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
EXTEST
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
Bypass Register
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 70-bit-long
register, and the x18 configuration has a 51-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.
Identification (ID) Register
When the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data, or control signals into
the SRAM and cannot preload the Input or Output buffers. The
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PRELIMINARY
simply ignore the value of the CK and CK# captured in the
Bypass
boundary scan register.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Controller State Diagram[5]
TEST-LOGIC
1
RESET
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
1
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
5. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05185 Rev. *B
Page 12 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
2
1
1
1
0
Circuitry
Instruction Register
TDO
TDI
29
Identification Register
31 30
.
.
2
0
.
.
.
.
.
2
0
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[6, 7]
Parameter
VOH1
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Test Conditions
IOH = −4.0 mA
Min.
2.4
Max.
Unit
V
V
VOH2
VOL1
VOL2
VIH
IOH = −100 µA
IOL = 8.0 mA
IOL = 100 µA
3.0
0.4
0.2
V
V
1.8
–0.5
–5
VDD + 0.3
0.8
V
VIL
V
IX
GND ≤ VI ≤ VDDQ
5
µA
[8, 9]
TAP AC Switching Characteristics Over the Operating Range
Parameter
tTCYC
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
ns
MHz
ns
tTF
10
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
ns
ns
tTDIH
Notes:
6. All voltage referenced to ground.
7. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t <
200 ms.
8. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
9. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05185 Rev. *B
Page 13 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range (continued)[8, 9]
Parameter
Description
Min.
Max.
Unit
tCH
Capture Hold after clock rise
10
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
20
ns
ns
0
TAP Timing and Test Conditions
1.25V
ALL INPUT PULSES
Vih
50Ω
0V
TDO
Z = 50Ω
0
C = 20 pF
L
tTL
tTH
(a)
GND
Test Clock
TCK
tTC YC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Department Number (27:25)
Voltage (28&24)
x 18
x36
Description
000
101
00
000
101
00
Reserved for version number.
Department Number
Architecture (23:21)
000
001
010
111
000
001
100
111
Architecture Type
Memory type (20:18)
Device Width (17:15)
Device Density (14:12)
Defines type of memory
Defines width of the SRAM. x36 or x18
Defines the density of the SRAM
Document #: 38-05185 Rev. *B
Page 14 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Identification Register Definitions (continued)
Instruction Field
Revision Number (31:29)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
x 18
x36
Description
000
00000110100
1
000
00000110100
1
Reserved for version number.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (x18)
Bit Size (x36)
Instruction
Bypass
3
1
3
1
ID
32
51
32
70
Boundary Scan
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures the Input/Output ring contents. Places the boundary scan register between the TDI
and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
010
011
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
RESERVED
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document #: 38-05185 Rev. *B
Page 15 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Boundary Scan Order (1M × 36)
Boundary Scan Order (2M × 18)
Document #: 38-05185 Rev. *B
Page 16 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Temperature[9]
VDD
VDDQ
Supply Voltage on VDD Relative to GND ...... –0.5V to +4.6V
Range
DC Voltage Applied to Outputs
Com’l
0°C to +70°C
3.3V + 5%/ 2.375V (Min.)
in High-Z State[11]................................ –0.5V to VDDQ + 0.5V
–5%
Vdd(Max)
DC Input Voltage[11] ............................ –0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
2.375
2.4
Max.
Unit
V
3.465
VDD
VDDQ
V
VOH
VDD = Min., IOH = –4.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
V
Output HIGH Voltage
VDD = Min., IOH = –1.0 mA
VDD = Min., IOL = 8.0 mA
VDD = Min., IOL = 1.0 mA
2.0
V
VOL
0.4
0.4
V
Output LOW Voltage
V
VIH
2.0
1.7
V
Input HIGH Voltage
V
VIL
–0.3
–0.3
0.8
0.7
V
Input LOW Voltage[11]
V
IX
Input Load Current
GND ≤ VI ≤ VDDQ
5
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
Input Current of MODE
Output Leakage Current
VDD Operating Supply
30
IOZ
IDD
GND ≤ VI ≤ VDDQ, Output Disabled
5
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
150 MHz
TBD
TBD
TBD
TBD
TBD
TBD
TBD
133 MHz
117 MHz
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, 150 MHz
VIN > VIH or VIN < VIL
f = fMAX = 1/tCYC
133 MHz
117 MHz
ISB2
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
Current—CMOS Inputs
V
IN ≤ 0.3V or VIN > VDDQ
−
0.3V, f = 0
ISB3
Automatic CE
Power-down
Current—CMOS Inputs
Max. VDD, Device Deselected, 150 MHz
TBD
TBD
TBD
TBD
mA
mA
mA
mA
or VIN £ 0.3V or VIN > VDDQ
0.3V, f = fMAX = 1/tCYC
–
133 MHz
117 MHz
ISB4
Automatic CE
Power-down
Max. VDD, Device Deselected, All speed grades
IN ≥ VIH or VIN ≤ VIL, f = 0
V
Current—TTL Inputs
Shaded areas contain advance information.
Notes:
10.
TA is the ambient temperature.
11. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
Document #: 38-05185 Rev. *B
Page 17 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Capacitance[13]
Parameter
Description
Test Conditions
Max.
TBD
TBD
TBD
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = VDDQ = 3.3V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
AC Test Loads and Waveforms
R=317Ω
V
[12]
DDQ
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
V
DD
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
GND
R = 351Ω
V = 1.25V
L
Rise Time:
2 V/ns
Fall Time:
2 V/ns
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Thermal Resistance[13]
Parameter
Description
Test Conditions
BGA Typ. TQFP Typ. Unit
QJA
QJC
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board
TBD
TBD
°C/W
Thermal Resistance
(Junction to Case)
TBD
TBD
°C/W
Switching Characteristics (over the operating range)
150
133
117
Parameter
Clock
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
6.7
7.5
8.5
ns
MHz
ns
FMAX
Maximum Operating Frequency
Clock HIGH
150
133
117
tCH
2.5
2.5
2.5
2.5
3.0
3.0
tCL
Clock LOW
ns
Output Times
tCO
Data Output Valid After CLK Rise
OE LOW to Output Valid[15, 17]
5.5
3.0
6.5
3.0
7.5
3.5
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
Data Output Hold After CLK Rise
Clock to High-Z[13, 14, 15, 16, 17]
Clock to Low-Z[13, 14, 15, 16, 17]
OE HIGH to Output High-Z[13, 14, 15, 16, 17]
OE LOW to Output Low-Z[13, 14, 15, 16, 17]
2.5
2.5
0
2.5
2.5
0
2.5
2.5
0
tCHZ
5.0
4.0
5.0
4.0
5.0
4.0
tCLZ
tEOHZ
tEOLZ
Set-Up Times
tAS
Address Set-up Before CLK Rise
1.5
1.5
1.5
ns
Notes:
12. Input waveform should have a slew rate of > 1 V/ns.
13. Tested initially and after any design or process change that may affect these parameters.
14. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC test loads.
15.
tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
16. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document #: 38-05185 Rev. *B
Page 18 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Switching Characteristics (over the operating range) (continued)
150
133
117
Parameter
tDS
Description
Min.
1.5
1.5
1.5
1.5
1.5
Max.
Min.
1.5
1.5
1.5
1.5
1.5
Max.
Min.
1.5
1.5
1.5
1.5
1.5
Max.
Unit
ns
Data Input Set-up Before CLK Rise
ADSP, ADSC Set-up Before CLK Rise
BWE, GW, BWx Set-up Before CLK Rise
ADV Set-Up Before CLK Rise
Chip Select Set-Up
tADS
ns
tWES
tADVS
tCES
ns
ns
ns
Hold Times
tAH
Address Hold After CLK Rise
Data Input Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
BWE, GW, BWx Hold After CLK Rise
ADV Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tDH
tADH
tWEH
tADVH
tCEH
Chip Select Hold After CLK Rise
Shaded areas contain advance information.
Document #: 38-05185 Rev. *B
Page 19 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Switching Waveforms
Write Cycle Timing[18,19]
Single Write
Burst Write
Pipelined Write
tCH
Unselected
tCYC
tADH
CLK
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADH
tADS
ADSC initiated write
tADVH
tADVS
tAS
ADV Must Be Inactive for ADSP Write
WD3
ADD
GW
WE
CE1
WD1
WD2
tAH
tWH
tWH
tWS
tWS
tCES
tCEH
CE1 masks ADSP
tCEH
tCES
Unselected with CE2
CE2
CE3
tCES
tCEH
tDH
OE
tDS
High-Z
High-Z
Data In
3a
2a
1a
2b
2c
2d
= UNDEFINED
= DON’T CARE
Notes:
18. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Descriptions table).
19. WDx stands for Write Data to Address X.
Document #: 38-05185 Rev. *B
Page 20 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Switching Waveforms (continued)
Read Cycle Timing[18, 20]
Burst Read
Single Read
Unselected
tCYC
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
ADV
tADVS
tADH
Suspend Burst
tADVH
tAS
ADD
GW
RD3
RD1
RD2
tAH
tWS
tWS
tWH
BWE
CE1
tCES
tCEH
tWH
CE1 masks ADSP
Unselected with CE2
CE2
tCES
tCEH
CE3
OE
tCEH
tEOV
tCES
tOEHZ
tDOH
tCDV
3a
Data Out
2d
2a
2b
2c
1a
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
20. RDx stands for Read Data from Address X.
Document #: 38-05185 Rev. *B
Page 21 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Switching Waveforms (continued)
Read/Write Timing[18, 20]
tCYC
tCL
tCH
CLK
tAH
tAS
A
D
B
C
ADD
tADH
tADS
ADSP
tADH
tADS
ADSC
tADVH
tADVS
ADV
tCEH
tCES
CE1
CE
tCEH
tCES
tWES
tWEH
WE
OE
ADSP ignored
with CE1 HIGH
tEOHZ
tCLZ
Data
Q
(B+3)
D
(C+1)
D
(C+2)
D
(C+3)
Q
(B+2)
Q
(B+1)
Q(B)
Q(B)
D(C)
Q(A)
Q(D)
In/Out
tCDV
tDOH
tCHZ
Device originally
deselected
WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table).
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
Document #: 38-05185 Rev. *B
Page 22 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Switching Waveforms (continued)
OE Timing
OE
tEOV
tEOHZ
Three-state
I/O’s
tEOLZ
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
150
CY7C1441V33-150AC
CY7C1443V33-150AC
A101
100-pin 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1441V33-150BGC
CY7C1443V33-150BGC
BG119
119-ball BGA (14 x 22 x 2.4 mm)
CY7C1447V33-150BX
BG209
209-ball FBGA (14 x 22 x 2.2 mm)
165-ball FBGA (15 x 17 mm)
CY7C1441V33-150BZC
CY7C1443V33-150BZC
BB165C
133
117
CY7C1441V33-133AC
CY7C1443V33-133AC
A101
100-pin 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
CY7C1441V33-133BGC
CY7C1443V33-133BGC
BG119
CY7C1447V33-133BX
BG209
209-ball FBGA (14 x 22 x 2.2 mm)
165-ball FBGA (15 x 17 mm)
CY7C1441V33-133BZC
CY7C1443V33-133BZC
BB165C
CY7C1441V33-117AC
CY7C1443V33-117AC
A101
100-pin 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
CY7C1441V33-117BGC
CY7C1443V33-117BGC
BG119
CY7C1447V33-117BX
BG209
209-ball FBGA (14 x 22 x 2.2 mm)
165-ball FBGA (15 x 17 mm)
CY7C1441V33-117BZC
CY7C1443V33-117BZC
BB165C
Shaded areas contain advance information.
Document #: 38-05185 Rev. *B
Page 23 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Package Diagram
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05185 Rev. *B
Page 24 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Package Diagram (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05185 Rev. *B
Page 25 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Package Diagram (continued)
209-Lead PBGA (14 x 22 x 2.20 mm) BG209
51-85143-*B
Document #: 38-05185 Rev. *B
Page 26 of 28
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Package Diagram (continued)
165-ball FBGA (15 x 17 x 1.20 mm) BB165C
51-85165-**
Zero Bus Latency, No Bus Latency, and NoBL are trademarks of Cypress Semiconductor Corporation. All products and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05185 Rev. *B
Page 27 of 28
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1441V33
CY7C1443V33
CY7C1447V33
PRELIMINARY
Document History Page
Document Title: CY7C1441V33/CY7C1443V33/CY7C1447V33 1M x 36/2M x 18/512K x 72 Flow-through SRAM
Document Number: 38-05185
Orig. of
REV.
**
ECN No.
113763
116917
Issue Date
04/23/02
08/07/02
Change
Description of Change
PKS
New Data Sheet
*A
FLX
Tdoh increase to 2.5 ns
Shaded 150-MHz device information
*B
121475
11/14/02
DSG
Updated package diagrams 51-85115 (BG119) to rev. *B and
51-85143 (BG209) to rev. *B
Document #: 38-05185 Rev. *B
Page 28 of 28
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| CY7C1442AV25-167AXI | CYPRESS | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM | 获取价格 |
|
| CY7C1442AV25-167BZC | CYPRESS | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM | 获取价格 |
|
| CY7C1442AV25-167BZI | CYPRESS | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM | 获取价格 |
|
| CY7C1442AV25-167BZXC | CYPRESS | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM | 获取价格 |
|
| CY7C1442AV25-167BZXI | CYPRESS | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM | 获取价格 |
|
| CY7C1442AV25-200AXC | CYPRESS | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM | 获取价格 |
|
| CY7C1442AV25-200AXI | CYPRESS | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM | 获取价格 |
|
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