CY7C1445AV33 [CYPRESS]
36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM 3.3 V core power supply; 36兆位（ 1米× 36/2米× 18 ）流水线DCD同步SRAM 3.3 V核心供电
| 型号： | CY7C1445AV33 |
| 厂家： | 
CYPRESS |
| 描述： | 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM 3.3 V core power supply |
| 文件： | 总28页 (文件大小：762K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1444AV33
CY7C1445AV33
36-Mbit (1 M × 36/2 M × 18)
Pipelined DCD Sync SRAM
36-Mbit (1
M × 36/2 M × 18) Pipelined DCD Sync SRAM
Features
Functional Description[1]
■ Supports bus operation up to 250 MHz
■ Available speed grades are 250, 200, and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ Optimal for performance (double-cycle deselect)
■ Depth expansion without wait state
The CY7C1444AV33/CY7C1445AV33 SRAM integrates
1 M × 36/2 M × 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE1), depth-expansion chip
enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and
ADV), write enables (BWX, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
■ 3.3 V core power supply
■ 2.5 V/3.3 V I/O power supply
■ Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
■ Provide high-performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
by the byte write control inputs. GW
active
causes all bytes
LOW
■ Asynchronous output enable
This device incorporates an additional pipelined
to be written.
enable register which delays turning off the output buffers an
additional cycle when a deselect is executed. This feature allows
depth expansion without penalizing system performance.
■ CY7C1444AV33, CY7C1445AV33 available in
JEDEC-standard Pb-free 100-pin TQFP package and Pb-free
and non Pb-free 165-ball FBGA package
The CY7C1444AV33/CY7C1445AV33 operates from a +3.3 V
core power supply while all outputs operate with a +3.3 V or a
+2.5 V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
■ IEEE 1149.1 JTAG-compatible boundary scan
■ “ZZ” sleep mode option
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05352 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 29, 2010
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CY7C1444AV33
CY7C1445AV33
Logic Block Diagram – CY7C1444AV33 (1 M × 36)
ADDRESS
A0,A1,A
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQD,DQP
D
DQD,DQP
D
BYTE
BYTE
BW
D
WRITE REGISTER
WRITE DRIVER
DQ
BYTE
WRITE DRIVER
c,DQPC
DQ
BYTE
WRITE REGISTER
c,DQPC
MEMORY
ARRAY
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
SENSE
AMPS
DQs
DQPA
DQ
BYTE
WRITE DRIVER
B,DQPB
E
DQ
BYTE
WRITE REGISTER
B,DQPB
DQP
DQP
B
C
BW
BW
B
A
DQPD
DQA,DQP
A
DQA,DQP
A
BYTE
WRITE DRIVER
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
ZZ
CONTROL
Logic Block Diagram – CY7C1445AV33 (2 M × 18)
ADDRESS
REGISTER
A0, A1, A
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQB , DQP
BYTE
WRITE DRIVER
B
DQB, DQP
BYTE
WRITE REGISTER
B
OUTPUT
BUFFERS
BW
B
A
OUTPUT
REGISTERS
DQs,
DQP
DQP
SENSE
AMPS
MEMORY
ARRAY
A
DQA, DQP
BYTE
WRITE DRIVER
A
B
E
DQ
BYTE
WRITE REGISTER
A , DQPA
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
CE
1
PIPELINED
ENABLE
2
3
OE
SLEEP
ZZ
CONTROL
Document Number: 38-05352 Rev. *G
Page 2 of 28
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CY7C1444AV33
CY7C1445AV33
Contents
Selection Guide ................................................................4
Pin Configurations ...........................................................4
Pin Definitions ..................................................................6
Functional Overview ........................................................7
Single Read Accesses ................................................7
Single Write Accesses Initiated by ADSP ...................7
Single Write Accesses Initiated by ADSC ...................7
Burst Sequences .........................................................8
Sleep Mode .................................................................8
Interleaved Burst Address Table
(MODE = Floating or VDD) ................................................8
Linear Burst Address Table (MODE = GND) ..................8
ZZ Mode Electrical Characteristics .................................8
Truth Table ........................................................................9
Partial Truth Table for Read/Write ................................10
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11
Disabling the JTAG Feature ......................................11
TAP Controller State Diagram .......................................11
Test Access Port (TAP) .............................................11
TAP Controller Block Diagram ......................................11
PERFORMING A TAP RESET ..................................11
TAP REGISTERS ......................................................11
TAP Instruction Set ...................................................12
TAP Timing ......................................................................13
TAP AC Switching Characteristics ...............................13
3.3 V TAP AC Test Conditions .......................................14
3.3 V TAP AC Output Load Equivalent .........................14
2.5 V TAP AC Test Conditions .......................................14
2.5 V TAP AC Output Load Equivalent ........................14
TAP DC Electrical Characteristics
And Operating Conditions .............................................14
Identification Register Definitions ................................15
Scan Register Sizes .......................................................15
Identification Codes .......................................................15
165-ball FBGA Boundary Scan Order ...........................16
Maximum Ratings ...........................................................17
Operating Range .............................................................17
Electrical Characteristics ...............................................17
Capacitance ....................................................................18
Thermal Resistance ........................................................18
AC Test Loads and Waveforms .....................................18
Switching Characteristics ..............................................19
Switching Waveforms ....................................................20
Read Cycle Timing ....................................................20
Write Cycle Timing ....................................................21
Read/Write Cycle Timing ...........................................22
ZZ Mode Timing ........................................................23
Ordering Information ......................................................24
Ordering Code Definitions .........................................24
Package Diagram ..........................................................25
Acronyms ........................................................................26
Document Conventions .................................................26
Units of Measure .......................................................26
Document History Page .................................................27
Sales, Solutions, and Legal Information ......................28
Worldwide Sales and Design Support .......................28
Products ....................................................................28
PSoC Solutions .........................................................28
Document Number: 38-05352 Rev. *G
Page 3 of 28
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CY7C1444AV33
CY7C1445AV33
Selection Guide
250 MHz
2.6
200 MHz
3.2
167 MHz
3.4
Unit
ns
Maximum access time
Maximum operating current
Maximum CMOS standby current
475
425
375
mA
mA
120
120
120
Pin Configurations
100-pin TQFP Pinout
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
NC
14
VDD
NC
VSS
NC
VDD
ZZ
15
CY7C1445AV33
(2 M × 18)
CY7C1444AV33
(1 M × 36)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
ZZ
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
Document Number: 38-05352 Rev. *G
Page 4 of 28
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CY7C1444AV33
CY7C1445AV33
Pin Configurations (continued)
165-ball FBGA (15 × 17 × 1.4 mm) Pinout
CY7C1444AV33 (1 M × 36)
1
2
A
3
4
5
6
7
8
9
10
A
11
NC
NC/288M
NC/144M
DQPC
A
B
C
D
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
OE
BWE
GW
VSS
VSS
ADV
ADSP
VDDQ
VDDQ
A
CE2
A
NC/576M
DQPB
DQB
NC
DQC
VDDQ
VDDQ
VSS
VDD
NC/1G
DQB
DQC
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
CY7C1445AV33 (2 M × 18)
1
2
A
3
4
5
NC
6
7
8
9
10
A
11
A
NC/288M
NC/144M
NC
A
B
C
D
BWB
NC
CE3
CLK
VSS
VSS
CE1
CE2
BWE
GW
VSS
VSS
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
A
BWA
VSS
VSS
A
NC/576M
DQPA
DQA
NC
VDDQ
VDDQ
VSS
VDD
VSS
NC/1G
NC
NC
DQB
VDD
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
‘VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
NC/72M
TDI
A1
A0
TDO
MODE
A
A
A
TMS
TCK
A
A
A
A
R
Document Number: 38-05352 Rev. *G
Page 5 of 28
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CY7C1444AV33
CY7C1445AV33
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:
A0 are fed to the two-bit counter.
.
BWA, BWB
BWC, BWD
Input-
synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
Input-
synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BWX and BWE).
BWE
CLK
CE1
Input-
synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
Input-
clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Input-
synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
sampled only when a new external address is loaded.
CE2
CE3
Input-
synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external
address is loaded.
Input-
synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE and CE to select/deselect the device.
Not connected for BGA. Where referenced,
1 2
CE is sampled only when a new
CE3 is assumed active throughout this document for BGA.
external address is loaded.
3
OE
Input-
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
Input-
synchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted,
it automatically increments the address in a burst cycle.
ADSP
Input-
synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1:
A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input-
synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1:
A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
ZZ
Input-
ZZ “sleep” input, active HIGH. Whenasserted HIGH places the device in a non-time-critical
asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW
or left floating. ZZ pin has an internal pull-down.
I/O-
synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory
DQs, DQPs
location specified by the addresses presented during the previous
clock rise of the read
cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins
behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
VDD
Power supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
Ground for the I/O circuitry.
VSSQ
VDDQ
MODE
I/O ground
I/O power supply Power supply for the I/O circuitry.
Input-
static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation. Mode pin has an internal pull-up.
Document Number: 38-05352 Rev. *G
Page 6 of 28
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CY7C1444AV33
CY7C1445AV33
Pin Definitions (continued)
Name
I/O
JTAGserialoutput Serialdata-outtotheJTAGcircuit. DeliversdataonthenegativeedgeofTCK. IftheJTAGfeature
synchronous is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages.
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Description
TDO
TDI
synchronous
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TMS
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
synchronous
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
NC
JTAG-
clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
–
–
No Connects. Not internally connected to the die.
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
No Connects. Not internally connected to the die. 72M, 144M, 288M, 576M and 1G are
address expansion pins are not internally connected to the die.
emerging from a deselected state to a selected state, its outputs
are always tri-stated during the first cycle of the access. After the
Functional Overview
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
The CY7C1444AV33/CY7C1445AV33 is
a
double-cycle
deselect part. Once the SRAM is deselected at clock rise by the
chip select and either ADSP or ADSC signals, its output will
tri-state immediately after the next clock rise.
The CY7C1444AV33/CY7C1445AV33 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486 processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip
select is asserted active. The address presented is loaded into
the address register and the address advancement logic while
being delivered to the memory core. The write signals (GW,
input. Accesses can
address strobe (ADSP)
be initiated with either the processor
or the controller address strobe (ADSC).
Address advancement through the burst sequence is controlled
by the ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
BWE, and
cycle.
) and ADV inputs are ignored during this first
BWX
Byte write operations are qualified with the byte write enable
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the
corresponding address location in the memory core. If GW is
HIGH, then the write operation is controlled by BWE and BWX
signals. The CY7C1444AV33/CY7C1445AV33 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the byte write enable input (BWE) with the
selected byte write input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
(BWE) and byte write select (BW ) inputs. A global write
enable
all four
X
(GW) overrides all byte write inputs and writes data to
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Synchronous chip selects CE1, CE2, CE3 and an asynchronous
output enable (OE) provide for easy bank selection and output
tri-state control.
is ignored if
is HIGH.
ADSP
CE1
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs is stored into
the address advancement logic and the address register while
being presented to the memory core. The corresponding data is
allowed to propagate to the input of the output registers. At the
rising edge of the next clock the data is allowed to propagate
through the output register and onto the data bus within tCO if OE
is active LOW. The only exception occurs when the SRAM is
Because the CY7C1444AV33/CY7C1445AV33 is a common I/O
device, the output enable (OE) must be deasserted HIGH before
presenting data to the DQinputs. Doing so will tri-state the output
drivers. As a safety precaution, DQ are automatically tri-stated
whenever a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
Document Number: 38-05352 Rev. *G
Page 7 of 28
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CY7C1444AV33
CY7C1445AV33
HIGH, (3) chip select is asserted active, and (4) the appropriate
combination of the write inputs (GW, BWE, and ) are
Sleep Mode
BWX
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CEs,
ADSP, and ADSC must remain inactive for the duration of tZZREC
asserted active to conduct a write to the desired byte(s). ADSC
triggered write accesses require a single clock cycle to complete.
The address presented is loaded into the address register and
the address advancement logic while being delivered to the
memory core. The ADV input is ignored during this cycle. If a
global write is conducted, the data presented to the DQX is
written into the corresponding address location in the memory
core. If a byte write is conducted, only the selected bytes are
written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
after the ZZ input returns LOW
.
Interleaved Burst Address Table
(MODE = Floating or V )
DD
Because the CY7C1444AV33/CY7C1445AV33 is a common I/O
device, the output enable (OE) must be deasserted HIGH before
presenting data to the DQX inputs. Doing so will tri-state the
output drivers. As a safety precaution, DQX are automatically
tri-stated whenever a write cycle is detected, regardless of the
state of OE.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Burst Sequences
The CY7C1444AV33/CY7C1445AV33 provides
a
two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input. Both read
and write burst operations are supported.
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Asserting ADV LOW at clock rise will automatically increment the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
Min
Max
Unit
mA
ns
IDDZZ
ZZ > VDD– 0.2 V
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
100
2tCYC
–
tZZS
–
2tCYC
–
tZZREC
tZZI
ZZ recovery time
ns
ZZ active to sleep current
ZZ inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
–
ns
tRZZI
0
ns
Document Number: 38-05352 Rev. *G
Page 8 of 28
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CY7C1444AV33
CY7C1445AV33
Truth Table[2, 3, 4, 5, 6, 7]
Operation
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Sleep mode, power-down
Read cycle, begin burst
Read cycle, begin burst
Write cycle, begin burst
Read cycle, begin burst
Read cycle, begin burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Write cycle, continue burst
Write cycle, continue burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Write cycle, suspend burst
Write cycle, suspend burst
None
None
H
L
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H Tri-state
L-H Tri-state
L-H Tri-state
L-H Tri-state
L-H Tri-state
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
X
Tri-state
Q
External
External
External
External
External
Next
L-H
L
L
L
H
X
L
L-H Tri-state
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L-H Tri-state
L-H
L-H Tri-state
L-H
L-H Tri-state
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-state
L-H
L-H Tri-state
Q
H
X
X
L-H
L-H
D
D
L
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE , CE , and CE are available only in the TQFP package. BGA package has only 2 chip selects CE and CE .
1
2
3
1
2
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
X
after the ADSP or with the assertion of
. As a result,
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
OE
ADSC
don't care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05352 Rev. *G
Page 9 of 28
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CY7C1444AV33
CY7C1445AV33
Partial Truth Table for Read/Write[8, 9]
Function (CY7C1444AV33)
Read
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
X
H
H
L
BWA
X
H
L
Read
Write byte A – (DQA and DQPA)
Write byte B – (DQB and DQPB)
Write bytes B, A
L
L
H
L
L
L
Write byte C – (DQC and DQPC)
Write bytes C, A
L
H
H
L
H
L
L
L
Write bytes C, B
L
L
H
L
Write bytes C, B, A
Write byte D – (DQD and DQPD)
Write bytes D, A
L
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
Write bytes D, B
L
L
H
L
Write bytes D, B, A
Write bytes D, C
L
L
L
L
L
H
H
L
H
L
Write bytes D, C, A
Write bytes D, C, B
Write all bytes
L
L
L
L
L
L
H
L
L
L
L
L
Write all bytes
X
X
X
X
X
Truth Table for Read/Write[8, 9]
GW
H
BWE
BWB
BWA
X
Function (CY7C1445AV33)
Read
H
L
L
L
L
X
X
H
H
L
Read
H
H
Write byte A – (DQA and DQPA)
Write byte B – (DQB and DQPB)
Write all bytes
H
L
H
H
H
L
L
Write all bytes
L
X
X
Notes
8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
9. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.
X
Document Number: 38-05352 Rev. *G
Page 10 of 28
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CY7C1444AV33
CY7C1445AV33
Test Data-In (TDI)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register. (See TAP Controller Block Diagram.)
The CY7C1444AV33/CY7C1445AV33 incorporates a serial
boundary scan test access port (TAP). This part is fully compliant
with the 1149.1 IEEE Standard 1149.1. The TAP operates using
JEDEC-standard 3.3 V or 2.5 V I/O logic levels.
The CY7C1444AV33/CY7C1445AV33 contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
Test Data-Out (TDO)
Disabling the JTAG Feature
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See TAP Controller State Diagram.)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in a
reset state which will not interfere with the operation of the
device.
TAP Controller Block Diagram
0
Bypass Register
TAP Controller State Diagram
2
1
0
0
0
TEST-LOGIC
1
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
RESET
0
Selection
TDI
TDO
Circuitr
y
.
.
. 2 1
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
x
.
.
.
.
. 2 1
1
1
CAPTURE-DR
CAPTURE-IR
Boundary Scan Register
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
TCK
TMS
1
1
EXIT1-DR
EXIT1-IR
TAP CONTROLLER
0
0
PAUSE-DR
0
PAUSE-IR
0
1
1
Performing a TAP Reset
0
0
EXIT2-DR
1
EXIT2-IR
1
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
UPDATE-DR
UPDATE-IR
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
1
0
1
0
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Document Number: 38-05352 Rev. *G
Page 11 of 28
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CY7C1444AV33
CY7C1445AV33
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
SRAM with minimal delay. The bypass register is set LOW (VSS
)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in tran-
sition (metastable state). This will not harm the device, but there
is no guarantee as to the value that will be captured. Repeatable
results may not be possible.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK captured in the boundary scan
register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
EXTEST
IDCODE
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
The boundary scan register has a special bit located at bit# 89
(for 165-ball FBGA packages).When this scan cell, called the
Document Number: 38-05352 Rev. *G
Page 12 of 28
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CY7C1444AV33
CY7C1445AV33
“extest output bus tri-state”, is latched into the preload register
during the “Update-DR” state in the TAP controller, it will directly
control the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable the
output buffers to drive the output bus. When LOW, this bit will
place the output bus into a high Z condition.
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is preset
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range[10,11]
Parameter
Clock
tTCYC
tTF
Description
Min
Max
Unit
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
50
–
–
20
–
ns
MHz
ns
tTH
20
20
tTL
–
ns
Output Times
tTDOV TCK clock LOW to TDO valid
tTDOX TCK clock LOW to TDO invalid
Set-up Times
tTMSS TMS set-up to TCK clock rise
tTDIS
–
0
10
–
ns
ns
5
5
5
–
–
–
ns
ns
ns
TDI set-up to TCK clock rise
Capture set-up to TCK rise
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
Notes
10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document Number: 38-05352 Rev. *G
Page 13 of 28
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CY7C1444AV33
CY7C1445AV33
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels................................................VSS to 3.3 V
Input rise and fall times....................................................1 ns
Input timing reference levels.......................................... 1.5 V
Output reference levels ................................................. 1.5 V
Test load termination supply voltage ............................. 1.5 V
Input pulse levels................................................VSS to 2.5 V
Input rise and fall time .....................................................1 ns
Input timing reference levels........................................ 1.25 V
Output reference levels ............................................... 1.25 V
Test load termination supply voltage ............................ 1.25V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50
50
TDO
TDO
ZO= 50
ZO= 50
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)[12]
Parameter
VOH1
Description
Output HIGH voltage IOH = –4.0 mA, VDDQ = 3.3 V
OH = –1.0 mA, VDDQ = 2.5 V
Output HIGH voltage IOH = –100 µA VDDQ = 3.3 V
DDQ = 2.5 V
Test Conditions
Min
2.4
2.0
2.9
2.1
–
Max
Unit
V
–
I
–
V
VOH2
VOL1
VOL2
VIH
–
V
V
–
0.4
V
Output LOW voltage IOL = 8.0 mA, VDDQ = 3.3 V
IOL = 1.0 mA, VDDQ = 2.5 V
V
–
0.4
V
Output LOW voltage IOL = 100 µA
VDDQ = 3.3 V
DDQ = 2.5 V
–
0.2
V
V
–
0.2
V
Input HIGH voltage
Input LOW voltage
Input load current
VDDQ = 3.3 V
DDQ = 2.5 V
VDDQ = 3.3 V
DDQ = 2.5 V
GND < VIN < VDDQ
2.0
1.7
–0.5
–0.3
–5
VDD + 0.3
VDD + 0.3
0.7
V
V
V
VIL
V
V
0.7
V
IX
5
µA
Note
12. All voltages referenced to V (GND).
SS
Document Number: 38-05352 Rev. *G
Page 14 of 28
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CY7C1444AV33
CY7C1445AV33
Identification Register Definitions
Instruction Field
CY7C1444AV33
CY7C1445AV33
000
Description
Revision number (31:29)
Device depth (28:24)[13]
000
01011
Describes the version number.
01011
Reserved for Internal Use
Architecture/memory type (23:18)
Bus width/density(17:12)
000110
100111
00000110100
1
000110
010111
Defines memory type and architecture
Defines width and density
Cypress JEDEC ID code (11:1)
ID register presence indicator (0)
00000110100
1
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 18)
Bit Size (× 36)
Instruction
Bypass
ID
3
1
3
1
32
89
32
89
Boundary scan order (165-ball FBGA package)
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
13. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05352 Rev. *G
Page 15 of 28
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CY7C1444AV33
CY7C1445AV33
165-ball FBGA Boundary Scan Order[14,15]
CY7C1444AV33 (1 M × 36), CY7C1445AV33 (2 M × 18)
Bit #
1
Ball ID
Bit #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ball ID
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
Bit #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
Bit #
Ball ID
N1
76
77
78
79
80
81
82
83
84
85
86
87
88
89
N6
N7
N10
P11
P8
2
N2
3
P1
4
R1
5
R2
6
R8
P3
7
R9
R3
8
P9
P2
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
R4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P4
G1
D2
E2
F2
N5
P6
B9
R6
C10
A8
Internal
G2
H1
H3
J1
B8
A7
B7
B6
K1
L1
A6
M1
J2
B5
A5
A4
B4
B3
H10
G11
F11
K2
L2
M2
Notes
14. Balls which are NC (No Connect) are pre-set LOW.
15. Bit# 89 is pre-set HIGH.
Document Number: 38-05352 Rev. *G
Page 16 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
DC input voltage.................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ......................................... 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, method 3015)
Storage temperature ................................ –65 °C to +150 °C
Latch-up current .................................................... > 200 mA
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Operating Range
Supply voltage on VDD relative to GND........–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD
Ambient
Range
VDD
VDDQ
Temperature
DC voltage applied to outputs
in tri-state...........................................–0.5 V to VDDQ + 0.5 V
Commercial 0 °C to +70 °C
3.3 V– 5% / 2.5 V – 5%
+ 10%
to VDD
Industrial
–40 °C to +85 °C
Electrical Characteristics
Over the Operating Range [16, 17]
Parameter
VDD
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
Max
3.6
VDD
2.625
–
Unit
V
3.135
3.135
2.375
2.4
VDDQ
for 3.3 V I/O
for 2.5V I/O
V
V
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
for 3.3 V I/O, IOH =4.0 mA
for 2.5 V I/O,I OH =1.0 mA
for 3.3 V I/O, IOL =8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
V
2.0
–
V
–
0.4
0.4
V
–
V
Input HIGH voltage[16] for 3.3 V I/O
2.0
VDD + 0.3V
V
V
for 2.5 V I/O
1.7
VDD + 0.3V
Input LOW voltage[16]
for 3.3 V I/O
–0.3
–0.3
–5
0.8
0.7
5
V
for 2.5 V I/O
V
Input leakage current
except ZZ and MODE
GND VI VDDQ
µA
Input current of MODE Input = VSS
Input = VDD
–30
–
–
5
µA
µA
Input current of ZZ
Input = VSS
Input = VDD
–5
–
–
µA
30
5
µA
IOZ
IDD
Output leakage current GND VI VDDQ, output disabled
–5
–
µA
VDD operating supply
current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
All speeds
475
425
375
225
mA
mA
mA
mA
–
–
ISB1
ISB2
ISB3
Automatic CE
VDD = Max, device deselected,
–
power-down
current—TTL inputs
VIN VIH or VIN VIL
f = fMAX = 1/tCYC
Automatic CE
power-down
current—CMOS inputs f = 0
VDD = Max, device deselected,
VIN 0.3V or VIN > VDDQ – 0.3 V,
All speeds
–
–
–
120
200
135
mA
mA
mA
Automatic CE
power-down
current—CMOS inputs f = fMAX = 1/tCYC
VDD = Max, device deselected, or All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V
ISB4
Automatic CE
VDD = Max, device deselected,
All speeds
power-down
current—TTL inputs
VIN VIH or VIN VIL,
f = 0
Notes
16. Overshoot: V (AC) < V + 1.5 V (Pulse width less than t
/2), undershoot: V (AC) > –2 V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
17. T
: Assumes a linear ramp from 0 V to V (min) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document Number: 38-05352 Rev. *G
Page 17 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Capacitance[18]
100 TQFP
Max
165 FBGA
Parameter
Description
Test Conditions
Unit
Max
CIN
Input capacitance
TA = 25 C, f = 1 MHz,
6.5
3
7
7
6
pF
pF
pF
V
DD = 3.3 V
CCLK
CI/O
Clock input capacitance
Input/output capacitance
VDDQ = 2.5 V
5.5
Thermal Resistance[18]
100 TQFP
Package
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.
25.21
20.8
C/W
JC
Thermal resistance
(junction to case)
2.28
3.2
C/W
AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
10%
L
GND
5 pF
R = 351
1 ns
1 ns
V = 1.5 V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
2.5 V I/O Test Load
(b)
R = 1667
2.5 V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50
0
R = 50
10%
L
5 pF
R = 1538
1 ns
1 ns
V = 1.25 V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note
18. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05352 Rev. *G
Page 18 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Switching Characteristics
Over the Operating Range[19, 20]
–250
–200
–167
Description
Unit
Parameter
tPOWER
Clock
tCYC
Min
Max
Min
Max
Min
Max
VDD(Typical) to the first access[21]
1
–
1
–
1
–
ms
Clock cycle time
Clock HIGH
4.0
1.5
1.5
–
–
–
5
–
–
–
6
–
–
–
ns
ns
ns
tCH
2.0
2.0
2.4
2.4
tCL
Clock LOW
Output Times
tCO
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z[22, 23, 24]
–
1.0
1.0
–
2.6
–
–
1.5
1.3
–
3.2
–
–
1.5
1.5
–
3.4
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
–
–
tCHZ
Clock to high Z[22, 23, 24]
2.6
2.6
–
3.0
3.0
–
3.4
3.4
–
tOEV
OE LOW to output valid
–
–
–
[22, 23, 24]
tOELZ
tOEHZ
Set-up Times
tAS
OE
0
0
0
LOW to output low Z
OE HIGH to output high Z[22, 23, 24]
–
2.6
–
3.0
–
3.4
Address set-up before CLK rise
ADSC, ADSP set-up before CLK rise
ADV set-up before CLK rise
1.2
1.2
1.2
1.2
1.2
1.2
–
–
–
–
–
–
1.4
1.4
1.4
1.4
1.4
1.4
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX set-up before CLK rise
Data input set-up before CLK rise
Chip enable set-up before CLK rise
tDS
tCES
Hold Times
tAH
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
ADV hold after CLK rise
0.3
0.3
0.3
0.3
0.3
0.3
–
–
–
–
–
–
0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
tADVH
tWEH
GW, BWE, BWX hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
tDH
tCEH
Notes
19. Timing reference level is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
21. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation
POWER
DD
can be initiated.
22. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
23. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
24. This parameter is sampled and not 100% tested.
Document Number: 38-05352 Rev. *G
Page 19 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Switching Waveforms
]
Read Cycle Timing[25
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,BWX
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
OEV
CO
t
t
CHZ
t
t
t
OELZ
OEHZ
DOH
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Q(A1)
Data Out (DQ)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
25. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document Number: 38-05352 Rev. *G
Page 20 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Switching Waveforms
Write Cycle Timing[26, 27]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
BWE,
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
Data in (D)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
DON’T CARE
Single WRITE
Extended BURST WRITE
UNDEFINED
Notes
26. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
27.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document Number: 38-05352 Rev. *G
Page 21 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Switching Waveforms
Read/Write Cycle Timing[28, 29, 30]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Back-to-Back READs
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
BURST READ
Back-to-Back
WRITEs
Single WRITE
DON’T CARE
UNDEFINED
Notes
28. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
29. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
30. GW is HIGH.
Document Number: 38-05352 Rev. *G
Page 22 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Switching Waveforms
ZZ Mode Timing[31, 32]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
31. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
32. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05352 Rev. *G
Page 23 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only
the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com
and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress
maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at t http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
167 CY7C1444AV33-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY7C 1444 A V33 - 167 AX
C
Temperature range:
C = Commercial
Package Type:
AX = 100-pin TQFP (Pb-free)
Speed Grade (167 MHz)
V33 = 3.3 V
Process Technology 90 nm
1444 = DCD, 1 Mb × 36 (36 Mb)
CY7C = Cypress SRAMs
Document Number: 38-05352 Rev. *G
Page 24 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Package Diagram
51-85050 *C
Document Number: 38-05352 Rev. *G
Page 25 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Acronyms
Document Conventions
Units of Measure
Acronym
CE
Description
chip enable
clock enable
Symbol
ns
Unit of Measure
CEN
FPBGA
I/O
nano seconds
Volts
fine-pitch ball grid array
input/output
V
µA
mA
ms
MHz
pF
W
micro Amperes
milli Amperes
milli seconds
Mega Hertz
pico Farad
Watts
JTAG
NoBL
OE
Joint Test Action Group
No Bus Latency
output enable
SRAM
TCK
static random access memory
test clock
TMS
TDI
test mode select
test data-in
°C
degree Celcius
TDO
TQFP
WE
test data-out
thin quad flat pack
write enable
Document Number: 38-05352 Rev. *G
Page 26 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Document History Page
Document Title: CY7C1444AV33/CY7C1445AV33 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM
Document Number: 38-05352
Submission
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
124419
254910
03/04/03
See ECN
CGM
SYT
New data sheet
*A
Part number changed from previous revision. New and old part number
differ by the letter “A”
Modified Functional Block diagrams
Modified switching waveforms
Added boundary scan information
Added footnote #13 (32-Bit Vendor I.D Code changed)
Added IDD, IX and ISB values in DC Electrical Characteristics
Added tPOWER specifications in Switching Characteristics table
Removed 119 PBGA package
Changed 165 FBGA package from BB165 (15 x 17 x 1.20 mm) to
BB165C
(15 x 17 x 1.40 mm)
*B
303533
See ECN
SYT
Changed the test condition from VDD = Min. to VDD = Max for VOL in the
Electrical Characteristics table
Replaced JA and JC from TBD to respective Thermal Values for All
Packages on the Thermal Resistance Table
Changed IDD from 450, 400 & 350 mA to 475, 425 & 375 mA for 250,
200 and 167 Mhz respectively
Changed ISB1 from 190, 180 and 170 mA to 225 mA for 250, 200 and
167 Mhz respectively
Changed ISB2 from 80 mA to 100 mA for all frequencies
Changed ISB3 from 180, 170 & 160 mA to 200 mA for 250, 200 and 167
MHz respectively
Changed ISB4 from 100 mA to 110 mA for all frequencies
Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for
TQFP Package
Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200
MHz Speed Bin
Added lead-free information for 100-pin TQFP and 165 FBGA packages
*C
331778
See ECN
SYT
Modified Address Expansion balls in the pinouts for 165 FBGA Package
as per JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165
FBGA Package
Added Industrial Temperature Grades
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respec-
tively
Updated the Ordering Information by Shading and Unshading MPNs as
per availability
*D
417509
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1
from “3901 North First Street” to “198 Champion Court”
Changed IX current value in MODE from –5 & 30 A to –30 & 5 A
respectively and also Changed IX current value in ZZ from –30 & 5 A
to –5 & 30 A respectively on page# 16
Modified test condition from VIH < VDD to VIH VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE”
in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the
Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Document Number: 38-05352 Rev. *G
Page 27 of 28
[+] Feedback
CY7C1444AV33
CY7C1445AV33
Document Title: CY7C1444AV33/CY7C1445AV33 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM
Document Number: 38-05352
Submission
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
*E
473229
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to
GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in
TAP AC Switching Characteristics table
Updated the Ordering Information table.
*F
2898663
3042209
03/24/2010
09/29/2010
NJY
NJY
Removed inactive parts from Ordering Information table. Updated
package diagram.
*G
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
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cypress.com/go/interface
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Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
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Memory
cypress.com/go/memory
cypress.com/go/image
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PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2003-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05352 Rev. *G
Revised September 29, 2010
Page 28 of 28
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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