CY7C146-15JCT [CYPRESS]
Dual-Port SRAM, 2KX8, 15ns, CMOS, PQCC52, PLASTIC, LCC-52;
| 型号： | CY7C146-15JCT |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 2KX8, 15ns, CMOS, PQCC52, PLASTIC, LCC-52 静态存储器 内存集成电路 |
| 文件： | 总15页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
2K x 8 Dual-Port Static RAM
Features
Functional Description
■ True dual-ported memory cells that enable simultaneous reads
of the same memory location
The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146
are high speed CMOS 2K x 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
memory. The CY7C132, CY7C136, and CY7C136A can be used
as either a standalone 8-bit dual-port static RAM or as a
MASTER dual-port RAM, in conjunction with the
CY7C142/CY7C146 SLAVE dual-port device. They are used in
systems that require 16-bit or greater word widths. This is the
solution to applications that require shared or buffered data, such
as cache memory for DSP, bit-slice, or multiprocessor designs.
■ 2K x 8 organization
■ 0.65 micron CMOS for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: ICC = 110 mA (maximum)
■ Fully asynchronous operation
■ Automatic power down
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). BUSY flags are provided
on each port. In addition, an interrupt flag (INT) is provided on
each port of the 52-pin PLCC version. BUSY signals that the port
is trying to access the same location currently being accessed
by the other port. On the PLCC version, INT is an interrupt flag
indicating that data is placed in an unique location (7FF for the
left port and 7FE for the right port).
■ MasterCY7C132/CY7C136/CY7C136A[1] easilyexpandsdata
bus width to 16 or more bits using slave CY7C142/CY7C146
■ BUSY output flag on CY7C132/CY7C136/CY7C136A;
BUSY input on CY7C142/CY7C146
■ INT flag for port to port communication (52-Pin PLCC/PQFP
versions)
An automatic power down feature is controlled independently on
each port by the chip enable (CE) pins.
■ CY7C136, CY7C136A, and CY7C146 available in 52-pin
PLCC and 52-pin PQFP packages
■ Pb-free packages available
Logic Block Diagram
R/W
L
R/W
R
CE
L
CE
R
OE
L
OE
R
I/O
I/O
I/O
I/O
7L
7R
I/O
CONTROL
I/O
CONTROL
0R
0L
[2]
[2]
BUSY
BUSY
R
L
A
A
A
10L
10R
0R
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
A
0L
ARBITRATION
LOGIC
(7C132/7C136 ONLY)
AND
INTERRUPTLOGIC
CE
L
CE
R
(7C136/7C146ONLY)
OE
L
OE
R
R/W
R/W
R
L
[3]
[3]
INT
L
INT
R
Notes
1. CY7C136 and CY7C136A are functionally identical.
2. CY7C132/CY7C136/CY7C136A (Master): BUSY is open drain output and requires pull up resistor. CY7C142/CY7C146 (Slave): BUSY is input.
3. Open drain outputs; pull up resistor required.
Cypress Semiconductor Corporation
Document #: 38-06031 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 24, 2009
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Pinouts
Figure 1. 52-Pin PLCC (Top View)
Figure 2. 52-Pin PQFP (Top View)
7
6
5
4
3
2
1
52 51 50 49 48 47
46
52 51 50 49 48 47 46 45 44 43 42 41 40
OE
A
A
OE
A
A
A
A
A
A
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
8
R
1L
2L
3L
4L
5L
6L
1
39
38
37
36
35
34
33
32
31
30
29
28
27
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
A
A
A
A
A
9
45
44
43
42
41
40
39
38
37
36
35
34
2
0R
A
10
11
12
13
14
15
16
17
18
19
20
3
1R
A
4
2R
3R
4R
5R
A
5
A
6
7C136/7C136A
7C146
7C136/7C136A
7C146
A
A
A
A
7L
8L
7
A
A
6R
A
7R
A
8R
A
9R
A
6R
A
7R
A
8R
A
9R
8
A
9L
0L
1L
9
I/O
I/O
I/O
I/O
10
11
12
13
I/O
I/O
I/O
I/O
NC
I/O
2L
NC
I/O
2L
3L
3L
7R
7R
2122 23 24 25 26 27 28 29 30 31 32 33
1415 16 17 18 19 20 21 22 23 24 25 26
Selection Guide
7C132-55
7C136-55
7C132-25 [4] 7C132-30 7C132-35 7C132-45
7C136-15[4]
7C146-15
7C136-25
7C142-25
7C146-25
7C136-30 7C136-35 7C136-45
7C142-30 7C142-35 7C142-45
7C146-30 7C146-35 7C146-45
Specification
7C136A-55 Unit
7C142-55
7C146-55
Maximum Access Time
15
190
75
25
170
65
30
170
65
35
120
45
45
120
45
55
110
35
ns
Maximum Operating Current Com’l/Ind
mA
mA
Maximum Standby Current Com’l/Ind
Shaded areas contain preliminary information.
Note:
4. 15 ns and 25 ns version available in PQFP and PLCC packages only.
Document #: 38-06031 Rev. *E
Page 2 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
DC Input Voltage.................................................−3.5V to +7.0V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Latch up Current.................................................... >200mA
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
Supply Voltage to Ground Potential
(Pin 48 to Pin 24).................................................−0.5V to +7.0V
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +7.0V
–40°C to +85°C
Electrical Characteristics
Over the Operating Range
7C132-55
7C132-30[4] 7C132-35,45
7C136-55
7C136A-55
7C142-55
7C146-55
7C136-15[4] 7C136-25, 30 7C136-35,45
7C146-15
7C142-30
7C142-35,45
Parameter
Description
Test Conditions
Unit
7C146-25, 30 7C146-35,45
Min Max Min Max Min Max Min Max
VOH
Output HIGH
voltage
VCC = Min., IOH = –4.0 mA
2.4
2.2
2.4
2.2
2.4
2.2
2.4
V
V
VOL
Output LOW
voltage
IOL = 4.0 mA
IOL = 16.0 mA[5]
0.4
0.5
0.4
0.5
0.4
0.5
0.4
0.5
VIH
VIL
Input HIGH
voltage
2.2
V
V
Input LOW
voltage
0.8
0.8
0.8
0.8
IIX
Input load current GND < VI < VCC
–5
–5
+5
+5
−5
−5
+5
+5
−5
−5
+5
+5
−5
−5
+5
+5
μA
μA
IOZ
Output leakage GND < VO < VCC, Output Disabled
current
IOS
ICC
ISB1
Output short
VCC = Max., VOUT = GND
–350
190
−350
−350
−350 mA
circuit current[6]
VCC Operating
Supply Current
CE = VIL, Outputs Open,
Com’l/
Ind’l
170
120
110 mA
[7]
f = fMAX
Standby current CEL and CER > VIH,
Com’l/
Ind’l
75
65
45
90
35
75
mA
mA
[7]
both ports, TTL
f = fMAX
Inputs
ISB2
Standby Current CEL or CER > VIH,
One Port,
TTL Inputs
Com’l/
Ind’l
135
115
Active Port Outputs Open,
[7]
f = fMAX
ISB3
Standby Current Both Ports CEL and
Com’l/
Ind’l
15
15
15
85
15
70
mA
mA
Both Ports,
CMOS Inputs
CER > VCC – 0.2V, VIN > VCC – 0.2V
or VIN < 0.2V, f = 0
ISB4
Standby Current One Port CEL or CER > VCC – 0.2V, Com’l/
125
105
One Port,
CMOS Inputs
Ind’l
VIN > VCC – 0.2V or VIN < 0.2V,
Active Port Outputs Open, f = fMAX
[7]
Shaded areas contain preliminary information.
Notes
5. BUSY and INT pins only.
6. Duration of the short circuit should not exceed 30 seconds.
7. At f = f
, address and data inputs are cycling at the maximum frequency of read cycle of 1/t and using AC Test Waveforms input levels of GND to 3V.
MAX
rc
Document #: 38-06031 Rev. *E
Page 3 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Capacitance
This parameter is guaranteed but not tested.
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
15
Unit
pF
CIN
TA = 25°C, f = 1 MHz, VCC = 5.0V
COUT
10
pF
Figure 3. AC Test Loads and Waveforms
5V
R1 893Ω
R1 893Ω
5V
5V
OUTPUT
OUTPUT
281Ω
BUSY
OR
INT
R2
347Ω
R2
347Ω
30 pF
5 pF
30 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
BUSY Output Load
(CY7C132/CY7C136 Only)
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
ALL INPUT PULSES
3.0V
90%
10%
90%
250Ω
10%
OUTPUT
1.4V
GND
< 5 ns
< 5 ns
Switching Characteristics
Over the Operating Range (Speeds -15, -25, -30) [8]
7C132-25 [4]
7C136-25
7C142-25
7C146-25
7C132-30
7C136-15 [4]
7C146-15
7C136-30
7C142-30
7C146-30
Parameter
Description
Unit
Min
Max
Min
Max
Min
Max
Read Cycle
tRC
Read Cycle Time
15
0
25
0
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid [9]
Data Hold from Address Change
CE LOW to Data Valid [9]
OE LOW to Data Valid [9]
OE LOW to Low Z [7, 10]
OE HIGH to High Z [7, 10, 11]
CE LOW to Low Z [7, 10]
CE HIGH to High Z [7, 10, 11]
CE LOW to Power Up [7]
CE HIGH to Power Down [7]
15
25
30
tOHA
tACE
15
10
25
15
30
20
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
0
3
5
0
3
5
0
10
10
15
15
15
25
15
15
25
tPD
Shaded areas contain preliminary information.
Notes
8. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified I /I
OL OH,
and 30 pF load capacitance.
9. AC test conditions use V = 1.6V and V = 1.4V.
OH
OL
10. At any given temperature and voltage condition for any given device, t
is less than t
and t
is less than t
.
LZOE
HZCE
LZCE
HZOE
11. t
, t
, t
, t
t
and t
are tested with C = 5pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 500 mV from steady state
LZCE LZWE HZOE LZOE, HZCE,
HZWE
L
voltage.
Document #: 38-06031 Rev. *E
Page 4 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Characteristics
Over the Operating Range (Speeds -15, -25, -30) [8] (continued)
7C132-25 [4]
7C136-25
7C142-25
7C146-25
7C132-30
7C136-30
7C142-30
7C146-30
7C136-15 [4]
7C146-15
Parameter
Description
Unit
Min
Max
Min
Max
Min
Max
Write Cycle[12]
tWC
Write Cycle Time
15
12
12
2
25
20
20
2
30
25
25
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
R/W Pulse Width
tHA
tSA
0
0
0
tPWE
tSD
12
10
0
15
15
0
25
15
0
Data Setup to Write End
Data Hold from Write End
R/W LOW to High Z [7]
R/W HIGH to Low Z [7]
tHD
tHZWE
tLZWE
10
15
15
0
0
0
Busy/Interrupt Timing
tBLA
tBHA
tBLC
tBHC
tPS
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch[13]
15
15
15
15
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH[13]
Port Set Up for Priority
R/W LOW after BUSY LOW[14]
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
5
0
5
0
5
0
tWB
tWH
13
20
30
tBDD
tDDD
tWDD
15
25
30
Write Data Valid to Read Data Valid
Note 15
Note 15
Note 15
Note 15
Note 15
Note 15
Write Pulse to Data Delay
Interrupt Timing [16]
tWINS
tEINS
tINS
R/W to INTERRUPT Set Time
15
15
15
15
15
15
25
25
25
25
25
25
25
25
25
25
25
25
ns
ns
ns
ns
ns
ns
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time[13]
CE to INTERRUPT Reset Time[13]
Address to INTERRUPT Reset Time[13]
tOINR
tEINR
tINR
Shaded areas contain preliminary information.
Notes
12. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
13. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.
14. CY7C142/CY7C146 only.
15. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
16. 52-pin PLCC and PQFP versions only.
Document #: 38-06031 Rev. *E
Page 5 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Characteristics
Over the Operating Range (Speeds -35, -45, -55) [8]
7C132-55
7C132-45
7C132-35
7C136-35
7C142-35
7C146-35
7C136-55
7C136-45
7C136A-55
7C142-45
Parameter
Description
Unit
7C142-55
7C146-55
7C146-45
Min
Max
Min
Max
Min
Max
Read Cycle
tRC
Read Cycle Time
35
0
45
0
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid[9]
Data Hold from Address Change
CE LOW to Data Valid[9]
OE LOW to Data Valid[9]
OE LOW to Low Z[7, 10]
OE HIGH to High Z[7, 10, 11]
CE LOW to Low Z[7, 10]
CE HIGH to High Z[7, 10, 11]
CE LOW to Power Up[7]
CE HIGH to Power Down[7]
35
45
55
tOHA
tACE
35
20
45
25
55
25
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
5
0
3
5
0
3
5
0
20
20
35
20
20
35
25
25
35
tPD
Write Cycle[12]
tWC
Write Cycle Time
35
30
30
2
45
35
35
2
55
40
40
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
R/W Pulse Width
tAW
tHA
tSA
0
0
0
tPWE
tSD
25
15
0
30
20
0
30
20
0
Data Setup to Write End
Data Hold from Write End
R/W LOW to High Z [7]
R/W HIGH to Low Z [7]
tHD
tHZWE
tLZWE
20
20
25
0
0
0
Busy/Interrupt Timing
tBLA
tBHA
tBLC
tBHC
tPS
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch[13]
20
20
20
20
25
25
25
25
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH[13]
Port Set Up for Priority
R/W LOW after BUSY LOW[14]
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
5
0
5
0
5
0
tWB
tWH
30
35
35
tBDD
tDDD
tWDD
35
45
45
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
Note 15
Note 15
Note 15
Note 15
Note 15
Note 15
Document #: 38-06031 Rev. *E
Page 6 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Characteristics
Over the Operating Range (Speeds -35, -45, -55) [8] (continued)
7C132-55
7C132-45
7C132-35
7C136-35
7C142-35
7C146-35
7C136-55
7C136-45
7C136A-55
7C142-45
Parameter
Description
Unit
7C142-55
7C146-55
7C146-45
Min
Max
Min
Max
Min
Max
Interrupt Timing [16]
tWINS
tEINS
tINS
R/W to INTERRUPT Set Time
25
25
25
25
25
25
35
35
35
35
35
35
45
45
45
45
45
45
ns
ns
ns
ns
ns
ns
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time[13]
CE to INTERRUPT Reset Time[13]
Address to INTERRUPT Reset Time[13]
tOINR
tEINR
tINR
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port-Address Access) [17, 18]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (Either Port-CE/OE )[17, 19]
CE
OE
t
HZCE
t
ACE
t
HZOE
t
DOE
t
LZOE
t
LZCE
DATA VALID
DATA OUT
t
PU
t
PD
I
CC
I
SB
Notes
17. R/W is HIGH for read cycle.
18. Device is continuously selected, CE = V and OE = V .
IL
IL
19. Address valid prior to or coincident with CE transition LOW.
Document #: 38-06031 Rev. *E
Page 7 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Waveforms (continued)
Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A)
t
RC
ADDRESSR
R/WR
ADDRESS MATCH
t
PWE
DINR
VALID
t
PS
ADDRESS MATCH
ADDRESSL
BUSYL
t
BHA
t
t
BDD
BLA
DOUTL
VALID
t
DDD
t
WDD
Figure 7. Write Cycle No.1 (OE Three-States Data I/Os—Either Port) [12, 20]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATAIN
OE
DATA VALID
t
HZOE
HIGH IMPEDANCE
DOUT
Note
20. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or t
+ t to allow the data I/O pins to enter high impedance
PWE
HZWE SD
and for data to be placed on the bus for the required t
.
SD
Document #: 38-06031 Rev. *E
Page 8 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Waveforms (continued)
Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[12, 21]
t
WC
ADDRESS
CE
t
t
HA
SCE
t
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATAIN
DATA VALID
t
t
LZWE
HZWE
HIGH IMPEDANCE
DOUT
Figure 9. Busy Timing Diagram No. 1 (CE Arbitration)
CEL Valid First:
ADDRESSL,R
ADDRESS MATCH
CEL
CER
t
PS
t
t
BHC
BLC
BUSYR
CER Valid First:
ADDRESSL,R
CER
ADDRESS MATCH
t
PS
CEL
t
t
BHC
BLC
BUSYL
Note
21. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state.
Document #: 38-06031 Rev. *E
Page 9 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Waveforms (continued)
Figure 10. Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
t
or t
WC
RC
ADDRESSL
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESSR
t
t
BHA
BLA
BUSYR
Right Address Valid First:
t
or t
WC
RC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESSL
BUSYL
t
t
BHA
BLA
Figure 11. Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)
CE
t
PWE
R/W
t
t
WH
WB
BUSY
Document #: 38-06031 Rev. *E
Page 10 of 15
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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Waveforms (continued)
Interrupt Timing Diagrams [16]
Figure 12. Left Side Sets INTR
t
WC
ADDRESSL
WRITE 7FF
t
t
HA
INS
CEL
t
EINS
R/WL
t
SA
t
WINS
INTR
Figure 13. Right Side Clears INTR
t
RC
ADDRESSR
CER
READ 7FF
t
t
INR
HA
t
EINR
R/WR
OER
INTR
t
OINR
Figure 14. Right Side Sets INTL
t
WC
ADDRESSR
CER
WRITE 7FE
t
t
HA
INS
t
EINS
R/WR
INTL
t
SA
t
WINS
Figure 15. Right Side Clears INTL
t
RC
ADDRESSL
CEL
READ 7FE
t
t
INR
HA
t
EINR
R/WL
OEL
t
OINR
INTL
Document #: 38-06031 Rev. *E
Page 11 of 15
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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Figure 16. Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.0
0.8
1.2
1.0
I
CC
I
CC
0.8
0.6
0.4
60
V
= 5.0V
= 25°C
CC
V
V
= 5.0V
CC
= 5.0V
0.6
0.4
T
A
IN
40
0.2
0.6
20
0
I
I
SB3
0.2
0.0
SB3
–55
25
125
0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
1.1
100
80
1.2
1.0
60
T
= 25°C
5.5
A
V
= 5.0V
1.0
CC
40
0.8
V
= 5.0V
= 25°C
CC
20
0
0.9
0.8
T
A
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I vs. CYCLE TIME
CC
1.25
30.0
25.0
3.0
2.5
V
A
V
= 5.0V
CC
T
= 25°C
= 0.5V
IN
1.0
2.0
20.0
15.0
10.0
1.5
1.0
0.75
V
= 4.5V
= 25°C
CC
0.5
0.0
5.0
0
T
A
0.50
10
20
30
40
0
1.0
2.0
3.0
4.0 5.0
0
200 400 600 800 1000
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
SUPPLY VOLTAGE (V)
Document #: 38-06031 Rev. *E
Page 12 of 15
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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Ordering Code
Package Type
Range
15
CY7C136-15JC
CY7C136-15NC
CY7C136-25JC
CY7C136-25JXC
CY7C136-25NC
CY7C136-25NXC
CY7C136-25JXI
CY7C136-30JC
CY7C136-30NC
CY7C136-30JI
CY7C136-35JC
CY7C136-35NC
CY7C136-35JI
CY7C136-45JC
CY7C136-45NC
CY7C136-45JI
CY7C136-55JC
CY7C136-55JXC
CY7C136-55NC
CY7C136-55NXC
CY7C136-55JI
CY7C136A-55JXI
CY7C136-55NI
CY7C136A-55NXI
CY7C146-15JC
CY7C146-15NC
CY7C146-25JC
CY7C146-25JXC
CY7C146-25NC
CY7C146-30JC
CY7C146-30NC
CY7C146-30JI
CY7C146-35JC
CY7C146-35NC
CY7C146-35JI
CY7C146-45JC
CY7C146-45NC
CY7C146-45JI
CY7C146-55JC
CY7C146-55JXC
CY7C146-55NC
CY7C146-55JI
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85042 52-Pin Plastic Quad Flatpack
51-85004 52-Pin Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier (Pb-Free)
51-85042 52-Pin Plastic Quad Flatpack
52-Pin Plastic Quad Flatpack (Pb-Free)
Commercial
25
Commercial
51-85004 52-Pin Plastic Leaded Chip Carrier (Pb-Free)
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85042 52-Pin Plastic Quad Flatpack
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85042 52-Pin Plastic Quad Flatpack
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85042 52-Pin Plastic Quad Flatpack
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85004 52-Pin Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier (Pb-Free)
51-85042 52-Pin Plastic Quad Flatpack
52-Pin Plastic Quad Flatpack (Pb-Free)
Industrial
30
35
45
55
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
51-85004 52-Pin Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier (Pb-Free)
51-85042 52-Pin Plastic Quad Flatpack
52-Pin Plastic Quad Flatpack (Pb-Free)
Industrial
15
25
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85042 52-Pin Plastic Quad Flatpack
51-85004 52-Pin Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier (Pb-Free)
51-85042 52-Pin Plastic Quad Flatpack
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85042 52-Pin Plastic Quad Flatpack
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85042 52-Pin Plastic Quad Flatpack
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85042 52-Pin Plastic Quad Flatpack
51-85004 52-Pin Plastic Leaded Chip Carrier
51-85004 52-Pin Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier (Pb-Free)
51-85042 52-Pin Plastic Quad Flatpack
51-85004 52-Pin Plastic Leaded Chip Carrier
Commercial
Commercial
30
35
45
55
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Document #: 38-06031 Rev. *E
Page 13 of 15
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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Package Diagrams
Figure 17. 52-Pin Plastic Leaded Chip Carrier, 51-85004
51-85004-*A
Figure 18. 52-Pin Plastic Quad Flatpack, 51-85042
51-85042-**
Document #: 38-06031 Rev. *E
Page 14 of 15
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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Document History Page
Document Title: CY7C132, CY7C136, CY7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM
Document Number: 38-06031
Submission Orig. of
Revision
ECN
Description of Change
Change from Spec number: 38-06031
Date
Change
**
110171
128959
236748
393184
10/21/01
09/03/03
See ECN
See ECN
SZV
*A
*B
*C
JFU
Added CY7C136-55NI to Order Information
YDT
Removed cross information from features section
YIM
Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C136-25JXC, CY7C136-25NXC, CY7C136-55JXC, CY7C136-55NXC,
CY7C136-55JXI, CY7C136-55NXI, CY7C146-25JXC, CY7C146-55JXC
*D
*E
2623658
12/17/08 VKN/PYRS Added CY7C136-25JXI part
Removed CY7C132/142 from the Ordering information table
Removed 48-Pin DIP and 52-Pin Square LCC package from the data sheet
2678221 03/24/2009 VKN/AESA Added CY7C136A-55JXI, and CY7C136A-55NXI parts.
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06031 Rev. *E
Revised March 24, 2009
Page 15 of 15
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