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CY7C1460AV33-200AXCT [CYPRESS]

ZBT SRAM, 1MX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100;
CY7C1460AV33-200AXCT
型号： CY7C1460AV33-200AXCT
厂家： CYPRESS    CYPRESS
描述：

ZBT SRAM, 1MX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100

时钟 静态存储器 内存集成电路
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
36 Mbit (1M x 36/2M x 18/512K x 72)  
Pipelined SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ Pin compatible and functionally equivalent to ZBT  
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are  
3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst  
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.  
They are designed to support unlimited true back-to-back  
Read/Write operations with no wait states. The CY7C1460AV33/  
CY7C1462AV33/CY7C1464AV33 are equipped with the  
advanced (NoBL) logic required to enable consecutive  
Read/Write operations with data being transferred on every clock  
cycle. This feature dramatically improves the throughput of data  
in systems that require frequent Write/Read transitions. The  
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin  
compatible and functionally equivalent to ZBT devices.  
■ Supports 250 MHz Bus Operations with Zero Wait States  
❐ Available speed grades are 250, 200 and 167 MHz  
■ Internally self timed Output Buffer Control to eliminate the need  
to use Asynchronous OE  
■ Fully registered (inputs and outputs) for Pipelined Operation  
■ Byte Write Capability  
■ 3.3V Power Supply  
■ 3.3V/2.5V I/O Power Supply  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the Clock Enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle.  
■ Fast Clock-to-output times  
❐ 2.6 ns (for 250 MHz device)  
■ Clock Enable (CEN) Pin to suspend operation  
■ Synchronous self timed Writes  
Write operations are controlled by the Byte Write Selects  
(BWa–BWh for CY7C1464AV33, BWa–BWd for CY7C1460AV33  
and BWa–BWb for CY7C1462AV33) and a Write Enable (WE)  
input. All writes are conducted with on-chip synchronous self  
timed write circuitry.  
■ CY7C1460AV33, CY7C1462AV33 available in  
JEDEC-standard Pb-Free 100-pin TQFP, Pb-Free and  
non-Pb-Free 165-ball FBGA package. CY7C1464AV33  
available in Pb-Free and non-Pb-Free 209-ball FBGA package  
■ IEEE 1149.1 JTAG-Compatible Boundary Scan  
■ Burst Capability—Linear or Interleaved Burst Order  
■ “ZZ” Sleep Mode Option and Stop Clock Option  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tristate control. To avoid bus contention, the  
output drivers are synchronously tristated during the data portion  
of a write sequence.  
Logic Block Diagram – CY7C1460AV33 (1M x 36)  
ADDRESS  
REGISTER  
A0, A1,  
A
0
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
ADV/LD  
CLK  
CEN  
C
C
WRITE ADDRESS  
REGISTER  
WRITE ADDRESS  
REGISTER 2  
1
O
O
S
U
D
A
T
U
T
T
P
U
T
E
N
S
P
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
F
E
R
S
S
T
E
E
R
I
DQ s  
DQ P  
DQ P  
DQ P  
DQ P  
WRITE  
DRIVERS  
BW  
a
a
b
c
A
M
P
BW  
BW  
BW  
b
c
S
T
E
R
S
d
d
S
WE  
E
E
N
G
INPUT  
REGISTER  
INPUT  
REGISTER 0  
E
E
1
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
Document #: 38-05353 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 27, 2009  
[+] Feedback  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Logic Block Diagram – CY7C1462AV33 (2M x 18)  
ADDRESS  
REGISTER  
A0, A1,  
A
0
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
ADV/LD  
CLK  
CEN  
C
C
WRITE ADDRESS  
REGISTER  
WRITE ADDRESS  
REGISTER 2  
1
O
U
T
O
U
T
P
U
T
S
E
P
U
T
D
A
T
ADV/LD  
N
S
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
A
R
E
G
I
MEMORY  
ARRAY  
E
B
U
F
F
E
R
S
DQ s  
DQ P  
DQ P  
WRITE  
DRIVERS  
BW  
BW  
a
S
T
E
E
R
I
A
M
P
a
b
S
T
E
R
S
b
S
N
G
WE  
E
E
INPUT  
REGISTER  
INPUT  
REGISTER 0  
E
E
1
OE  
CE1  
CE2  
CE3  
READ LOGIC  
Sleep  
Control  
ZZ  
Logic Block Diagram – CY7C1464AV33 (512K x 72)  
ADDRESS  
REGISTER  
A0, A1,  
A
0
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
ADV/LD  
CLK  
CEN  
C
C
WRITE ADDRESS  
REGISTER  
WRITE ADDRESS  
REGISTER 2  
1
O
U
T
O
U
T
P
U
T
S
E
P
U
T
D
A
T
ADV/LD  
N
S
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
A
BW  
BW  
BW  
BW  
BW  
a
R
E
G
I
MEMORY  
ARRAY  
E
B
U
F
F
E
R
S
DQ s  
DQ P  
DQ P  
DQ P  
DQ P  
DQ P  
DQ P  
DQ P  
DQ P  
WRITE  
DRIVERS  
b
S
T
E
E
R
I
A
M
P
a
b
c
c
d
e
S
T
E
R
S
S
d
e
f
BW  
f
N
G
BW  
g
E
E
BW  
h
g
h
WE  
INPUT  
REGISTER  
INPUT  
REGISTER 0  
E
E
1
OE  
CE1  
CE2  
CE3  
READ LOGIC  
Sleep  
Control  
ZZ  
Selection Guide  
Description  
250 MHz  
2.6  
200 MHz  
3.2  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
475  
425  
375  
mA  
mA  
Maximum CMOS Standby  
Current  
120  
120  
120  
Document #: 38-05353 Rev. *E  
Page 2 of 28  
[+] Feedback  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Pin Configurations  
Figure 1. 100-Pin TQFP Pinout  
DQPc  
DQc  
DQc  
1
2
3
4
5
6
7
8
NC  
NC  
NC  
DDQ  
1
2
3
4
5
6
7
8
A
NC  
NC  
78  
DQPb  
DQb  
DQb  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
80  
79  
V
V
DDQ  
V
V
V
NC  
DQPa  
DQa  
DQa  
DDQ  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DDQ  
SS  
V
V
V
SS  
SS  
SS  
DQc  
DQc  
NC  
NC  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQc  
DQc  
9
9
V
V
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
V
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
V
SS  
SS  
V
V
DDQ  
DDQ  
V
V
DQa  
DQa  
V
NC  
V
ZZ  
DDQ  
DDQ  
DQc  
DQc  
NC  
DQb  
DQb  
DQb  
DQb  
NC  
V
SS  
CY7C1462AV33  
(2M × 18)  
CY7C1460AV33  
(1M × 36)  
SS  
V
V
DD  
NC  
DD  
NC  
NC  
V
DD  
DD  
V
V
SS  
SS  
ZZ  
DQa  
DQa  
DQd  
DQb  
DQb  
DQa  
DQa  
DQd  
V
V
DDQ  
DDQ  
V
V
V
DQa  
DQa  
NC  
NC  
V
V
DDQ  
DDQ  
V
V
SS  
V
SS  
SS  
SS  
DQd  
DQd  
DQd  
DQd  
DQa  
DQa  
DQb  
DQb  
DQa DQPb  
DQa  
NC  
V
SS  
V
V
SS  
SS  
SS  
V
V
DDQ  
V
DDQ  
DDQ  
DDQ  
DQd  
DQd  
DQPd  
DQa  
DQa  
DQPa  
NC  
NC  
NC  
NC  
NC  
NC  
Document #: 38-05353 Rev. *E  
Page 3 of 28  
[+] Feedback  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Pin Configurations (continued)  
Figure 2. 165-ball FBGA (15 x 17 x 1.4 mm)  
CY7C1460AV33 (1M × 36)  
1
2
A
3
4
5
6
7
8
9
A
10  
A
11  
NC  
NC/576M  
NC/1G  
DQPc  
ADV/LD  
A
B
C
D
CE1  
BWc  
BWd  
VSS  
VDD  
BWb  
BWa  
VSS  
VSS  
CE3  
CLK  
VSS  
VSS  
CEN  
WE  
A
CE2  
VDDQ  
VDDQ  
OE  
VSS  
VDD  
A
A
NC  
NC  
DQc  
VSS  
VSS  
VDDQ  
VDDQ  
NC  
DQb  
DQPb  
DQb  
DQc  
DQc  
DQc  
DQc  
NC  
DQc  
DQc  
DQc  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
DQb  
DQb  
DQb  
NC  
DQb  
DQb  
DQb  
ZZ  
E
F
G
H
J
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
K
L
DQd  
DQd  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC  
A1  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQa  
NC  
A
DQa  
DQPa  
M
N
P
DQPd  
NC/144M NC/72M  
TDI  
TDO  
NC/288M  
A
MODE  
A
A
TMS  
A0  
TCK  
A
A
A
A
R
CY7C1462AV33 (2M × 18)  
1
NC/576M  
NC/1G  
NC  
2
A
3
4
5
NC  
6
CE3  
7
8
9
A
10  
A
11  
A
A
B
C
D
CE1  
BWb  
NC  
CEN  
ADV/LD  
NC  
A
CE2  
VDDQ  
VDDQ  
BWa  
VSS  
VSS  
CLK  
VSS  
VSS  
A
A
WE  
VSS  
VSS  
OE  
VSS  
VDD  
NC  
DQb  
VSS  
VDD  
VDDQ  
VDDQ  
NC  
NC  
DQPa  
DQa  
NC  
NC  
NC  
DQb  
DQb  
DQb  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
NC  
DQa  
DQa  
DQa  
ZZ  
E
F
NC  
NC  
G
H
J
NC  
NC  
DQb  
DQb  
DQb  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQa  
DQa  
DQa  
NC  
NC  
NC  
K
L
NC  
NC  
DQb  
NC  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC  
A1  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQa  
NC  
A
NC  
NC  
M
N
P
DQPb  
NC/144M NC/72M  
TDI  
TDO  
NC/288M  
A
MODE  
A
A
TMS  
A0  
TCK  
A
A
A
A
R
Document #: 38-05353 Rev. *E  
Page 4 of 28  
[+] Feedback  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Pin Configurations (continued)  
Figure 3.  
209-ball FBGA (14 x 22 x 1.76 mm)  
CY7C1464AV33 (512K x 72)  
1
DQg  
DQg  
DQg  
2
3
4
5
6
7
8
9
10  
11  
A
B
C
D
E
F
DQg  
DQg  
CE3  
DQb  
DQb  
CE2  
ADV/LD  
WE  
DQb  
DQb  
A
A
A
A
A
BWSb  
NC  
BWSc  
BWSh  
VSS  
BWSf  
BWSg  
BWSd  
DQg  
DQg  
DQPc  
DQc  
DQc  
NC/576M  
NC  
NC  
BWSe  
NC  
CE1  
BWSa DQb  
DQb  
DQb  
DQPb  
DQf  
DQg  
NC/1G  
OE  
VSS  
NC  
DQb  
DQPg  
DQc  
VDDQ  
VDDQ  
DQPf  
VDDQ  
VDDQ  
VSS  
VDDQ  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VDD  
NC  
VDD  
VSS  
VDD  
VSS  
DQf  
VSS  
VDDQ  
VSS  
VSS  
G
H
J
DQc  
DQc  
VDDQ  
VSS  
NC  
VDDQ  
VSS  
DQf  
DQf  
DQf  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
VSS  
VDD  
NC  
A
DQc  
DQc  
NC  
NC  
DQf  
DQf  
NC  
VDDQ  
DQc  
NC  
VDDQ  
VDDQ  
CLK  
VDDQ  
NC  
NC  
DQf  
NC  
K
L
CEN  
NC  
NC  
NC  
DQh  
DQh  
DQh  
VDDQ  
VSS  
VDDQ  
VSS  
VDDQ  
VDDQ  
VSS  
VDDQ  
VSS  
DQa  
DQa  
DQa  
M
N
P
R
T
NC  
VSS  
VDDQ  
VSS  
VDDQ  
NC  
DQh  
DQh  
DQh  
VSS  
VDD  
VSS  
DQa  
DQa  
DQa  
VDDQ  
DQh  
DQh  
DQPd  
DQd  
DQd  
VDDQ  
VSS  
NC  
ZZ  
DQa  
DQa  
DQPa  
DQe  
DQe  
VSS  
VDDQ  
VDDQ  
VDD  
NC  
DQPh  
DQd  
DQd  
DQd  
DQd  
VDDQ  
VDD  
DQPe  
DQe  
DQe  
DQe  
DQe  
VSS  
VSS  
NC  
A
MODE  
A
U
V
W
NC/72M  
A
NC/288M  
NC/144M  
A
A
A1  
A
DQd  
DQd  
A
A
A
A
DQe  
DQe  
TDI  
TDO  
TCK  
A0  
A
TMS  
Pin Definitions  
Pin Name  
I/O Type  
Pin Description  
A0  
A1  
A
Input-  
Synchronous  
Address Inputs Used to Select One of the Address Locations. Sampled at the rising  
edge of the CLK.  
BWa  
BWb  
BWc  
BWd  
BWe  
BWf  
Input-  
Synchronous  
Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM.  
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and  
DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and  
DQPe, BWf controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and  
DQPh.  
BWg  
BWh  
WE  
Input-  
Synchronous  
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active  
LOW. This signal must be asserted LOW to initiate a write sequence.  
Document #: 38-05353 Rev. *E  
Page 5 of 28  
[+] Feedback  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Pin Definitions (continued)  
Pin Name  
ADV/LD  
I/O Type  
Pin Description  
Input-  
Synchronous  
Advance/Load Input Used to Advance the On-chip Address Counter or Load a New  
Address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced.  
When LOW, a new address can be loaded into the device for an access. After being  
deselected, ADV/LD should be driven LOW to load a new address.  
CLK  
CE1  
CE2  
CE3  
OE  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with  
CEN. CLK is only recognized if CEN is active LOW.  
Input-  
Synchronous  
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in  
conjunction with CE2 and CE3 to select/deselect the device.  
Input-  
Synchronous  
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in  
conjunction with CE1 and CE3 to select/deselect the device.  
Input-  
Synchronous  
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in  
conjunction with CE1 and CE2 to select/deselect the device.  
Input-  
Asynchronous  
Output Enable, Active LOW. Combined with the synchronous logic block inside the  
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to  
behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data  
pins. OE is masked during the data portion of a write sequence, during the first clock when  
emerging from a deselected state and when the device has been deselected.  
CEN  
Input-  
Synchronous  
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by  
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN  
does not deselect the device, CEN can be used to extend the previous cycle when required.  
DQa  
DQb  
DQc  
DQd  
DQe  
DQf  
I/O-  
Synchronous  
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is  
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the  
memory location specified by AX during the previous clock rise of the read cycle. The  
direction of the pins is controlled by OE and the internal control logic. When OE is asserted  
LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tristate  
condition. The outputs are automatically tristated during the data portion of a write  
sequence, during the first clock when emerging from a deselected state, and when the  
device is deselected, regardless of the state of OE.  
DQg  
DQh  
DQPa,DQPb,  
DQPc,DQPd  
DQPe,DQPf  
DQPg,DQPh  
I/O-  
Synchronous  
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ[31:0].  
During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is  
controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is  
controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh.  
MODE  
Input Strap Pin  
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst  
order. Pulled LOW selects the linear burst order. MODE should not change states during  
operation. When left floating MODE defaults HIGH, to an interleaved burst order.  
TDO  
TDI  
JTAG serial output Serial Data-out to the JTAG Circuit. Delivers data on the negative edge of TCK.  
Synchronous  
JTAG serial input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK.  
Synchronous  
TMS  
Test Mode Select This Pin Controls the Test Access Port State Machine. Sampled on the rising edge of  
Synchronous  
JTAG-Clock  
Power Supply  
TCK.  
TCK  
VDD  
Clock Input to the JTAG Circuitry.  
Power Supply Inputs to the Core of the Device.  
VDDQ  
I/O Power Supply Power Supply for the I/O Circuitry.  
VSS  
Ground  
N/A  
Ground for the Device. Should be connected to ground of the system.  
NC  
No Connects. This pin is not connected to the die.  
NC/72M  
N/A  
Not Connected to the Die. Can be tied to any voltage level.  
NC/144M  
NC/288M  
N/A  
N/A  
Not Connected to the Die. Can be tied to any voltage level.  
Not Connected to the Die. Can be tied to any voltage level.  
Document #: 38-05353 Rev. *E  
Page 6 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Pin Definitions (continued)  
Pin Name  
NC/576M  
I/O Type  
Pin Description  
Not Connected to the Die. Can be tied to any voltage level.  
Not Connected to the Die. Can be tied to any voltage level.  
N/A  
N/A  
NC/1G  
ZZ  
Input-  
Asynchronous  
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”  
condition with data integrity preserved. During normal operation, this pin can be connected  
to VSS or left floating. ZZ pin has an internal pull down.  
Burst Read Accesses  
Functional Overview  
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 have an  
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are  
synchronous-pipelined Burst NoBL SRAMs designed specifi-  
cally to eliminate wait states during Write/Read transitions. All  
synchronous inputs pass through input registers controlled by  
the rising edge of the clock. The clock signal is qualified with the  
Clock Enable input signal (CEN). If CEN is HIGH, the clock signal  
is not recognized and all internal states are maintained. All  
synchronous operations are qualified with CEN. All data outputs  
pass through output registers controlled by the rising edge of the  
clock. Maximum access delay from the clock rise (tCO) is 2.6 ns  
(250 MHz device).  
on-chip burst counter that enables the user the ability to supply  
a single address and conduct up to four Reads without  
reasserting the address inputs. ADV/LD must be driven LOW in  
order to load a new address into the SRAM, as described in the  
Single Read Access section earlier. The sequence of the burst  
counter is determined by the MODE input signal. A LOW input  
on MODE selects a linear burst mode, a HIGH selects an inter-  
leaved burst sequence. Both burst counters use A0 and A1 in the  
burst sequence, and wraps around when incremented suffi-  
ciently. A HIGH input on ADV/LD increments the internal burst  
counter regardless of the state of chip enables inputs or WE. WE  
is latched at the beginning of a burst cycle. Therefore, the type  
of access (Read or Write) is maintained throughout the burst  
sequence.  
Accesses can be initiated by asserting all three Chip Enables  
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock  
Enable (CEN) is active LOW and ADV/LD is asserted LOW, the  
address presented to the device is latched. The access can  
either be a read or write operation, depending on the status of  
the Write Enable (WE). BW[x] can be used to conduct byte write  
operations.  
Single Write Accesses  
Write access are initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,  
and CE3 are ALL asserted active, and (3) the write signal WE is  
asserted LOW. The address presented to the address inputs is  
loaded into the Address Register. The write signals are latched  
into the Control Logic block.  
Write operations are qualified by the Write Enable (WE). All  
writes are simplified with on-chip synchronous self timed write  
circuitry.  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) simplify depth expansion. All  
operations (Reads, Writes, and Deselects) are pipelined.  
ADV/LD should be driven LOW after the device has been  
deselected to load a new address for the next operation.  
On the subsequent clock rise the data lines are automatically  
tristated regardless of the state of the OE input signal. This  
enables the external logic to present the data on DQ and DQP  
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h  
for  
CY7C1464AV33,  
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for  
CY7C1462AV33). In addition, the address for the subsequent  
access (Read/Write/Deselect) is latched into the Address  
Register (provided the appropriate control signals are asserted).  
Single Read Accesses  
A read access is initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,  
and CE3 are ALL asserted active, (3) the Write Enable input  
signal WE is deasserted HIGH, and (4) ADV/LD is asserted  
LOW. The address presented to the address inputs is latched  
into the Address Register and presented to the memory core and  
control logic. The control logic determines that a read access is  
in progress and allows the requested data to propagate to the  
input of the output register. At the rising edge of the next clock  
the requested data is allowed to propagate through the output  
register and onto the data bus within 2.6 ns (250 MHz device)  
provided OE is active LOW. After the first clock of the read  
access the output buffers are controlled by OE and the internal  
control logic. OE must be driven LOW for the device to drive out  
the requested data. During the second clock, a subsequent  
operation (Read/Write/Deselect) can be initiated. Deselecting  
the device is also pipelined. Therefore, when the SRAM is  
deselected at clock rise by one of the chip enable signals, its  
output tristates following the next clock rise.  
On the next clock rise the data presented to DQ and DQP  
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h  
for  
CY7C1464AV33,  
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for  
CY7C1462AV33) (or a subset for byte write operations, see  
Write Cycle Description table for details) inputs is latched into the  
device and the write is complete.  
The data written during the Write operation is controlled by BW  
(BWa,b,c,d,e,f,g,h  
CY7C1460AV33 and BWa,b for CY7C1462AV33) signals. The  
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 provides  
for  
CY7C1464AV33,  
BWa,b,c,d  
for  
byte write capability that is described in the Write Cycle  
Description table. Asserting the Write Enable input (WE) with the  
selected Byte Write Select (BW) input selectively writes to only  
the desired bytes. Bytes not selected during a byte write  
operation remains unaltered. A synchronous self timed write  
mechanism has been provided to simplify the write operations.  
Byte write capability has been included in order to greatly simplify  
Document #: 38-05353 Rev. *E  
Page 7 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Read/Modify/Write sequences, which can be reduced to simple  
byte write operations.  
Sleep Mode  
The ZZ input pin is an asynchronous input. Asserting ZZ places  
the SRAM in a power conservation “sleep” mode. Two clock  
cycles are required to enter into or exit from this “sleep” mode.  
While in this mode, data integrity is guaranteed. Accesses  
pending when entering the “sleep” mode are not considered valid  
nor is the completion of the operation guaranteed. The device  
must be deselected prior to entering the “sleep” mode. CE1, CE2,  
and CE3, must remain inactive for the duration of tZZREC after the  
ZZ input returns LOW.  
Because the CY7C1460AV33/CY7C1462AV33/CY7C1464AV33  
are common I/O devices, data should not be driven into the  
device while the outputs are active. The Output Enable (OE) can  
be deasserted HIGH before presenting data to the DQ and DQP  
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h  
for  
CY7C1464AV33,  
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for  
CY7C1462AV33) inputs. Doing so tristates the output drivers. As  
a
safety  
precaution,  
DQ  
for  
and  
DQP  
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h  
CY7C1464AV33,  
Interleaved Burst Address Table  
(MODE = Floating or V )  
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for  
CY7C1462AV33) are automatically tristated during the data  
portion of a write cycle, regardless of the state of OE.  
DD  
First  
Address  
Second  
Address  
Third  
Address  
Fourth  
Address  
Burst Write Accesses  
A1,A0  
00  
A1,A0  
01  
A1,A0  
10  
A1,A0  
11  
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 has an  
on-chip burst counter that allows the user the ability to supply a  
single address and conduct up to four WRITE operations without  
reasserting the address inputs. ADV/LD must be driven LOW in  
order to load the initial address, as described in the Single Write  
Access section earlier. When ADV/LD is driven HIGH on the  
subsequent clock rise, the chip enables (CE1, CE2, and CE3)  
and WE inputs are ignored and the burst counter is incremented.  
The correct BW (BWa,b,c,d,e,f,g,h for CY7C1464AV33, BWa,b,c,d  
for CY7C1460AV33 and BWa,b for CY7C1462AV33) inputs must  
be driven in each cycle of the burst write in order to write the  
correct bytes of data.  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Linear Burst Address Table (MODE = GND)  
First  
Address  
Second  
Address  
Third  
Address  
Fourth  
Address  
A1,A0  
00  
A1,A0  
01  
A1,A0  
10  
A1,A0  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
ZZ Mode Electrical Characteristics  
Parameter  
IDDZZ  
Description  
Sleep mode standby current  
Device operation to ZZ  
ZZ recovery time  
Test Conditions  
Min  
Max  
Unit  
mA  
ns  
ZZ > VDD − 0.2V  
100  
tZZS  
ZZ > VDD − 0.2V  
2tCYC  
tZZREC  
tZZI  
ZZ < 0.2V  
2tCYC  
0
ns  
ZZ active to sleep current  
ZZ Inactive to exit sleep current  
This parameter is sampled  
This parameter is sampled  
2tCYC  
ns  
tRZZI  
ns  
Document #: 38-05353 Rev. *E  
Page 8 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Truth Table  
The Truth Table for CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 follows. [1, 2, 3, 4, 5, 6, 7]  
Address  
Operation  
CE  
ZZ  
ADV/LD WE  
BWx  
OE  
CEN  
CLK  
DQ  
Used  
None  
None  
Deselect Cycle  
Continue  
H
X
L
L
L
X
X
X
X
X
X
L
L
L-H  
L-H  
Tristate  
Tristate  
H
Deselect Cycle  
Read Cycle  
(Begin Burst)  
Read Cycle  
(Continue Burst)  
NOP/Dummy Read  
(Begin Burst)  
Dummy Read  
(Continue Burst)  
Write Cycle  
(Begin Burst)  
Write Cycle  
(Continue Burst)  
NOP/WRITE ABORT  
(Begin Burst)  
WRITE ABORT  
(Continue Burst)  
IGNORE CLOCK  
EDGE  
External  
Next  
L
X
L
L
L
L
L
L
L
L
L
L
L
H
L
H
X
H
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
H
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
Data Out (Q)  
Data Out (Q)  
Tristate  
External  
Next  
H
H
X
X
X
X
X
X
L
H
L
Tristate  
External  
Next  
Data In (D)  
Data In (D)  
Tristate  
X
L
H
L
X
L
L
None  
H
H
X
Next  
X
X
H
X
X
X
Tristate  
Current  
-
(Stall)  
SLEEP MODE  
None  
X
H
X
X
X
X
X
X
Tristate  
Notes  
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =  
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.  
2. Write is defined by WE and BW . See Write Cycle Description table for details.  
X
3. When a write cycle is detected, all I/Os are tristated, even during byte writes.  
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.  
5. CEN = H inserts wait states.  
6. Device powers up deselected and the I/Os in a tristate condition, regardless of OE.  
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ and DQP = Tristate when OE  
s
X
is inactive or when the device is deselected, and DQ =data when OE is active.  
s
Document #: 38-05353 Rev. *E  
Page 9 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Partial Write Cycle Description  
The Partial Write Cycle Description for CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 follows. [1, 2, 3, 8]  
Function (CY7C1460AV33)  
WE  
H
L
BWd  
X
H
H
H
H
H
H
H
H
L
BWc  
X
BWb  
BWa  
X
H
L
Read  
X
H
H
L
Write – No bytes written  
Write Byte a – (DQa and DQPa)  
Write Byte b – (DQb and DQPb)  
Write Bytes b, a  
H
H
H
H
L
L
L
H
L
L
L
Write Byte c – (DQc and DQPc)  
Write Bytes c, a  
L
H
H
L
H
L
L
L
Write Bytes c, b  
L
LL  
L
H
L
Write Bytes c, b, a  
L
L
Write Byte d – (DQd and DQPd)  
Write Bytes d, a  
L
H
H
H
H
L
H
H
L
H
L
L
L
Write Bytes d, b  
L
L
H
L
Write Bytes d, b, a  
L
L
L
Write Bytes d, c  
L
L
H
H
L
H
L
Write Bytes d, c, a  
L
L
L
Write Bytes d, c, b  
L
L
L
H
L
Write All Bytes  
L
L
L
L
Function (CY7C1462AV33)[2,8]  
WE  
BWb  
BWa  
Read  
H
L
L
L
L
x
H
H
L
x
H
L
Write – No Bytes Written  
Write Byte a – (DQa and DQPa)  
Write Byte b – (DQb and DQPb)  
Write Both Bytes  
H
L
L
Function (CY7C1464AV33)[2,8]  
WE  
BWx  
Read  
H
L
L
L
x
Write – No Bytes Written  
Write Byte X − (DQx and DQPx)  
Write All Bytes  
H
L
All BW = L  
Note  
8. Table only lists a partial listing of the byte write combinations. Any combination of BW  
is valid. Appropriate write is done based on which byte write is active.  
[a:d]  
Document #: 38-05353 Rev. *E  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Test Data-In (TDI)  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
The TDI ball is used to serially input information into the registers  
and can be connected to the input of any of the registers. The  
register between TDI and TDO is chosen by the instruction that  
is loaded into the TAP instruction register. TDI is internally pulled  
up and can be unconnected if the TAP is unused in an appli-  
cation. TDI is connected to the most significant bit (MSB) of any  
register. (See TAP Controller Block Diagram.)  
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 incor-  
porates a serial boundary scan test access port (TAP). This part  
is fully compliant with 1149.1. The TAP operates using  
JEDEC-standard 3.3V or 2.5V I/O logic level.  
The  
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33  
contains a TAP controller, instruction register, boundary scan  
register, bypass register, and ID register.  
Test Data-Out (TDO)  
Disabling the JTAG Feature  
The TDO output ball is used to serially clock data-out from the  
registers. The output is active depending upon the current state  
of the TAP state machine. The output changes on the falling edge  
of TCK. TDO is connected to the least significant bit (LSB) of any  
register. (See TAP Controller State Diagram.)  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
(VSS) to prevent clocking of the device. TDI and TMS are inter-  
nally pulled up and may be unconnected. They may alternately  
be connected to VDD through a pull up resistor. TDO should be  
left unconnected. Upon power up, the device comes up in a reset  
state which does not interfere with the operation of the device.  
TAP Controller Block Diagram  
0
TAP Controller State Diagram  
Bypass Register  
TEST-LOGIC  
1
2
1
0
0
0
RESET  
0
Selection  
Circuitry  
Selection  
Circuitry  
Instruction Register  
31 30 29  
Identification Register  
TDI  
TDO  
1
1
1
RUN-TEST/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
.
.
. 2 1  
0
0
0
1
1
CAPTURE-DR  
CAPTURE-IR  
x
.
.
.
.
. 2 1  
0
0
Boundary Scan Register  
SHIFT-DR  
0
SHIFT-IR  
0
1
1
1
1
EXIT1-DR  
EXIT1-IR  
TCK  
TAP CONTROLLER  
0
0
TM S  
PAUSE-DR  
0
PAUSE-IR  
1
0
1
0
0
Performing a TAP Reset  
EXIT2-DR  
1
EXIT2-IR  
1
A RESET is performed by forcing TMS HIGH (VDD) for five rising  
edges of TCK. This RESET does not affect the operation of the  
SRAM and may be performed while the SRAM is operating.  
UPDATE-DR  
UPDATE-IR  
1
0
1
0
At power up, the TAP is reset internally to ensure that TDO  
comes up in a High Z state.  
TAP Registers  
The 0/1 next to each state represents the value of TMS at the  
rising edge of TCK.  
Registers are connected between the TDI and TDO balls and  
allow data to be scanned into and out of the SRAM test circuitry.  
Only one register can be selected at a time through the  
instruction register. Data is serially loaded into the TDI ball on the  
rising edge of TCK. Data is output on the TDO ball on the falling  
edge of TCK.  
Test Access Port (TAP)  
Test Clock (TCK)  
The test clock is used only with the TAP controller. All inputs are  
captured on the rising edge of TCK. All outputs are driven from  
the falling edge of TCK.  
Instruction Register  
Three bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the TDI  
and TDO balls as shown in the Tap Controller Block Diagram.  
Upon power up, the instruction register is loaded with the  
IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as described  
in the previous section.  
Test MODE SELECT (TMS)  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to leave  
this ball unconnected if the TAP is not used. The ball is pulled up  
internally, resulting in a logic HIGH level.  
Document #: 38-05353 Rev. *E  
Page 11 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
When the TAP controller is in the Capture-IR state, the two least  
significant bits are loaded with a binary “01” pattern to enable  
fault isolation of the board-level serial test data path.  
the IDCODE to be shifted out of the device when the TAP  
controller enters the Shift-DR state.  
The IDCODE instruction is loaded into the instruction register  
upon power up or whenever the TAP controller is given a test  
logic reset state.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single bit register that can be placed between the  
TDI and TDO balls. This allows data to be shifted through the  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register to  
be connected between the TDI and TDO pins when the TAP  
controller is in a Shift-DR state. The SAMPLE Z command puts  
the output bus into a High Z state until the next command is given  
during the “Update IR” state.  
SRAM with minimal delay. The bypass register is set LOW (VSS  
)
when the BYPASS instruction is executed.  
Boundary Scan Register  
The boundary scan register is connected to all the input and  
bidirectional balls on the SRAM. The length of the Boundary  
Scan Register for the SRAM in different packages is listed in the  
Scan Register Sizes table.  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the  
instruction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and output pins is  
captured in the boundary scan register.  
The boundary scan register is loaded with the contents of the  
RAM I/O ring when the TAP controller is in the Capture-DR state  
and is then placed between the TDI and TDO balls when the  
controller is moved to the Shift-DR state. The EXTEST,  
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to  
capture the contents of the I/O ring.  
The Table , “165-ball FBGA Boundary Scan Order [13],” on  
page 16 and Table , “209-ball BGA Boundary Scan Order [13,  
14],” on page 17 show the order in which the bits are connected.  
Each bit corresponds to one of the bumps on the SRAM  
package. The MSB of the register is connected to TDI, and the  
LSB is connected to TDO.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because there  
is a large difference in the clock frequencies, it is possible that  
during the Capture-DR state, an input or output undergoes a  
transition. The TAP may then try to capture a signal while in  
transition (metastable state). This does not harm the device, but  
there is no guarantee as to the value that is captured.  
Repeatable results may not be possible.  
To guarantee that the boundary scan register captures the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture setup plus hold  
times (tCS and tCH). The SRAM clock input might not be captured  
correctly if there is no way in a design to stop (or slow) the clock  
during a SAMPLE/PRELOAD instruction. If this is an issue, it is  
still possible to capture all other signals and simply ignore the  
value of the CK and CK# captured in the boundary scan register.  
Identification (ID) Register  
The ID register is loaded with a vendor-specific, 32 bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired into  
the SRAM and can be shifted out when the TAP controller is in  
the Shift-DR state. The ID register has a vendor code and other  
information described in the Table , “Identification Register  
Definitions,” on page 14  
After the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the boundary  
scan register between the TDI and TDO pins.  
TAP Instruction Set  
PRELOAD allows an initial data pattern to be placed at the  
latched parallel outputs of the boundary scan register cells prior  
to the selection of another boundary scan test operation.  
Overview  
Eight different instructions are possible with the three bit  
instruction register. All combinations are listed in the Instruction  
Codes table. Three of these instructions are listed as  
RESERVED and should not be used. The other five instructions  
described in detail are as follows.  
The shifting of data for the SAMPLE and PRELOAD phases can  
occur concurrently when required—that is, while data captured  
is shifted out, the preloaded data can be shifted in.  
BYPASS  
Instructions are loaded into the TAP controller during the Shift-IR  
state when the instruction register is placed between TDI and  
TDO. During this state, instructions are shifted through the  
instruction register through the TDI and TDO balls. To execute  
the instruction after it is shifted in, the TAP controller needs to be  
moved into the Update-IR state.  
When the BYPASS instruction is loaded in the instruction register  
and the TAP is placed in a Shift-DR state, the bypass register is  
placed between the TDI and TDO pins. The advantage of the  
BYPASS instruction is that it shortens the boundary scan path  
when multiple devices are connected together on a board.  
IDCODE  
EXTEST  
The IDCODE instruction causes a vendor-specific, 32 bit code to  
be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO balls and allows  
The EXTEST instruction enables the preloaded data to be driven  
out through the system output pins. This instruction also selects  
the boundary scan register to be connected for serial access  
between the TDI and TDO in the shift-DR controller state.  
Document #: 38-05353 Rev. *E  
Page 12 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
EXTEST OUTPUT BUS TRISTATE  
This bit can be set by entering the SAMPLE/PRELOAD or  
EXTEST command, and then shifting the desired bit into that cell,  
during the “Shift-DR” state. During “Update-DR,” the value  
loaded into that shift-register cell latches into the preload  
register. When the EXTEST instruction is entered, this bit directly  
controls the output Q-bus pins. Note that this bit is preset HIGH  
to enable the output when the device is powered-up, and also  
when the TAP controller is in the “Test-Logic-Reset” state.  
IEEE Standard 1149.1 mandates that the TAP controller be able  
to put the output bus into a tristate mode.  
The boundary scan register has a special bit located at bit #89  
(for 165-FBGA package) or bit #138 (for 209-FBGA package).  
When this scan cell, called the “extest output bus tristate,” is  
latched into the preload register during the “Update-DR” state in  
the TAP controller, it directly controls the state of the output  
(Q-bus) pins, when the EXTEST is entered as the current  
instruction. When HIGH, it enables the output buffers to drive the  
output bus. When LOW, this bit places the output bus into a High  
Z condition.  
Reserved  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
TAP Timing Diagram  
1
2
3
4
5
6
Test Clock  
(TCK)  
t
t
t
CYC  
TH  
TL  
t
t
t
t
TM SS  
TDIS  
TM SH  
Test M ode Select  
(TM S)  
TDIH  
Test Data-In  
(TDI)  
t
TDOV  
t
TDOX  
Test Data-Out  
(TDO)  
DON’T CARE  
UNDEFINED  
TAP AC Switching Characteristics Over the Operating Range[9, 10]  
Parameter  
Clock  
tTCYC  
tTF  
tTH  
tTL  
Description  
Min  
Max  
Unit  
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH time  
TCK Clock LOW time  
50  
ns  
MHz  
ns  
20  
10  
20  
20  
ns  
Output Times  
tTDOV  
tTDOX  
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
ns  
ns  
0
Setup Times  
tTMSS  
tTDIS  
TMS Setup to TCK Clock Rise  
TDI Setup to TCK Clock Rise  
Capture Setup to TCK Rise  
5
5
5
ns  
ns  
ns  
tCS  
Hold Times  
tTMSH  
tTDIH  
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
tCH  
Capture Hold after Clock Rise  
Notes  
9.  
t
and t refer to the setup and hold time requirements of latching data from the boundary scan register.  
CS CH  
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.  
R
F
Document #: 38-05353 Rev. *E  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
3.3V TAP AC Test Conditions  
2.5V TAP AC Test Conditions  
Input pulse levels.................................................VSS to 3.3V  
Input rise and fall times....................................................1 ns  
Input timing reference levels........................................... 1.5V  
Output reference levels .................................................. 1.5V  
Test load termination supply voltage .............................. 1.5V  
Input pulse levels ................................................VSS to 2.5V  
Input rise and fall time .....................................................1 ns  
Input timing reference levels......................................... 1.25V  
Output reference levels ................................................ 1.25V  
Test load termination supply voltage ............................ 1.25V  
Figure 4. 3.3V TAP AC Output Load Equivalent  
Figure 5. 2.5V TAP AC Output Load Equivalent  
1.25V  
1.5V  
50Ω  
50Ω  
TDO  
TDO  
ZO= 50Ω  
20pF  
ZO= 50Ω  
20pF  
TAP DC Electrical Characteristics And Operating Conditions  
(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11]  
Parameter  
VOH1  
Description  
Output HIGH Voltage IOH = –4.0 mA, VDDQ = 3.3V  
OH = –1.0 mA, VDDQ = 2.5V  
Test Conditions  
Min  
2.4  
2.0  
2.9  
2.1  
Max  
Unit  
V
V
V
V
V
V
V
V
V
V
V
V
µA  
I
VOH2  
VOL1  
VOL2  
VIH  
Output HIGH Voltage IOH = –100 µA  
VDDQ = 3.3V  
VDDQ = 2.5V  
VDDQ = 3.3V  
VDDQ = 2.5V  
VDDQ = 3.3V  
Output LOW Voltage IOL = 8.0 mA  
0.4  
0.4  
I
OL = 1.0 mA  
Output LOW Voltage IOL = 100 µA  
0.2  
VDDQ = 2.5V  
0.2  
Input HIGH Voltage  
VDDQ = 3.3V  
VDDQ = 2.5V  
VDDQ = 3.3V  
2.0  
1.7  
VDD + 0.3  
VDD + 0.3  
0.8  
VIL  
Input LOW Voltage  
–0.3  
–0.3  
–5  
VDDQ = 2.5V  
0.7  
IX  
Input Load Current  
GND < VIN < VDDQ  
5
Identification Register Definitions  
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33  
Instruction Field  
Description  
(1M ×36)  
000  
(2M ×18)  
000  
(512K ×72)  
000  
Revision Number (31:29)  
Device Depth (28:24)[12]  
Architecture/Memory Type(23:18)  
Describes the version number.  
Reserved for Internal Use  
Defines memory type and  
architecture  
01011  
001000  
01011  
001000  
01011  
001000  
Bus Width/Density(17:12)  
100111  
010111  
110111  
Defines width and density  
Cypress JEDEC ID Code (11:1)  
00000110100  
00000110100  
00000110100 Allows unique identification of  
SRAM vendor.  
ID Register Presence Indicator (0)  
1
1
1
Indicates the presence of an ID  
register.  
Notes  
11. All voltages referenced to V (GND).  
SS  
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.  
Document #: 38-05353 Rev. *E  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Scan Register Sizes  
Register Name  
Bit Size (×36)  
Bit Size (×18)  
Bit Size (×72)  
Instruction  
3
1
3
1
3
1
Bypass  
ID  
32  
89  
-
32  
89  
-
32  
-
Boundary Scan Order (165-ball FBGA package)  
Boundary Scan Order (209-ball FBGA package)  
138  
Identification Codes  
Instruction  
EXTEST  
Code  
Description  
000  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM outputs to High Z state.  
IDCODE  
001  
010  
Loads the ID register with the vendor ID code and places the register between TDI and  
TDO. This operation does not affect SRAM operations.  
SAMPLE Z  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM output drivers to a High Z state.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Does not affect SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect SRAM  
operations.  
Document #: 38-05353 Rev. *E  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
165-ball FBGA Boundary Scan Order [13]  
CY7C1460AV33 (1M x 36), CY7C1462AV33 (2M x 18)  
Bit#  
1
ball ID  
N6  
Bit#  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
ball ID  
E11  
D11  
G10  
F10  
E10  
D10  
C11  
A11  
B11  
A10  
B10  
A9  
Bit#  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
ball ID  
A3  
A2  
B2  
C2  
B1  
A1  
C1  
D1  
E1  
F1  
Bit#  
ball ID  
N1  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
2
N7  
N2  
3
10N  
P11  
P8  
P1  
4
R1  
5
R2  
6
R8  
P3  
7
R9  
R3  
8
P9  
P2  
9
P10  
R10  
R11  
H11  
N11  
M11  
L11  
K11  
J11  
M10  
L10  
K10  
J10  
H9  
R4  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
P4  
G1  
D2  
E2  
F2  
N5  
P6  
B9  
R6  
C10  
A8  
Internal  
G2  
H1  
H3  
J1  
B8  
A7  
B7  
B6  
K1  
L1  
A6  
B5  
M1  
J2  
A5  
H10  
G11  
F11  
A4  
K2  
L2  
B4  
B3  
M2  
Note  
13. Bit# 89 is preset HIGH.  
Document #: 38-05353 Rev. *E  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
209-ball BGA Boundary Scan Order [13, 14]  
CY7C14604V33 (512K x 72)  
Bit#  
1
Ball ID  
Bit#  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
ball ID  
6F  
Bit#  
71  
ball ID  
6H  
6C  
6B  
6A  
5A  
5B  
5C  
5D  
4D  
4C  
4A  
4B  
3C  
3B  
3A  
2A  
1A  
2B  
1B  
2C  
1C  
2D  
1D  
1E  
2E  
2F  
Bit#  
ball ID  
3K  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
W6  
V6  
2
8K  
72  
4K  
3
U6  
9K  
73  
6K  
4
W7  
V7  
10K  
11J  
10J  
11H  
10H  
11G  
10G  
11F  
10F  
10E  
11E  
11D  
10D  
11C  
10C  
11B  
10B  
11A  
10A  
9C  
74  
2K  
5
75  
2L  
6
U7  
76  
1L  
7
T7  
77  
2 Mbit  
1 Mbit  
2N  
8
V8  
78  
9
U8  
79  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
T8  
80  
1N  
V9  
81  
2P  
U9  
82  
1P  
P6  
83  
2R  
W11  
W10  
V11  
V10  
U11  
U10  
T11  
T10  
R11  
R10  
P11  
P10  
N11  
N10  
M11  
M10  
L11  
L10  
K11  
M6  
84  
1R  
85  
2T  
86  
1T  
87  
2U  
88  
1U  
89  
2V  
90  
1V  
91  
2W  
1W  
6T  
92  
93  
9B  
94  
3U  
9A  
95  
3V  
8D  
96  
4T  
8C  
97  
1F  
5T  
8B  
98  
1G  
2G  
2H  
1H  
2J  
4U  
8A  
99  
4V  
7D  
100  
101  
102  
103  
104  
105  
5W  
5V  
7C  
7B  
5U  
7A  
1J  
Internal  
L6  
6D  
1K  
6N  
J6  
6G  
Note  
14. Bit# 138 is preset HIGH.  
Document #: 38-05353 Rev. *E  
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CY7C1460AV33  
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CY7C1464AV33  
Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the  
device. User guidelines are not tested.  
Neutron Soft Error Immunity  
Test  
Parameter Description  
Typ Max* Unit  
Storage Temperature ................................. –65°C to +150°C  
Conditions  
Ambient Temperature with  
Power Applied ............................................ –55°C to +125°C  
LSBU  
LMBU  
SEL  
Logical  
Single Bit  
Upsets  
25°C  
25°C  
85°C  
361  
394  
FIT/  
Mb  
Supply Voltage on VDD Relative to GND ........–0.5V to +4.6V  
Supply Voltage on VDDQ Relative to GND...... –0.5V to +VDD  
DC to Outputs in Tristate .....................–0.5V to VDDQ + 0.5V  
DC Input Voltage ...................................–0.5V to VDD + 0.5V  
Current into Outputs (LOW)......................................... 20 mA  
Logical Multi  
Bit Upsets  
0
0.01 FIT/  
Mb  
Single Event  
Latch up  
0
0.1  
FIT/  
Dev  
* No LMBU or SEL events occurred during testing; this column represents a  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
2
statistical χ , 95% confidence limit calculation. For more details refer to Appli-  
cation Note AN 54908 “Accelerated Neutron SER Testing and Calculation of  
Terrestrial Failure Rates”  
Latch up Current.................................................... > 200 mA  
Operating Range  
Ambient  
Temperature  
Range  
VDD  
VDDQ  
Commercial 0°C to +70°C  
Industrial –40°C to +85°C  
3.3V  
–5%/+10%  
2.5V –5% to  
VDD  
Electrical Characteristics Over the Operating Range[15, 16]  
DC Electrical Characteristics Over the Operating Range  
Parameter  
VDD  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min  
3.135  
3.135  
2.375  
2.4  
Max  
3.6  
Unit  
V
VDDQ  
VOH  
VOL  
VIH  
VIL  
for 3.3V I/O  
for 2.5V I/O  
VDD  
2.625  
V
V
Output HIGH Voltage  
Output LOW Voltage  
for 3.3V I/O, IOH = −4.0 mA  
for 2.5V I/O, IOH = −1.0 mA  
for 3.3V I/O, IOL = 8.0 mA  
for 2.5V I/O, IOL = 1.0 mA  
V
2.0  
V
0.4  
V
0.4  
VDD + 0.3V  
VDD + 0.3V  
0.8  
V
Input HIGH Voltage[15] for 3.3V I/O  
2.0  
1.7  
V
for 2.5V I/O  
V
Input LOW Voltage[15] for 3.3V I/O  
for 2.5V I/O  
–0.3  
–0.3  
–5  
V
0.7  
V
IX  
Input Leakage Current GND ≤ VI ≤ VDDQ  
except ZZ and MODE  
5
μA  
Input Current of MODE Input = VSS  
Input = VDD  
–30  
–5  
μA  
μA  
μA  
μA  
μA  
5
Input Current of ZZ  
Input = VSS  
Input = VDD  
30  
5
IOZ  
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled  
–5  
Notes  
15. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC)> –2V (Pulse width less than t  
/2).  
IH  
DD  
CYC  
IL  
CYC  
16. T  
: Assumes a linear ramp from 0V to V (Min) within 200 ms. During this time V < V and V  
< V  
.
power up  
DD  
IH  
DD  
DDQ  
DD  
Document #: 38-05353 Rev. *E  
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Electrical Characteristics Over the Operating Range[15, 16]  
DC Electrical Characteristics Over the Operating Range  
Parameter  
IDD  
Description  
Test Conditions  
Min  
Max  
475  
425  
375  
225  
Unit  
mA  
mA  
mA  
mA  
VDD Operating Supply VDD = Max, IOUT = 0 mA,  
f = fMAX = 1/tCYC  
4 ns cycle, 250 MHz  
5 ns cycle, 200 MHz  
6 ns cycle, 167 MHz  
All speed grades  
ISB1  
ISB2  
ISB3  
ISB4  
Automatic CE  
Power down  
Current—TTL Inputs  
Max VDD, Device Deselected,  
VIN ≥ VIH or VIN ≤ VIL, f = fMAX  
1/tCYC  
=
Automatic CE  
Power down  
Current—CMOS Inputs f = 0  
Max VDD, Device Deselected,  
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,  
All speed grades  
All speed grades  
All speed grades  
120  
200  
135  
mA  
mA  
mA  
Automatic CE  
Power down  
Current—CMOS Inputs f = fMAX = 1/tCYC  
Max VDD, Device Deselected,  
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,  
Automatic CE  
Max VDD, Device Deselected,  
Power down  
Current—TTL Inputs  
VIN ≥ VIH or VIN ≤ VIL, f = 0  
Capacitance[17]  
100 TQFP  
Max  
165 FBGA  
209 FBGA  
Max  
Parameter  
Description  
Test Conditions  
Unit  
Max  
CIN  
Input Capacitance  
TA = 25°C, f = 1 MHz,  
6.5  
3
7
7
6
5
5
7
pF  
pF  
pF  
V
DD = 2.5V VDDQ = 2.5V  
CCLK  
CI/O  
Clock Input Capacitance  
Input/Output Capacitance  
5.5  
Thermal Resistance[17]  
100 TQFP  
Package  
165 FBGA  
Package  
209 FBGA  
Package  
Parameters  
Description  
Test Conditions  
Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Testconditionsfollowstandard  
test methods and procedures  
for measuring thermal  
25.21  
20.8  
25.31  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
2.28  
3.2  
4.48  
°C/W  
impedance, per EIA/JESD51.  
Figure 6. AC Test Loads and Waveforms  
3.3V I/O Test Load  
R = 317Ω  
3.3V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R = 351Ω  
≤ 1 ns  
≤ 1 ns  
INCLUDING  
V = 1.5V  
T
(a)  
JIG AND  
SCOPE  
(b)  
(c)  
2.5V I/O Test Load  
OUTPUT  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
ALL INPUT PULSES  
90%  
VDDQ  
90%  
10%  
Z = 50Ω  
0
10%  
L
GND  
5 pF  
R =1538Ω  
≤ 1 ns  
INCLUDING  
JIG AND  
SCOPE  
≤ 1 ns  
V = 1.25V  
T
(a)  
(b)  
(c)  
Note  
17. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05353 Rev. *E  
Page 19 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Switching Characteristics Over the Operating Range [22, 23]  
–250  
–200  
–167  
Unit  
Max  
Parameter  
Description  
Min  
Max  
Min  
Max  
Min  
[18]  
tPower  
VCC (typical) to the first access read or write  
1
1
1
ms  
Clock  
tCYC  
Clock Cycle Time  
Maximum Operating Frequency  
Clock HIGH  
4.0  
5.0  
6.0  
ns  
FMAX  
tCH  
250  
200  
167  
MHz  
ns  
1.5  
1.5  
2.0  
2.0  
2.4  
2.4  
tCL  
Clock LOW  
ns  
Output Times  
tCO  
Data Output Valid After CLK Rise  
OE LOW to Output Valid  
2.6  
2.6  
3.2  
3.0  
3.4  
3.4  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tEOV  
tDOH  
Data Output Hold After CLK Rise  
Clock to High Z[19, 20, 21]  
Clock to Low Z[19, 20, 21]  
1.0  
1.0  
0
1.5  
1.3  
0
1.5  
1.5  
0
tCHZ  
2.6  
2.6  
3.0  
3.0  
3.4  
3.4  
tCLZ  
[19, 20, 21]  
tEOHZ  
tEOLZ  
Setup Times  
tAS  
OE  
HIGH to Output High Z  
OE LOW to Output Low Z[19, 20, 21]  
Address Setup Before CLK Rise  
Data Input Setup Before CLK Rise  
CEN Setup Before CLK Rise  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
tDS  
tCENS  
tWES  
WE, BWx Setup Before CLK Rise  
ADV/LD Setup Before CLK Rise  
Chip Select Setup  
tALS  
tCES  
Hold Times  
tAH  
Address Hold After CLK Rise  
Data Input Hold After CLK Rise  
CEN Hold After CLK Rise  
0.3  
0.3  
0.3  
0.3  
0.3  
0.3  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
tDH  
tCENH  
tWEH  
WE, BWx Hold After CLK Rise  
ADV/LD Hold after CLK Rise  
Chip Select Hold After CLK Rise  
tALH  
tCEH  
Notes  
18. This part has a voltage regulator internally; tpower is the time power needs to be supplied above Vdd minimum initially, before a Read or Write operation can  
be initiated.  
19. t  
, t  
, t  
, and t  
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
EOHZ  
CHZ CLZ EOLZ  
20. At any voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same data  
EOHZ  
EOLZ  
CHZ  
CLZ  
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to  
achieve High Z prior to Low Z under the same system conditions.  
21. This parameter is sampled and not 100% tested.  
22. Timing reference is 1.5V when V  
3.3V and is 1.25V when V  
2.5V.  
DDQ=  
DDQ=  
23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
Document #: 38-05353 Rev. *E  
Page 20 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Switching Waveforms  
Figure 7. Read/Write/Timing[24, 25, 26]  
1
2
3
4
5
6
7
8
9
10  
t
CYC  
t
CLK  
t
t
t
CENS  
CENH  
CL  
CH  
CEN  
t
t
CES  
CEH  
CE  
ADV/LD  
WE  
BW  
x
A1  
A2  
A4  
CO  
A3  
A5  
A6  
A7  
ADDRESS  
t
t
t
t
DS  
DH  
t
t
t
DOH  
OEV  
CLZ  
CHZ  
t
t
AS  
AH  
Data  
D(A1)  
D(A2)  
D(A2+1)  
Q(A3)  
Q(A4)  
Q(A4+1)  
D(A5)  
Q(A6)  
In-Out (DQ)  
t
OEHZ  
t
DOH  
t
OELZ  
OE  
WRITE  
D(A1)  
WRITE  
D(A2)  
BURST  
WRITE  
READ  
Q(A3)  
READ  
Q(A4)  
BURST  
READ  
WRITE  
D(A5)  
READ  
Q(A6)  
WRITE  
D(A7)  
DESELECT  
D(A2+1)  
Q(A4+1)  
DON’T CARE  
UNDEFINED  
Notes  
24. For this waveform ZZ is tied low.  
25. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH,CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.  
Document #: 38-05353 Rev. *E  
Page 21 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Switching Waveforms (continued)  
Figure 8. NOP, STALL and DESELECT Cycles[24, 25, 27]  
1
2
3
4
5
6
7
8
9
10  
CLK  
CEN  
CE  
ADV/LD  
WE  
BWx  
A1  
A2  
A3  
A4  
A5  
ADDRESS  
t
CHZ  
D(A4)  
D(A1)  
Q(A2)  
Q(A3)  
Q(A5)  
Data  
In-Out (DQ)  
WRITE  
D(A1)  
READ  
Q(A2)  
STALL  
READ  
Q(A3)  
WRITE  
D(A4)  
STALL  
NOP  
READ  
Q(A5)  
DESELECT  
CONTINUE  
DESELECT  
DON’T CARE  
UNDEFINED  
Figure 9. ZZ Mode Timing[28, 29]  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes  
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.  
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.  
29. I/Os are in High Z when exiting ZZ sleep mode.  
Document #: 38-05353 Rev. *E  
Page 22 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Ordering Information  
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local  
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at  
http://www.cypress.com/products  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office  
closest to you, visit us at http://www.cypress.com/go/datasheet/offices  
Ordering Information  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Part and Package Type  
Ordering Code  
167 CY7C1460AV33-167AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
CY7C1462AV33-167AXC  
Commercial  
CY7C1460AV33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1464AV33-167BGI  
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
lndustrial  
Commercial  
Commercial  
200 CY7C1460AV33-200AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
250 CY7C1460AV33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
CY7C1460AV33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1460AV33-250AXI  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
Industrial  
Document #: 38-05353 Rev. *E  
Page 23 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Package Diagrams  
Figure 10. 100-Pin TQFP (14 x 20 x 1.4 mm)  
16.00 0.20  
1.40 0.05  
14.00 0.10  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
0.25  
1. JEDEC STD REF MS-026  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
51-85050 *B  
1.00 REF.  
DETAIL  
A
Document #: 38-05353 Rev. *E  
Page 24 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Package Diagrams (continued)  
Figure 11. 165-Ball FBGA (15 x 17 x 1.4 mm)  
51-85165 *B  
Document #: 38-05353 Rev. *E  
Page 25 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Package Diagrams (continued)  
Figure 12. 209-Ball FBGA (14 x 22 x 1.76 mm)  
51-85167 **  
Document #: 38-05353 Rev. *E  
Page 26 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Document History Page  
Document Title: CY7C1460AV33/CY7C1462AV33/CY7C1464AV33, 36 Mbit (1M x 36/2M x 18/512K x 72)  
Pipelined SRAM with NoBL™ Architecture  
Document Number: 38-05353  
Orig. of Submission  
Revision ECN  
Description of Change  
Change  
Date  
**  
254911  
SYT  
See ECN New Data sheet  
Part number changed from previous revision. New and old part number differ by the  
letter “A”  
*A  
303533  
SYT  
See ECN Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA on  
Page # 5  
Changed the test condition from VDD = Min to VDD = Max for VOL in the Electrical  
Characteristics table  
Replaced ΘJA and ΘJC from TBD to respective Thermal Values for All Packages on  
the Thermal Resistance Table  
Changed IDD from 450, 400 and 350 mA to 475, 425 and 375 mA for 250, 200 and  
167 MHz respectively  
Changed ISB1 from 190, 180 and 170 mA to 225 mA for 250, 200 and 167 MHz  
respectively  
Changed ISB2 from 80 mA to 100 mA for all frequencies  
Changed ISB3 from 180, 170 and 160 mA to 200 mA for 250, 200 and 167 MHz  
respectively  
Changed ISB4 from 100 mA to 110 mA for all frequencies  
Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP Package  
Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 MHz Speed Bin  
Added Pb-Free information for 100-pin TQFP and 165 FBGA and 209 BGA packages  
*B  
*C  
331778  
417509  
SYT  
RXU  
See ECN Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA Package  
as per JEDEC standards and updated the Pin Definitions accordingly  
Modified VOL, VOH test conditions  
Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA Package  
Added Industrial Temperature Grade  
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively  
Updated the Ordering Information by Shading and Unshading MPNs as per availability  
See ECN Converted from Preliminary to Final  
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901  
North First Street” to “198 Champion Court”  
Changed IX current value in MODE from –5 and 30 μA to –30 and 5 μA respectively  
and also Changed IX current value in ZZ from –30 and 5 μA to –5 and 30 μA respec-  
tively on page# 18  
Modified test condition from VIH < VDD to VIH < VDD  
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the  
Electrical Characteristics Table  
Replaced Package Name column with Package Diagram in the Ordering  
Information table  
Replaced Package Diagram of 51-85050 from *A to *B  
*D  
*E  
473229  
NXR  
VKN  
See ECN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND  
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching  
Characteristics table  
Updated the Ordering Information table.  
2756998  
08/28/09 Included Soft Error Immunity Data  
Modified Ordering Information table by including parts that are available and modified  
the disclaimer for the Ordering information.  
Updated Package Diagram for spec 51-85165.  
Document #: 38-05353 Rev. *E  
Page 27 of 28  
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CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
psoc.cypress.com  
clocks.cypress.com  
wireless.cypress.com  
memory.cypress.com  
image.cypress.com  
Clocks & Buffers  
Wireless  
Memories  
Image Sensors  
© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 38-05353 Rev. *E  
Revised August 27, 2009  
Page 28 of 28  
®
TM  
TM  
QDR is the registered trademark and NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be  
the trademarks of their respective holders.  
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