CY7C1460KV25-200BZI [CYPRESS]
36-Mbit (1M à 36/2M à 18) Pipelined SRAM with NoBL⢠Architecture (With ECC);
| 型号： | CY7C1460KV25-200BZI |
| 厂家： | 
CYPRESS |
| 描述： | 36-Mbit (1M à 36/2M à 18) Pipelined SRAM with NoBL⢠Architecture (With ECC) 静态存储器 内存集成电路 |
| 文件： | 总32页 (文件大小：830K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
36-Mbit (1M × 36/2M × 18)
Pipelined SRAM
with NoBL™ Architecture (With ECC)
36-Mbit (1M
× 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
Functional Description
The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 are 2.5 V, 1M × 36/2M × 18 synchronous
pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic,
respectively. They are designed to support unlimited true
back-to-back read/write operations with no wait states. The
CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 are equipped with the advanced NoBL logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data in systems that require frequent
write/read transitions. The CY7C1460KV25/CY7C1462KV25/
CY7C1460KVE25/CY7C1462KVE25 are pin-compatible and
functionally equivalent to ZBT devices.
■ Pin-compatible and functionally equivalent to ZBT™
■ Supports 250 MHz bus operations with zero wait states
❐ Availablespeedgradesare250MHz, 200MHz, and167MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte Write capability
■ 2.5 V core power supply
■ 2.5 V I/O power supply
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the byte write selects
■ Fast clock-to-output times
❐ 2.5 ns (for 250 MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
BWa–BWd
for
CY7C1460KV25/CY7C1460KVE25
and
■ CY7C1460KV25, CY7C1462KV25, CY7C1460KVE25 and
CY7C1462KVE25 available in JEDEC-standard Pb-free
100-pin TQFP, and Pb-free and non Pb-free 165-ball FBGA
packages.
BWa–BWb for CY7C1462KV25/CY7C1462KVE25 and a write
enable (WE) input. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ Burst capability — linear or interleaved burst order
■ “ZZ” sleep mode option
■ On-chip error correction code (ECC) to reduce soft error rate
(SER)
Selection Guide
Description
Maximum access time
250 MHz
2.5
200 MHz
3.2
167 MHz Unit
3.4
170
190
ns
Maximum operating current
× 18
× 36
220
190
mA
240
210
Cypress Semiconductor Corporation
Document Number: 001-66679 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 7, 2018
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Logic Block Diagram – CY7C1460KV25
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
ADV/LD
CLK
CEN
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
WRITE
DRIVERS
BW
BW
a
a
b
c
d
A
M
P
b
BW
BW
c
S
T
E
R
S
F
d
E
R
S
S
WE
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1462KV25
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
Q1
Q0
BURST
LOGIC
D0
MODE
ADV/LD
C
CLK
CEN
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
MEMORY
ARRAY
E
B
U
F
DQs
DQP
DQP
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
a
F
b
S
T
E
R
S
b
E
R
S
S
N
G
WE
E
E
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Document Number: 001-66679 Rev. *J
Page 2 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Logic Block Diagram – CY7C1460KVE25
ADDRESS
A0, A1, A
REGISTER 0
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
O
S
U
D
A
T
E
C
C
U
T
T
P
U
T
E
N
S
P
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
D
E
R
E
G
I
MEMORY
ARRAY
B
U
F
F
E
R
S
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
WRITE
DRIVERS
BW
BW
BW
BW
A
C
O
D
E
A
B
B
C
A
M
P
S
T
E
R
S
C
D
D
S
WE
R
E
E
N
G
ECC
ENCODER
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Document Number: 001-66679 Rev. *J
Page 3 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Logic Block Diagram – CY7C1462KVE25
ADDRESS
A0, A1, A
REGISTER 0
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
O
U
T
P
U
T
S
E
E
C
C
P
U
T
D
A
T
ADV/LD
N
S
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
MEMORY
ARRAY
D
E
B
U
F
F
E
R
S
DQs
DQP
DQP
WRITE
DRIVERS
BW
A
S
T
E
E
R
I
A
M
P
C
O
D
E
A
B
BW
B
S
T
E
R
S
S
R
N
G
WE
E
E
ECC
ENCODER
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Document Number: 001-66679 Rev. *J
Page 4 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Contents
Pin Configurations ...........................................................6
Pin Definitions ..................................................................8
Functional Overview ........................................................9
Single Read Accesses ................................................9
Burst Read Accesses ..................................................9
Single Write Accesses ...............................................10
Burst Write Accesses ................................................10
Sleep Mode ...............................................................10
On-Chip ECC ............................................................10
Interleaved Burst Address Table ...............................11
Linear Burst Address Table .......................................11
ZZ Mode Electrical Characteristics ............................11
Truth Table ......................................................................12
Partial Write Cycle Description .....................................13
Partial Write Cycle Description .....................................13
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................14
Disabling the JTAG Feature ......................................14
Test Access Port (TAP) .............................................14
PERFORMING A TAP RESET ..................................14
TAP REGISTERS ......................................................14
TAP Instruction Set ...................................................15
TAP Controller State Diagram .......................................16
TAP Controller Block Diagram ......................................16
TAP Timing ......................................................................16
TAP AC Switching Characteristics ...............................17
2.5 V TAP AC Test Conditions .......................................18
2.5 V TAP AC Output Load Equivalent .........................18
TAP DC Electrical Characteristics
Identification Register Definitions ................................19
Scan Register Sizes .......................................................19
Identification Codes .......................................................19
Boundary Scan Order ....................................................20
Maximum Ratings ...........................................................21
Operating Range .............................................................21
Neutron Soft Error Immunity .........................................21
Electrical Characteristics ...............................................21
Capacitance ....................................................................23
Thermal Resistance ........................................................23
AC Test Loads and Waveforms .....................................23
Switching Characteristics ..............................................24
Switching Waveforms ....................................................25
Ordering Information ......................................................27
Ordering Code Definitions .........................................27
Package Diagrams ..........................................................28
Acronyms ........................................................................30
Document Conventions .................................................30
Units of Measure .......................................................30
Document History Page .................................................31
Sales, Solutions, and Legal Information ......................32
Worldwide Sales and Design Support .......................32
Products ....................................................................32
PSoC® Solutions ......................................................32
Cypress Developer Community .................................32
Technical Support .....................................................32
and Operating Conditions .............................................18
Document Number: 001-66679 Rev. *J
Page 5 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Pin Configurations
Figure 1. 100-pin TQFP Pinout
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
V
DDQ
V
V
DDQ
DDQ
V
V
V
SS
V
SS
SS
SS
DQc
DQc
NC
NC
NC
DQb
DQb
DQb
DQb
DQPa
DQa
DQa
DQc
DQc
DQb
DQb
9
9
V
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
V
DDQ
DDQ
V
V
DQa
DQa
DDQ
DDQ
DQc
DQc
NC
DQb
DQb
DQb
DQb
NC
V
V
SS
CY7C1460KV25/CY7C1460KVE25
(1M × 36)
SS
V
V
DD
NC
DD
NC
CY7C1462KV25
(2M × 18)
NC
NC
V
V
DD
DD
V
V
SS
SS
ZZ
ZZ
DQa
DQa
DQd
DQb
DQb
DQa
DQa
DQd
V
V
DDQ
DDQ
V
V
DDQ
DDQ
V
V
SS
V
SS
V
SS
SS
DQd
DQd
DQd
DQd
DQa
DQa
DQb
DQb
DQa DQPb
DQa
DQa
NC
DQa
NC
NC
V
SS
V
V
V
SS
SS
SS
V
V
DDQ
DDQ
V
V
DDQ
DDQ
DQd
DQd
DQPd
DQa
DQa
DQPa
NC
NC
NC
NC
NC
NC
Document Number: 001-66679 Rev. *J
Page 6 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Pin Configurations (continued)
Figure 2. 165-ball FBGA Pinout
CY7C1460KV25/CY7C1460KVE25 (1M × 36)
1
2
A
3
4
5
6
7
8
ADV/LD
OE
9
A
10
A
11
NC
NC/576M
NC/1G
DQPc
A
B
C
D
CE1
CE2
BWc
BWd
VSS
VDD
BWb
BWa
VSS
VSS
CE3
CLK
VSS
VSS
CEN
WE
A
A
A
NC
NC
DQc
VDDQ
VDDQ
VSS
VSS
VSS
VDDQ
VDDQ
NC
DQb
DQPb
DQb
DQc
VDD
DQc
DQc
DQc
NC
DQc
DQc
DQc
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
E
F
G
H
J
DQd
DQd
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
K
L
DQd
DQd
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
DQa
DQPa
M
N
P
DQPd
NC/144M NC/72M
TDI
TDO
NC/288M
A
MODE
A
A
TMS
A0
TCK
A
A
A
A
R
CY7C1462KV25/CY7C1462KVE25 (2M × 18)
1
NC/576M
NC/1G
NC
2
A
3
4
5
NC
6
7
8
9
A
10
A
11
A
A
B
C
D
CE1
CE2
BWb
NC
CE3
CLK
VSS
VSS
CEN
ADV/LD
NC
A
BWa
VSS
VSS
A
A
WE
VSS
VSS
OE
VSS
VDD
NC
DQb
VDDQ
VDDQ
VSS
VDD
VDDQ
VDDQ
NC
NC
DQPa
DQa
NC
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQa
DQa
DQa
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
NC
NC
NC
K
L
NC
NC
DQb
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
NC
NC
M
N
P
DQPb
NC/144M NC/72M
TDI
TDO
NC/288M
A
MODE
A
A
TMS
A0
TCK
A
A
A
A
R
Document Number: 001-66679 Rev. *J
Page 7 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
Input-synchronous
Address inputs used to select one of the address locations. Sampled at the rising
edge of the CLK.
BWa, BWb, BWc, BWd Input-synchronous
Byte write select inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb
controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd
WE
Input-synchronous
Input-synchronous
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
ADV/LD
Advance/load input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
CLK
CE1
CE2
CE3
OE
Input-clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Input-synchronous
Input-synchronous
Input-synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
Input-asynchronous Output enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
CEN
Input-synchronous
Clock enable input, active LOW. When asserted LOW the clock signal is recognized
by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting
CEN does not deselect the device, CEN can be used to extend the previous cycle
when required.
DQa, DQb, DQc, DQd I/O-synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained in
the memory location specified by AX during the previous read cycle. The direction of
the pins is controlled by OE and the internal control logic. When OE is asserted LOW,
the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tristate
condition. The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when
the device is deselected, regardless of the state of OE.
DQPa, DQPb, DQPc, I/O-synchronous
DQPd
Bidirectional data parity I/O lines. Functionally, these signals are identical to
DQ[31:0]. During write sequences, DQPa is controlled by BWa, DQPb is controlled by
BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled
by BWe, DQPf is controlled by BWf, DQPg is controlled by BWg, DQPh is controlled
by BWh.
MODE
TDO
Input strap pin
Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change
states during operation. When left floating MODE will default HIGH, to an interleaved
burst order.
JTAG serial output
synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Document Number: 001-66679 Rev. *J
Page 8 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
TDI
JTAG serial input
synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
TMS
Test mode select
synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge
of TCK.
TCK
VDD
VDDQ
VSS
NC
JTAG-clock
Clock input to the JTAG circuitry.
Power supply
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
I/O power supply
Ground
N/A
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
NC/72M
NC/144M
NC/288M
NC/576M
NC/1G
N/A
N/A
N/A
N/A
N/A
ZZ
Input-asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved. During normal operation, this pin has
to be LOW or left floating. ZZ pin has an internal pull-down.
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
Functional Overview
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 2.5 ns (200-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will tristate following the next clock rise.
The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 are synchronous-pipelined burst NoBL
SRAMs designed specifically to eliminate wait states during
write/read transitions. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. The clock
signal is qualified with the clock enable input signal (CEN). If
CEN is HIGH, the clock signal is not recognized and all internal
states are maintained. All synchronous operations are qualified
with CEN. All data outputs pass through output registers
controlled by the rising edge of the clock. Maximum access delay
from the clock rise (tCO) is 2.5 ns (250 MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[x] can be used to conduct byte write
operations.
Burst Read Accesses
The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 have an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
reads without reasserting the address inputs. ADV/LD must be
driven LOW in order to load a new address into the SRAM, as
described in the Single Read Accesses section above. The
sequence of the burst counter is determined by the MODE input
signal. A LOW input on MODE selects a linear burst mode, a
HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
Document Number: 001-66679 Rev. *J
Page 9 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
CY7C1462KVE25) are automatically three-stated during the
data portion of a write cycle, regardless of the state of OE.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address inputs is
loaded into the address register. The write signals are latched
into the control logic block.
Burst Write Accesses
The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 have an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
WRITE operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial address,
as described in the Single Write Accesses section above. When
ADV/LD is driven HIGH on the subsequent clock rise, the chip
enables (CE1, CE2, and CE3) and WE inputs are ignored and the
burst counter is incremented. The correct BW (BWa,b,c,d for
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1460KV25/CY7C1460KVE25
and DQa,b/DQPa,b for CY7C1462KV25/CY7C1462KVE25). In
addition, the address for the subsequent access
(read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
CY7C1460KV25/CY7C1460KVE25
and
BWa,b
for
CY7C1462KV25/CY7C1462KVE25) inputs must be driven in
each cycle of the burst write in order to write the correct bytes of
data.
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1460KV25/CY7C1460KVE25
and DQa,b/DQPa,b for CY7C1462KV25/CY7C1462KVE25) (or a
subset for byte write operations, see Write Cycle Description
table for details) inputs is latched into the device and the write is
complete.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1460KV25/CY7C1460KVE25 and BWa,b for
CY7C1462KV25/CY7C1462KVE25)
signals.
The
CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 provides byte write capability that is described
in the Write Cycle Description table. Asserting the write enable
input (WE) with the selected byte write select (BW) input will
selectively write to only the desired bytes. Bytes not selected
during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided to
simplify the write operations. Byte write capability has been
included in order to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write
operations.
On-Chip ECC
CY7C1460KVE25/CY7C1462KVE25 SRAMs include an on-chip
ECC algorithm that detects and corrects all single-bit memory
errors, including Soft Error Upset (SEU) events induced by
cosmic rays, alpha particles etc. The resulting Soft Error Rate
(SER) of these devices is anticipated to be <0.01 FITs/Mb a
4-order-of-magnitude improvement over comparable SRAMs
with no On-Chip ECC, which typically have an SER of
200 FITs/Mb or more. To protect the internal data, ECC parity bits
(invisible to the user) are used.
Because the CY7C1460KV25/CY7C1462KV25/
CY7C1460KVE25/CY7C1462KVE25 are common I/O devices,
data should not be driven into the device while the outputs are
active. The output enable (OE) can be deasserted HIGH before
presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1460KV25/CY7C1460KVE25 and DQa,b/DQPa,b for
CY7C1462KV25/CY7C1462KVE25) inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ and
DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1460KV25/
The
ECC
algorithm
does
not
correct
multi-bit
errors.However,Cypress SRAMs are architected in such a way
that a single SER event has a very low probability of causing a
multi-bit error across any data word. The extreme rarity of
multi-bit errors results in a SER of <0.01 FITs/Mb.
CY7C1460KVE25 and DQa,b/DQPa,b for CY7C1462KV25/
Document Number: 001-66679 Rev. *J
Page 10 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Interleaved Burst Address Table
(MODE = Floating or VDD
Linear Burst Address Table
)
(MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
Unit
mA
ns
ZZ VDD 0.2 V
ZZVDD 0.2 V
ZZ 0.2 V
–
75
2tCYC
–
tZZS
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ Inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 001-66679 Rev. *J
Page 11 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Truth Table
The Truth Table for CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/CY7C1462KVE25 is as follows [1, 2, 3, 4, 5, 6, 7]
.
WE
X
X
H
X
H
X
L
Operation
Address Used CE ZZ ADV/LD
BWx OE CEN CLK
DQ
Deselect cycle
None
H
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
X
X
X
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L
L
H
X
L–H
L–H
Tristate
Tristate
Continue deselect cycle
None
Read cycle (begin burst)
External
Next
L–H Data out (Q)
L–H Data out (Q)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
X
L
H
L
L
External
Next
H
H
X
X
X
X
X
X
L–H
L–H
Tristate
Tristate
X
L
H
L
External
Next
L–H Data in (D)
L–H Data in (D)
Write cycle (continue burst)
NOP/WRITE ABORT (begin burst)
WRITE ABORT (continue burst)
IGNORE CLOCK EDGE (stall)
Sleep MODE
X
L
H
L
X
L
L
None
H
H
X
X
L–H
L–H
L–H
X
Tristate
Tristate
–
Next
X
X
X
H
X
X
X
X
X
Current
None
Tristate
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW . See Write Cycle Description table for details.
X
3. When a write cycle is detected, all I/Os are tristated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tristate condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ and DQP = Three-state when OE is
s
X
inactive or when the device is deselected, and DQ =data when OE is active.
s
Document Number: 001-66679 Rev. *J
Page 12 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Partial Write Cycle Description
The Partial Write Cycle Description for CY7C1460KV25/CY7C1460KVE25 is as follows [8, 9, 10, 11]
.
Function (CY7C1460KV25/CY7C1460KVE25)
WE
H
L
BWd
X
H
H
H
H
H
H
H
H
L
BWc
X
BWb
X
H
H
L
BWa
X
H
L
Read
Write – no bytes written
Write byte a – (DQa and DQPa)
Write byte b – (DQb and DQPb)
Write bytes b, a
H
H
H
H
L
L
L
H
L
L
L
Write byte c – (DQc and DQPc)
Write bytes c, a
L
H
H
L
H
L
L
L
Write bytes c, b
L
LL
L
H
L
Write bytes c, b, a
L
L
Write byte d – (DQd and DQPd)
Write bytes d, a
L
H
H
H
H
L
H
H
L
H
L
L
L
Write bytes d, b
L
L
H
L
Write bytes d, b, a
L
L
L
Write bytes d, c
L
L
H
H
L
H
L
Write bytes d, c, a
L
L
L
Write bytes d, c, b
L
L
L
H
L
Write all bytes
L
L
L
L
Partial Write Cycle Description
The Partial Write Cycle Description for CY7C1462KV25/CY7C1462KVE25 is as follows[8, 9, 10, 11]
.
Function (CY7C1462KV25/CY7C1462KVE25)
WE
H
L
BWb
X
BWa
X
Read
Write – no bytes written
Write byte a – (DQa and DQPa)
Write byte b – (DQb and DQPb)
Write both bytes
H
H
L
H
L
L
L
H
L
L
L
Notes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
9. Write is defined by WE and BW . See Write Cycle Description table for details.
X
10. When a write cycle is detected, all I/Os are tristated, even during byte writes.
11. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document Number: 001-66679 Rev. *J
Page 13 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
TAP Registers
IEEE 1149.1 Serial Boundary Scan (JTAG)
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 2.5 V I/O logic level.
The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 16. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Test Access Port (TAP)
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
SRAM with minimal delay. The bypass register is set LOW (VSS
)
when the BYPASS instruction is executed.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the Boundary
Scan Register for the SRAM in different packages is listed in the
Scan Register Sizes on page 19.
Test Data-In (TDI)
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register (see TAP Controller Block Diagram on page 16).
The Boundary Scan Order on page 20 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register (see TAP Controller State Diagram on page 16).
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 19.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
Document Number: 001-66679 Rev. *J
Page 14 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
EXTEST Output Bus Tristate
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tristate,” is latched into the preload register
during the “Update-DR” state in the TAP controller, it will directly
control the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable the
output buffers to drive the output bus. When LOW, this bit will
place the output bus into a high Z condition.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is preset
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the clock captured in the boundary scan
register.
Document Number: 001-66679 Rev. *J
Page 15 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
TAP Controller State Diagram
TAP Controller Block Diagram
TEST-LOGIC
1
0
RESET
0
Bypass Register
2
1
0
0
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
Selection
Circuitry
Instruction Register
31 30 29
Selection
TDI
TDO
0
0
Circuitr
y
.
.
. 2 1
1
1
CAPTURE-DR
CAPTURE-IR
Identification Register
x
.
.
.
.
. 2 1
0
0
Boundary Scan Register
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
TAP CONTROLLER
0
0
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 001-66679 Rev. *J
Page 16 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
TAP AC Switching Characteristics
Over the Operating Range
Parameter [12, 13]
Clock
Description
Min
Max
Unit
tTCYC
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
–
0
10
–
ns
ns
tTDOX
Set-up Times
tTMSS
TMS set-up to TCK clock rise
TDI set-up to TCK clock rise
Capture set-up to TCK rise
5
5
5
–
–
–
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
Notes
12. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
13. Test conditions are specified using the load in TAP AC test Conditions. t /t = 2 V/ns (Slew Rate).
R
F
Document Number: 001-66679 Rev. *J
Page 17 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
2.5 V TAP AC Test Conditions
2.5 V TAP AC Output Load Equivalent
1.25V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall times (Slew Rate) ........................... 2 V/ns
Input timing reference levels .......................................1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ..........................1.25 V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)[14]
Parameter
VOH1
Description
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input load current
Test Conditions
VDDQ = 2.5 V
Min
1.7
2.1
–
Max
Unit
V
IOH = –1.0 mA
IOH = –100 A
IOL = 1.0 mA
IOL = 100 A
–
–
VOH2
VOL1
VOL2
VIH
VDDQ = 2.5 V
VDDQ = 2.5 V
VDDQ = 2.5 V
VDDQ = 2.5 V
VDDQ = 2.5 V
–
–
0.4
V
V
–
0.2
V
1.7
–0.3
–5
VDD + 0.3
0.7
V
VIL
–
V
IX
GND VI VDDQ
5
A
Note
14. All voltages referenced to V (GND).
SS
Document Number: 001-66679 Rev. *J
Page 18 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Identification Register Definitions
CY7C1460KV25/
CY7C1460KVE25
(1M × 36)
CY7C1462KV25/
CY7C1462KVE25
(2M × 18)
Instruction Field
Description
Revision number (31:29)
000
01011
000
01011
Describes the version number
Device depth (28:24)
Reserved for internal use
Architecture/memory type(23:18)
Bus width/density(17:12)
001000
100111
00000110100
1
001000
010111
00000110100
1
Defines memory type and architecture
Defines width and density
Cypress JEDEC ID code (11:1)
ID register presence indicator (0)
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (× 36)
Bit Size (× 18)
Instruction
Bypass
ID
3
1
3
1
32
89
32
89
Boundary scan order (165-ball FBGA package)
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to high Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 001-66679 Rev. *J
Page 19 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Boundary Scan Order
165-ball FBGA[15]
CY7C1460KV25/CY7C1460KVE25 (1M × 36), CY7C1462KV25/CY7C1462KVE25 (2M × 18)
Bit#
1
Ball ID
N6
Bit#
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ball ID
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
Bit#
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
Bit#
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
N1
2
N7
N2
3
N10
P11
P8
P1
4
R1
5
R2
6
R8
P3
7
R9
R3
8
P9
P2
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
R4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P4
G1
D2
E2
F2
N5
P6
B9
R6
C10
A8
Internal
G2
H1
H3
J1
B8
A7
B7
B6
K1
L1
A6
B5
M1
J2
A5
H10
G11
F11
A4
K2
L2
B4
B3
M2
Note
15. Bit# 89 is preset HIGH.
Document Number: 001-66679 Rev. *J
Page 20 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Maximum Ratings
Operating Range
Ambient
Exceeding maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Range
VDD
VDDQ
Temperature
0 °C to +70 °C
–40 °C to +85 °C
Commercial
Industrial
2.5 V+ 5% 2.5 V – 5% to
Storage temperature ................................ –65 °C to +150 °C
VDD
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +3.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC to outputs in tristate ....................–0.5 V to VDDQ + 0.5 V
DC input voltage .................................–0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Neutron Soft Error Immunity
Test
Parameter Description
Conditions
Typ Max* Unit
LSBU
Logical
Single-Bit
Upsets
25 °C
<5
5
FIT/
Mb
(Device
without
ECC)
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch-up current ................................................... > 200 mA
LSBU
0
0
0
0.01 FIT/
Mb
(Device with
ECC)
LMBU (All
Devices)
Logical
Multi-Bit
Upsets
25 °C
85 °C
0.01 FIT/
Mb
SEL (All
Devices)
Single Event
Latch up
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [16, 17]
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
2.375
2.375
2.0
Max
Unit
V
VDD
VDDQ
VOH
VOL
VIH
–
2.625
for 2.5 V I/O
VDD
V
Output HIGH voltage
Output LOW voltage
Input HIGH voltage [16]
Input LOW voltage [16]
for 2.5 V I/O, IOH =1.0 mA
for 2.5 V I/O, IOL =1.0 mA
for 2.5 V I/O
–
V
–
0.4
V
1.7
VDD + 0.3 V
V
VIL
for 2.5 V I/O
–0.3
–5
0.7
5
V
IX
Input leakage current except ZZ GND VI VDDQ
and MODE
A
Input current of MODE
Input = VSS
–30
–
–
5
A
A
A
A
A
Input = VDD
Input current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
Output leakage current
GND VI VDDQ, output disabled
-5
Notes
16. Overshoot: V (AC) < V +1.5 V (Pulse width less than t
/2), undershoot: V (AC) > –2 V (Pulse width less than t
/2).
CYC
IH
DD
CYC
IL
17. T
: Assumes a linear ramp from 0 V to V (min) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document Number: 001-66679 Rev. *J
Page 21 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Electrical Characteristics (continued)
Over the Operating Range
Parameter [16, 17]
Description
Test Conditions
4-ns cycle,
Min
–
Max
220
240
190
210
170
190
85
Unit
IDD
VDD operating supply
VDD = Max,
× 18
× 36
× 18
× 36
× 18
× 36
× 18
× 36
× 18
× 36
× 18
× 36
× 18
× 36
mA
IOUT = 0 mA,
f = fMAX = 1/tCYC
250 MHz
–
5-ns cycle,
200 MHz
–
mA
mA
mA
mA
mA
mA
–
6-ns cycle,
167 MHz
–
–
ISB1
Automatic CE power-down
current – TTL inputs
Max VDD
,
4-ns cycle,
250 MHz
–
device deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
–
90
5-ns cycle,
200 MHz
–
85
–
90
6-ns cycle,
167 MHz
–
85
–
90
ISB2
Automatic CE power-down
current – CMOS inputs
Max VDD
,
All speeds
–
75
device deselected,
80
VIN 0.3 V or
V
f = 0
IN > VDDQ 0.3 V,
ISB3
Automatic CE power-down
current – CMOS inputs
Max VDD
,
4-ns cycle,
250 MHz
× 18
× 36
× 18
× 36
× 18
× 36
× 18
× 36
–
–
–
85
90
85
90
85
90
75
80
mA
mA
mA
device deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f = fMAX = 1/tCYC
5-ns cycle,
200 MHz
6-ns cycle,
167 MHz
ISB4
Automatic CE power-down
current – TTL inputs
Max VDD
,
All speed
grades
–
–
mA
mA
device deselected,
VIN VIH or VIN VIL,
f = 0
Document Number: 001-66679 Rev. *J
Page 22 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Capacitance
100-pin TQFP 165-ballFBGA
Parameter [18]
Description
Input capacitance
Test Conditions
Unit
Max
Max
CIN
TA = 25 °C, f = 1 MHz,
VDD = 2.5 V VDDQ = 2.5 V
5
5
5
5
5
5
pF
pF
pF
CCLK
CI/O
Clock input capacitance
Input/output capacitance
Thermal Resistance
100-pin TQFP 165-ballFBGA
Parameter [18]
Description
Test Conditions
Unit
Package
35.36
31.30
28.86
7.52
Package
14.24
12.47
11.40
JA
Thermal resistance
(junction to ambient)
Test
conditions With Still Air (0 m/s)
°C/W
°C/W
°C/W
°C/W
follow standard test
With Air Flow (1 m/s)
methods
procedures
and
for With Air Flow (3 m/s)
measuring thermal
JC
JB
Thermal resistance
(junction to case)
–
3.92
impedance,
per
EIA/JESD51.
Thermal resistance
(junction to board)
28.89
7.19
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
10%
L
GND
5 pF
R = 1538
INCLUDING
JIG AND
SCOPE
1 ns
2 V/ns
V = 1.25 V
T
(a)
(b)
(c)
Note
18. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-66679 Rev. *J
Page 23 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Switching Characteristics
Over the Operating Range
–250
–200
–167
Parameter [19, 20]
Description
Unit
Min
Max
Min
Max
Min
Max
[21]
tPower
VCC (typical) to the first access read or write
1
–
1
–
1
–
ms
Clock
tCYC
Clock cycle time
Maximum operating frequency
Clock HIGH
4.0
–
–
250
–
5.0
–
–
200
–
6.0
–
–
167
–
ns
MHz
ns
FMAX
tCH
1.5
1.5
2.0
2.0
2.4
2.4
tCL
Clock LOW
–
–
–
ns
Output Times
tCO
Data output valid after CLK rise
OE LOW to output valid
–
–
2.5
2.6
–
–
–
3.2
3.0
–
–
–
3.4
3.4
–
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
Data output hold after CLK rise
Clock to high Z [22, 23, 24]
Clock to low Z [22, 23, 24]
OE HIGH to output high Z [22, 23, 24]
OE LOW to output low Z [22, 23, 24]
1.0
–
1.5
–
1.5
–
tCHZ
2.6
–
3.0
–
3.4
–
tCLZ
1.0
–
1.3
–
1.5
–
tEOHZ
tEOLZ
Set-up Times
tAS
2.6
–
3.0
–
3.4
–
0
0
0
Address set-up before CLK rise
Data input set-up before CLK rise
CEN set-up before CLK rise
1.2
1.2
1.2
1.2
1.2
1.2
–
–
–
–
–
–
1.4
1.4
1.4
1.4
1.4
1.4
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDS
tCENS
tWES
WE, BWx set-up before CLK rise
ADV/LD set-up before CLK rise
Chip select set-up
tALS
tCES
Hold Times
tAH
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
0.3
0.3
0.3
0.3
0.3
0.3
–
–
–
–
–
–
0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
WE, BWx hold after CLK rise
ADV/LD hold after CLK rise
Chip select hold after CLK rise
tALH
tCEH
Notes
19. Timing reference is 1.25 V when V
= 2.5 V.
DDQ
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
21. This part has a voltage regulator internally; t is the time power needs to be supplied above V minimum initially, before a read or write operation can be initiated.
power
DD
22. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of Figure 3 on page 23. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ EOLZ
EOHZ
23. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
CLZ
EOHZ
EOLZ
CHZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
24. This parameter is sampled and not 100% tested.
Document Number: 001-66679 Rev. *J
Page 24 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Switching Waveforms
Figure 4. Read/Write/Timing [25, 26, 27]
1
2
3
4
5
6
7
8
9
10
t
CYC
CLK
t
t
t
t
CENS CENH
CL
CH
CEN
t
t
CEH
CES
CE
ADV/LD
WE
BW
x
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
DH
t
DS
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Figure 5. NOP, STALL and DESELECT Cycles [25, 26, 28]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
Notes
25. For this waveform ZZ is tied low.
26. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
27. Order of the burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved). Burst operations are optional.
28. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 001-66679 Rev. *J
Page 25 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [29, 30]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
29. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
30. I/Os are in high Z when exiting ZZ sleep mode.
Document Number: 001-66679 Rev. *J
Page 26 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Ordering Information
Table 1 lists the ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking
for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the
product summary page at http://www.cypress.com/products.
Table 1. Ordering Information
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
250 CY7C1460KV25-250AXC
CY7C1462KV25-250BZXC
CY7C1460KV25-250BZC
CY7C1460KVE25-250AXC
200 CY7C1460KV25-200BZXI
CY7C1460KV25-200BZI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
165-ball FBGA (15 × 17 × 1.4 mm)
Commercial
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
165-ball FBGA (15 × 17 × 1.4 mm)
Industrial
CY7C1460KVE25-200BZXI
CY7C1462KV25-200AXC
167 CY7C1460KV25-167AXC
CY7C1460KVE25-167AXC
CY7C1460KV25-167BZXI
CY7C1460KV25-167BZC
CY7C1462KV25-167BZI
165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
165-ball FBGA (15 × 17 × 1.4 mm)
Commercial
Industrial
Commercial
Industrial
165-ball FBGA (15 × 17 × 1.4 mm)
CY7C1462KVE25-167BZI
165-ball FBGA (15 × 17 × 1.4 mm)
Ordering Code Definitions
-
XXX XX
X X
25
CY
7
C
14XX
KV
E
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = -40 °C to +85 °C
X = Pb-free; X Absent = Leaded
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 167 MHz or 200 MHz or 250 MHz
25 = 2.5 V VDD
E = Device with ECC; E Absent = Device without ECC
Process Technology: KV = 65 nm
Part Identifier: 14XX = 1460 or 1462
1460 = PL, 1M × 36 (36-Mbit)
1462 = PL, 2M × 18 (36-Mbit)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-66679 Rev. *J
Page 27 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș 2
ș
1
ș
DIMENSIONS
MIN. NOM. MAX.
1.60
NOTE:
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
MOLD PROTRUSION/END FLASH SHALL
A
0.05
0.15
A1
A2
D
1.35 1.40 1.45
15.80 16.00 16.20
13.90 14.00 14.10
21.80 22.00 22.20
19.90 20.00 20.10
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
D1
E
E1
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
0.08
0.08
0°
R
R
ș
0.20
0.20
7°
1
2
ș 1
ș 2
c
0°
11° 12° 13°
0.20
0.22 0.30 0.38
0.45 0.60 0.75
1.00 REF
b
L
L1
L 2
L 3
e
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 001-66679 Rev. *J
Page 28 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Package Diagrams (continued)
Figure 8. 165-ball FBGA (15 × 17 × 1.4 mm (0.5 Ball Diameter)) Package Outline, 51-85195
51-85195 *D
Document Number: 001-66679 Rev. *J
Page 29 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Acronyms
Document Conventions
Table 2. Acronyms Used in this Document
Units of Measure
Acronym
CE
Description
Table 3. Units of Measure
Chip Enable
Clock Enable
Symbol
°C
Unit of Measure
CEN
CMOS
FBGA
I/O
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
nanosecond
percent
MHz
µA
mA
mm
ms
ns
Complementary Metal Oxide Semiconductor
Fine-Pitch Ball Grid Array
Input/Output
JTAG
NoBL
OE
Joint Test Action Group
No Bus Latency
Output Enable
%
SRAM
TCK
TDI
Static Random Access Memory
Test Clock
pF
V
picofarad
volt
Test Data-In
W
watt
TDO
TMS
TQFP
WE
Test Data-Out
Test Mode Select
Thin Quad Flat Pack
Write Enable
ECC
Error Correcting Code
Document Number: 001-66679 Rev. *J
Page 30 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Document History Page
Document Title: CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/CY7C1462KVE25, 36-Mbit (1M × 36/2M × 18) Pipelined
SRAM with NoBL™ Architecture (With ECC)
Document Number: 001-66679
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*E
*F
4680535
4757974
PRIT
04/10/2015 Changed status from Preliminary to Final.
DEVM
05/07/2015 Updated Functional Overview:
Updated ZZ Mode Electrical Characteristics:
Changed maximum value of IDDZZ parameter from 89 mA to 75 mA.
*G
*H
5028596
5210861
PRIT
11/26/2015 Added Errata.
DEVM
04/07/2016 Removed Errata.
Updated to new template.
Completing Sunset Review.
*I
5337537
6062214
PRIT
CNX
07/05/2016 Updated Neutron Soft Error Immunity:
Updated values in “Typ” and “Max” columns corresponding to LSBU (Device
without ECC) parameter.
*J
02/07/2018 Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
Document Number: 001-66679 Rev. *J
Page 31 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Memory
cypress.com/support
cypress.com/memory
cypress.com/mcu
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2011-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-66679 Rev. *J
Revised February 7, 2018
Page 32 of 32
ZBT is a registered trademark of Integrated Device Technology, Inc. No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
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