CY7C1465V25-133BX [CYPRESS]
ZBT SRAM, 512KX72, 6.5ns, CMOS, PBGA209, 14 X 22 MM, 2.20 MM HEIGHT, PLASTIC, BGA-209;
| 型号： | CY7C1465V25-133BX |
| 厂家： | 
CYPRESS |
| 描述： | ZBT SRAM, 512KX72, 6.5ns, CMOS, PBGA209, 14 X 22 MM, 2.20 MM HEIGHT, PLASTIC, BGA-209 时钟 静态存储器 内存集成电路 |
| 文件： | 总26页 (文件大小：471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
1M x 36/2M x 18/512K x 72 F/T SRAM
with NoBL™ Architecture
BWSc, BWSd, BWSe, BWSf, BWSg, BWSh), and read-write
control (WE). BWSc and BWSd apply to CY7C1461V25 and
CY7C1465V25 only. BWSe, BWSf, BWSg, and BWSh apply to
CY7C1465V25 only.
Features
• Zero Bus Latency , no dead cycles between write and
read cycles
•Supports 133-MHz bus operations
•1M x 36/2M x18/512K x 72 common I/O
•Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
A
Clock Enable (CEN) pin allows operation of the
CY7C1461V25,CY7C1463V25 and CY7C1465V25 to be
suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers
will hold their previous values.
There are three Chip Enable (CE1, CE2, CE3) pins that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is low, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(read or write) will be completed. The data bus will be in high
impedance state two cycles after chip is deselected or a write
cycle is initiated.
• Single 2.5V –5% and +5% power supply VDD
• Separate VDDQ for 2.5V or 1.8V I/O
• Clock Enable (CEN) pin to suspend operation
• Burst Capability - linear or interleaved burst order
• Available in 119-ball bump BGA, 165-ball FBGA
package and 100-pin TQFP packages (CY7C1461V25
and CY7C1463V25). 209 FBGA package for
CY7C1465V25.
The CY7C1461V25,CY7C1463V25 and CY7C1465V25 have
an on-chip two-bit burst counter. In the burst mode,
CY7C1461V25,CY7C1463V25 and CY7C1465V25 provide
four cycles of data for a single address presented to the
SRAM. The order of the burst sequence is defined by the
MODE input pin. The MODE pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load
a new external address (ADV/LD = LOW) or increment the
internal burst counter (ADV/LD = HIGH)
Functional Description
The CY7C1461V25,CY7C1463V25 and CY7C1465V25
SRAMs are designed to eliminate dead cycles when transi-
tions from Read to Write or vice versa. These SRAMs are
optimized for 100 percent bus utilization and achieves Zero
Bus Latency. They integrate 1,048,576 x 36/2,097,152 x 18/
524,288 x 72 SRAM cells, respectively, with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. The Synchronous Burst SRAM family
employs high-speed, low-power CMOS designs using
advanced single layer polysilicon, three-layer metal
technology. Each memory cell consists of six transistors.
Output Enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the
outputs at any given time. ZZ may be tied to LOW if it is not
used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE1, CE2, and CE3), cycle start input (ADV/LD),
Clock Enable (CEN), Byte Write Selects (BWSa, BWSb,
Logic Block Diagram
D
CLK
Data-In REG.
CE
Q
ADV/LD
A
x
CEN
CE
CONTROL
and WRITE
LOGIC
1MX36/
1
2M x18/
CE
2
512KX72
MEMORY
ARRAY
DQ
x
CE
DQ
3
A
BWS
X
DP
X
X
X
DP
WE
x
BWS
X = a, b
, c, d
x
X = a, b, X= a, b,
X = 19:0
X = 20:0
1Mx36
c, d
c, d
Mode
X = a, b
X = a, b X = a, b
2Mx18
X = a, b
X = a, b,
c,d,e,f,g,h
X = a, b,
c,d,e,f,g,h
X = 18:0
512Kx72
OE
c,d,e,f,g,h
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05192 Rev. *B
Revised November 8, 2002
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Selection Guide
CY7C1461V25
CY7C1463V25
CY7C1465V25
-150
CY7C1461V25
CY7C1463V25
CY7C1465V25
-133
CY7C1461V25
CY7C1463V25
CY7C1465V25
-117
Unit
ns
Maximum Access Time
5.5
6.5
7.5
Maximum Operating Current
Com’l
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
Maximum CMOS Standby Current
Shaded areas contain advance information.
Pin Configurations
100-pin TQFP Packages
DPc
DQc
DQc
1
2
3
4
5
6
7
8
DPb
NC
NC
NC
1
2
3
4
5
6
7
8
A
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb
DQb
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
NC
VSS
DQc
DQc
VSS
NC
NC
DQb
DQb
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
DPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
DQc
DQc
VSS
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQb
DQb
NC
VDD
NC
NC
VDD
ZZ
CY7C1461V25
(1M x 36)
CY7C1463V25
(2M x 18)
VDD
ZZ
DQa
DQa
VSS
DQb
DQa
DQa
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
DQb
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
DQa
DQa
NC
DQa
DQa
DQa
DQa
VSS
DQb
DQb
DPb
NC
VSS
VDDQ
NC
VSS
VDDQ
NC
NC
NC
VDDQ
VDDQ
DQd
DQd
DPd
DQa
DQa
DPa
NC
NC
NC
Document #: 38-05192 Rev. *B
Page 2 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Pin Configurations (continued)
119-ball Bump BGA
CY7C1461V25 (1M x 36) – 7 x 17 BGA
1
2
3
4
5
6
7
V
A
A
A
A
A
V
DDQ
A
DDQ
NC
NC
DQ
CE
A
A
A
ADV/LD
A
A
CE
A
NC
NC
DQ
B
C
D
2
c
3
b
V
DD
DP
V
NC
V
DP
c
SS
SS
SS
SS
SS
SS
b
DQ
DQ
DQ
DQ
DQ
V
V
V
CE
V
V
DQ
DQ
DQ
DQ
V
DQ
b
E
F
c
c
c
c
c
1
b
b
b
b
V
OE
A
V
DDQ
DDQ
DQ
BWS
BWS
DQ
G
H
J
c
c
c
b
a
b
DQ
V
WE
DQ
V
SS
b
SS
V
NC
V
NC
V
DDQ
DDQ
DD
DD
DD
DQ
DQd
V
CLK
NC
V
DQ
DQ
K
L
d
SS
SS
a
a
a
a
DQ
DQ
BWS
BWS
DQ
DQ
DQ
DP
DQ
d
d
d
V
DQ
V
CEN
A1
V
V
DDQ
M
N
P
DDQ
d
SS
SS
a
a
DQ
DQ
DP
V
V
DQ
d
d
SS
SS
a
a
DQ
V
A0
V
DQ
d
d
SS
SS
a
NC
NC
A
MODE
A
V
NC
A
A
A
NC
ZZ
R
T
DD
72M
TMS
A
V
TDI
TCK
TDO
NC
V
DDQ
U
DDQ
CY7C1463V25 (2M x 18) – 7 x 17 BGA
1
2
3
4
5
6
7
V
A
A
A
A
A
V
A
B
C
D
E
F
DDQ
DDQ
NC
CE
A
A
A
ADV/LD
A
A
CE
NC
NC
NC
DQ
2
3
NC
V
A
DD
DQ
NC
DQ
V
NC
V
DP
b
SS
SS
SS
SS
SS
SS
a
NC
V
V
CE
V
V
NC
b
1
a
V
NC
DQ
OE
DQ
V
DDQ
DDQ
a
NC
BWS
A
V
V
NC
DQ
a
G
H
J
b
b
SS
SS
DQ
NC
V
WE
DQ
NC
b
SS
a
V
V
NC
V
NC
V
V
DDQ
DDQ
DD
DD
DD
NC
DQ
V
CLK
NC
V
NC
DQ
K
L
b
SS
SS
a
DQ
NC
DQ
V
BWS
DQ
NC
b
SS
a
a
V
V
CEN
A1
V
NC
V
DDQ
M
N
P
R
T
DDQ
b
SS
SS
DQ
NC
DP
V
V
DQ
NC
DQ
b
SS
SS
a
NC
V
A0
V
NC
A
b
SS
SS
a
NC
A
A
MODE
A
V
NC
A
NC
ZZ
DD
72M
A
A
V
TMS
TDI
TCK
TDO
NC
V
DDQ
U
DDQ
Document #: 38-05192 Rev. *B
Page 3 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Pin Configurations (continued)
165-ball Bump FBGA
CY7C1461V25 (1M x 36) – 15 x 17 FBGA
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWSc
BWSb
CE
CEN
A
ADV/LD
A
A
NC
1
2
3
NC
DPc
DQc
A
CE
BWSd
BWSa
CLK
WE
B
C
D
OE
A
A
NC
DPb
DQb
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DDQ
DQc
DQc
DQc
DQc
V
V
V
V
V
DQb
DD
SS
SS
SS
DD
DQc
DQc
DQc
NC
V
V
V
V
E
F
V
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
DDQ
DDQ
V
V
V
V
V
DD
SS
SS
SS
DD
V
V
V
V
G
H
J
V
DD
SS
SS
SS
DD
V
NC
V
V
V
V
V
NC
DD
DD
SS
SS
SS
DD
DQd
DQd
DQd
DQd
DPd
NC
DQd
DQd
DQd
DQd
NC
V
V
V
V
V
V
V
DQa
DQa
DQa
DQa
NC
DQa
DQa
DQa
DQa
DPa
NC
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
K
L
V
V
V
V
V
DD
SS
SS
SS
DD
V
V
V
V
V
DD
SS
SS
SS
DD
V
V
V
V
M
N
P
V
DDQ
DD
SS
SS
SS
DD
DDQ
V
NC
TDI
NC
A1
A0
NC
V
DDQ
SS
SS
DDQ
72M
A
A
A
TDO
TCK
A
A
A
A
MODE
A
A
TMS
R
A
A
A
CY7C1463V25 (2M x 18) – 15 x 17 FBGA
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWSb
NC
CE
CEN
A
ADV/LD
A
A
A
1
2
3
NC
NC
NC
A
CE
NC
BWSa
CLK
WE
B
C
D
E
F
OE
A
A
NC
DPa
DQa
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
NC
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DDQ
DQb
V
V
V
V
V
DD
SS
SS
SS
DD
NC
NC
DQb
DQb
DQb
V
V
V
V
V
NC
NC
DQa
DQa
DQa
ZZ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
DDQ
DDQ
V
V
V
V
V
DD
SS
SS
SS
DD
NC
V
V
V
V
G
H
J
V
NC
DD
SS
SS
SS
DD
NC
V
NC
V
V
V
V
V
NC
NC
DD
DD
SS
SS
SS
DD
DQb
DQb
DQb
DQb
DPb
NC
NC
NC
NC
NC
NC
72M
V
V
V
V
V
V
V
DQa
DQa
DQa
DQa
NC
NC
DDQ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
K
L
V
V
V
V
V
NC
DD
SS
SS
SS
DD
V
V
V
V
V
NC
DD
SS
SS
SS
DD
V
V
V
V
M
N
P
V
NC
DD
SS
SS
SS
DD
V
NC
TDI
NC
A1
A0
NC
V
NC
DDQ
SS
SS
DDQ
A
A
A
TDO
TCK
A
A
A
A
NC
MODE
A
A
TMS
R
A
A
A
Document #: 38-05192 Rev. *B
Page 4 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Pin Configurations (continued)
209-ball Bump BGA
CY7C1465V25 (512K x72)
1
DQg
DQg
DQg
2
3
4
5
6
7
8
9
10
DQb
11
A
B
C
D
E
F
DQg
DQg
CE
CE
ADV/LD
WE
DQb
DQb
3
2
A
A
A
A
A
BWS
NC
NC
DQb
DQb
BWS
BWS
f
BWS
b
c
g
DQg
DQg
DPc
DQc
DQc
NC
NC
BWS
NC
BWS
CE
BWS
a
BWS
e
DQb
DQb
DPb
DQf
DQf
d
1
h
DQg
V
NC
OE
V
NC
V
SS
DQb
SS
DPg
DQc
V
V
V
V
V
V
DD
DDQ
DDQ
DDQ
SS
DDQ
DD
DD
DPf
DQf
V
V
V
V
V
NC
NC
NC
NC
CEN
NC
NC
V
V
SS
SS
DD
SS
SS
DD
SS
G
H
J
DQc
DQc
V
V
V
DDQ
V
V
V
DDQ
DQf
DQf
DDQ
DDQ
V
V
V
V
V
V
SS
V
DQc
DQc
NC
SS
SS
SS
SSQ
DDQ
SS
DQf
DQf
NC
DQc
NC
V
V
V
V
V
V
DDQ
DD
DD
DDQ
DDQ
DQf
NC
K
L
CLK
NC
V
SS
SS
NC
NC
DQh
DQh
DQh
V
V
V
V
V
DDQ
DD
SS
DD
SS
DDQ
DDQ
DQa
DQa
DQa
DDQ
M
N
P
R
T
V
V
V
V
DQh
DQh
DQh
V
V
SS
SS
SS
SS
DQa
DQa
DQa
V
V
V
V
V
DDQ
DQh
DQh
DPd
DQd
DQd
V
V
V
V
V
V
NC
ZZ
DD
DD
SS
DDQ
DDQ
SS
DDQ
DQa
DQa
DPa
DQe
DQe
V
V
V
V
V
V
SS
SS
SS
SS
V
DPh
DQd
DQd
DQd
DQd
V
DDQ
V
DDQ
DD
DD
DDQ
DDQ
SS
DD
DPe
DQe
DQe
DQe
DQe
NC
V
NC
NC
NC
A
MODE
A
SS
U
V
W
72M
A
A
NC
NC
A
A
A1
A
DQd
DQd
A
A
A
A
DQe
DQe
TDI
TDO
TCK
A0
A
TMS
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
Input-
Synchronous
Address inputs used to select one of the 1048576/2097152/524288 address locations.
Sampled at the rising edge of the CLK.
BWSa
BWSb
BWSc
BWSd
BWSe
BWSf
BWSg
BWSh
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb controls DQb and DPb,
BWSc controls DQc and DPc, BWSd controls DQd and DPd.BWSe controls DQe and DPe, BWSf
controls DQf and DPf, BWSg controls DQg and DPg, BWSh controls DQh and DPh.
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Document #: 38-05192 Rev. *B
Page 5 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1
CE2
CE3
OE
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
Input-
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the first clock when emerging from a
deselected state and when the device has been deselected.
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQa
DQb
DQc
DQd
DQe
DQf
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A[x:0] during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are
automatically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state of
OE.DQ a,b,c,d,e,f,g,h are eight bits wide.
DQg
DQh
DPa
DPb
DPc
DPd
DPe
DPf
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[x:0]. DP
a,b,c,d,e,f,g and h are one bit wide.
DPg
DPh
ZZ
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical“sleep” condition
Asynchronous with data integrity preserved.This pin can also be left as a NC.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
VDD
Power Supply
Power supply inputs to the core of the device.
VDDQ
VSS
I/O Power Supply Power supply for the I/O circuitry.
Ground
Ground for the device. Should be connected to ground of the system.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA Only).
Synchronous
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. (BGA Only). This pin
Synchronous can be left as a NC if JTAG is not used.
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous (BGA Only). This pin can be left as a NC if JTAG is not used.
JTAG serial clock Serial clock to the JTAG circuit. (BGA Only). This pin can be left as a NC if JTAG is not used.
This pin can be left as a NC if JTAG is not used.
TDI
TMS
TCK
72M
NC
–
–
No connects. Reserved for address expansion.
No connects.
Document #: 38-05192 Rev. *B
Page 6 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and will wraparound when incre-
mented sufficiently. A HIGH input on ADV/LD will increment
the internal burst counter regardless of the state of chip
enables inputs or WE. WE is latched at the beginning of a burst
cycle. Therefore, the type of access (Read or Write) is
maintained throughout the burst sequence.
Introduction
Functional Overview
The CY7C1461V25/CY7C1463V25/CY7C1465V25 is
a
Synchronous Flow-Through Burst NoBL SRAM designed
specifically to eliminate wait states during Write-Read transi-
tions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the Clock Enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. Maximum access delay from the clock rise (tCDV) is
6.5 ns (133-MHz device).
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) Chip
Enable(s) asserted active, and (3) the write signal WE is
asserted LOW. The address presented is loaded into the
Address Register. The write signals are latched into the
Control Logic block. The data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DP.
Accesses can be initiated by asserting Chip Enable(s) (CE1,
CE2, CE3 on the TQFP, CE1 on the BGA) active at the rising
edge of the clock. If Clock Enable (CEN) is active LOW and
ADV/LD is asserted LOW, the address presented to the device
will be latched. The access can either be a Read or Write
operation, depending on the status of the Write Enable (WE).
Byte Write Selects can be used to conduct byte write opera-
tions.
On the next clock rise the data presented to DQ and DP (or a
subset for byte write operations, see Write Cycle Description
table for details) inputs is latched into the device and the write
is complete. Additional accesses (Read/Write/Deselect) can
be initiated on this cycle.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
The data written during the Write operation is controlled by
Byte Write Select signals. The CY7C1461V25/CY7C1463V25
/CY7C1465V25 provide byte write capability that is described
in the Write Cycle Description table. Asserting the Write
Enable input (WE) with the selected Byte Write Select input
will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera-
tions.
Synchronous Chip Enable (CE1, CE2, and CE3 on the TQFP,
CE1 on the BGA) and an asynchronous Output Enable (OE)
simplify depth expansion. All operations (Reads, Writes, and
Deselects) are pipelined. ADV/LD should be driven LOW once
the device has been deselected in order to load a new address
for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within
6.5 ns (133-MHz device) provided OE is active LOW. After the
first clock of the read access the output buffers are controlled
by OE and the internal control logic. OE must be driven LOW
in order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Because the CY7C1461V25/CY7C1463V25/CY7C1465V25
are common I/O devices, data should not be driven into the
device while the outputs are active. The Output Enable (OE)
can be deasserted HIGH before presenting data to the DQand
DP inputs. Doing so will three-state the output drivers. As a
safety precaution, DQ and DP are automatically three-stated
during the data portion of a write cycle, regardless of the state
of OE.
Burst Write Accesses
The CY7C1461V25/CY7C1463V25/CY7C1465V25 has an
on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four Write operations
without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
driven HIGH on the subsequent clock rise, the chip enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
Burst Read Accesses
The CY7C1461V25/CY7C1463V25/CY7C1465V25 has an
on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
counter is incremented. The correct BWSa,b,c,d,e,f,g,h
/
BWSa,b,c,d/BWSa,b inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Document #: 38-05192 Rev. *B
Page 7 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Operation Address Used CE CEN ADV/LD WE BWSx CLK
Comments
Deselected External
Suspend
1
X
0
0
X
0
1
0
0
0
0
X
0
0
1
X
X
1
X
X
X
L-H I/Os three-state following next recognized clock.
L-H Clock ignored, all operations suspended.
L-H Address latched.
–
Begin Read External
Begin Write External
0
Valid L-H Address latched, data presented two valid clocks later.
Burst Read Internal
Operation
X
X
L-H Burst Read operation. Previous access was a Read
operation. Addresses incremented internally in
conjunction with the state of MODE.
Burst Write Internal
Operation
X
0
1
X
Valid L-H Burst Write operation. Previous access was a Write
operation. Addresses incremented internally in
conjunction with the state of MODE. Bytes written are
determined by BWSa,b,c,d,e,f,g,h/ BWSa,b,c,d/BWSa,b
.
Sleep Mode
Interleaved Burst Sequence
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
First
Second
Third
Fourth
Address
Address
Address
Address
A[1:0]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD – 0.2V
Min. Max. Unit
15 mA
IDDZZ
tZZS
ZZ > VDD – 0.2V
2tCYC ns
2tCYC ns
tZZREC
ZZ < 0.2V
Write Cycle Descriptions[1, 2]
Function (CY7C1461V25)
Read
WE
1
BWSd BWSc BWSb BWSa
Function (CY7C1461V25)
X
1
1
1
1
X
1
1
1
1
X
1
1
0
0
X
1
0
1
0
Read
Write – No Bytes Written
Write Byte 0 − (DQa and DPa)
Write Byte 1 − (DQb and DPb)
0
Write – No Bytes Written
Write Byte 0 − (DQa and DPa)
Write Byte 1 − (DQb and DPb)
Write Bytes 1, 0
0
0
Write Bytes 1, 0
0
Notes:
1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWS = 0 signifies at least one Byte Write Select is active, BWS
x
x
= Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS . See Write Cycle Description table for details.
x
Document #: 38-05192 Rev. *B
Page 8 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Write Cycle Descriptions[1, 2]
Function (CY7C1461V25)
Write Byte 2 − (DQc and DPc)
Write Bytes 2, 0
WE
0
BWSd BWSc BWSb BWSa
Function (CY7C1461V25)
Write Byte 2 − (DQc and DPc)
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
Write Bytes 2, 0
Write Bytes 2, 1
0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 − (DQd and DPd)
Write Bytes 3, 0
0
Write Bytes 2, 1, 0
Write Byte 3 − (DQd and DPd)
Write Bytes 3, 0
0
0
Write Bytes 3, 1
0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
0
Write Bytes 3, 1, 0
Write Bytes 3, 2
0
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
0
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
0
0
Function (CY7C1463V25)
Read
WE
1
BWSb
BWSa
Function (CY7C1463V25)
x
1
1
0
0
x
1
0
1
0
Read
Write – No Bytes Written
Write Byte 0 – (DQa and DPa)
Write Byte 1 – (DQb and DPb)
Write Both Bytes
0
Write – No Bytes Written
Write Byte 0 – (DQa and DPa)
Write Byte 1 – (DQb and DPb)
Write Both Bytes
0
0
0
Test Mode Select
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The CY7C1463V25/CY7C1461V25 incorporates a serial
boundary scan Test Access Port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1-1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
Test Access Port (TAP) - Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Notes:
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN = 1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
Document #: 38-05192 Rev. *B
Page 9 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data, or control signals into
the SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
EXTEST
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
Bypass Register
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 70-bit-long
register, and the x18 configuration has a 51-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.
Identification (ID) Register
When the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
Document #: 38-05192 Rev. *B
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CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Bypass
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05192 Rev. *B
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CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
TAP Controller State Diagram[7]
TEST-LOGIC
1
RESET
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
7. Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05192 Rev. *B
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CY7C1461V25
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CY7C1465V25
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
1
1
0
TDO
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
0
.
.
.
.
.
2
0
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[8, 9]
Parameter
VOH1
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Test Conditions
IOH = −4.0 mA
Min.
2.0
Max.
Unit
V
V
VOH2
VOL1
VOL2
VIH
IOH = −100 µA
IOL = 8.0 mA
IOL = 100 µA
2.2
0.4
0.2
V
V
1.7
–0.3
–5
VDD + 0.3
0.7
V
VIL
V
IX
GND ≤ VI ≤ VDDQ
5
µA
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
tTCYC
Description
Min.
Max
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
ns
MHz
ns
tTF
10
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
10
ns
Notes:
8. All voltage referenced to ground.
9. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t <
200 ms.
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05192 Rev. *B
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CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
tTDIH
Description
Min.
10
Max
Unit
ns
TDI Hold after Clock Rise
tCH
Capture Hold after clock rise
10
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
20
ns
ns
0
TAP Timing and Test Conditions
1.25V
50Ω
ALL INPUT PULSES
TDO
Vih
Z = 50Ω
0
C = 20 pF
L
0V
GND
tTL
tTH
(a)
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Department Number (27:25)
Voltage (28&24)
x 18
000
101
01
x36
000
101
01
Description
Reserved for version number.
Department number
Architecture (23:21)
001
001
001
001
Architecture type
Memory Type (20:18)
Defines type of memory
Document #: 38-05192 Rev. *B
Page 14 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Identification Register Definitions (continued)
Instruction Field
Revision Number (31:29)
Device Width (17:15)
x 18
000
010
111
x36
000
100
111
Description
Reserved for version number.
Defines width of the SRAM. x36 or x18
Defines the density of the SRAM
Device Density (14:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
00000110100 00000110100 Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
1
1
Scan Register Sizes
Register Name
Bit Size (x18)
Bit Size (x36)
Instruction
Bypass
3
1
3
1
ID
32
51
32
70
Boundary Scan
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
010
011
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
SAMPLE Z
RESERVED
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100
CapturestheInput/Outputringcontents. Placestheboundaryscanregister betweenTDIandTDO.
Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1 compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Document #: 38-05192 Rev. *B
Page 15 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Boundary Scan Order (1M × 36)
Boundary Scan Order (2M × 18)
Document #: 38-05192 Rev. *B
Page 16 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 1500V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Range Temperature[11]
VDD
VDDQ
Supply Voltage on VDD Relative to GND ...... –0.5V to +3.6V
DC Voltage Applied to Outputs
Com’l
0°C to +70°C
2.5 +5%/
–5%
1.7V(Min.)
VDD(Max.)
in High-Z State[12] ..............................–0.5V to VDDQ + 0.5V
DC Input Voltage[12] ............................–0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
2.375
2.375
1.7
Max.
2.625
VDD
Unit
V
V
VDDQ
2.5V range
1.8V range
VDD
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[13]
VDD = Min., IOH = –1.0 mA
VDD = Min., IOH = –100 µA
VDD = Min., IOL = 1.0 mA
VDD = Min., IOL = 100µA
VDDQ = 2.5V
VDDQ = 1.8V
VDDQ = 2.5V
VDDQ = 1.8V
VDDQ = 2.5V
VDDQ = 1.8V
VDDQ = 2.5V
VDDQ = 1.8V
2.0
V
1.4
V
0.4
0.2
V
V
1.7
V
1.26
–0.3
–0.3
V
0.7
0.36
5
V
V
Input Load Current
GND ≤ VI ≤ VDDQ
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
Input Current of MODE
Output Leakage Current
VDD Operating Supply
30
IOZ
IDD
GND ≤ VI ≤ VDDQ, Output Disabled
5
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
150 MHz
TBD
TBD
TBD
TBD
TBD
TBD
TBD
133 MHz
117 MHz
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, 150 MHz
VIN > VIH or VIN < VIL
f = fMAX = 1/tCYC
133 MHz
117 MHz
ISB2
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
Current—CMOS Inputs
V
IN ≤ 0.3V or VIN > VDDQ
−
0.3V, f= 0
ISB3
Automatic CE
Power-down
Current—CMOS Inputs
Max. VDD, Device Deselected, 150 MHz
TBD
TBD
TBD
TBD
mA
mA
mA
mA
or VIN < 0.3V or VIN > VDDQ
0.3V; f = fMAX = 1/tCYC
–
133 MHz
117 MHz
ISB4
Automatic CE
Power-down
Max. VDD, Device Deselected, All speed grades
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Shaded areas contain advance information.
Notes:
12.
TA is the case temperature.
13. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
Document #: 38-05192 Rev. *B
Page 17 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Capacitance[15]
Parameter
Description
Input Capacitance
Test Conditions
Max.
TBD
TBD
TBD
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
VDD = VDDQ = 2.5V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
AC Test Loads and Waveforms
R = 317Ω
V
[14]
DDQ
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
V
DD
90%
10%
Z =50Ω
0
R =50Ω
10%
L
5 pF
GND
R = 351Ω
V = 1.25V
L
Rise Time:
1ns
Fall Time:
1ns
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Thermal Resistance[15]
Parameter
Description
Test Conditions
BGA Typ.
TQFP Typ.
Unit
QJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch,
four-layer printed circuit board
TBD
TBD
°C/W
QJC
Thermal Resistance
(Junction to Case)
TBD
TBD
°C/W
Switching Characteristics (over the operating range)
150
133
117
Parameter
Clock
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
6.7
7.5
8.5
ns
MHz
ns
FMAX
Maximum Operating Frequency
Clock HIGH
150
133
117
tCH
2.5
2.5
2.5
2.5
3.0
3.0
tCL
Clock LOW
ns
Output Times
tCDV
Data Output Valid After CLK Rise
OE LOW to Output Valid[15, 17, 19]
Data Output Hold After CLK Rise
Clock to High-Z[15, 16, 17, 18, 19]
Clock to Low-Z[15, 16, 17, 18, 19]
OE HIGH to Output High-Z[15, 16, 17, 18, 19]
OE LOW to Output Low-Z[15, 16, 17, 18, 19]
5.5
3.0
6.5
3.0
7.5
3.5
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
2.5
2.5
0
2.5
2.5
0
2.5
2.5
0
tCHZ
5.0
4.0
5.0
4.0
5.0
4.0
tCLZ
tEOHZ
tEOLZ
Set-Up Times
tAS
Address Set-Up Before CLK Rise
1.5
1.5
1.5
Notes:
14. Input waveform should have a slew rate of > 1 V/ns.
15. Tested initially and after any design or process change that may affect these parameters.
16. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC test loads.
17. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
18. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
19. This parameter is sampled and not 100% tested.
Document #: 38-05192 Rev. *B
Page 18 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Switching Characteristics (over the operating range) (continued)
150
133
117
Parameter
tDS
Description
Data Input Set-Up Before CLK Rise
CEN Set-Up Before CLK Rise
WE, BWSx Set-Up Before CLK Rise
ADV/LD Set-Up Before CLK Rise
Chip Select Set-Up
Min.
1.5
1.5
1.5
1.5
1.5
Max.
Min.
1.5
1.5
1.5
1.5
1.5
Max.
Min.
1.5
1.5
1.5
1.5
1.5
Max.
Unit
ns
tCENS
tWES
tALS
ns
ns
ns
tCES
ns
Hold Times
tAH
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
tALH
WE, BWx Hold After CLK Rise
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
tCEH
Shaded areas contain advance information.
Switching Waveforms
Read/Write/Deselect Sequence
CLK
tCENH
tCENH
tCENS
tCENS
tCL
tCH
tCYC
CEN
tAS
ADDRESS
WA2
WA5
RA1
RA3
RA4
RA6
RA7
tAH
WE
CE
tWEH
tCEH
tWES
tCES
tCHZ
tDOH
tCLZ
tCHZ
Data
In/Out
Q6
Q4
Out
D5
In
D2
In
Q7
Out
Q3
Out
Q1
Out
Out
Device
originally
deselected
tDOH
tCDV
WE is the combination of WE and BWSx(x = a, b, c, d) to define a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip selects need to be active in order to select
the device. Any chip select can deselect the device. RAx stands for Read Address X, WA stands for
Write Address X, Dx stands for Data-in X, Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
Document #: 38-05192 Rev. *B
Page 19 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Switching Waveforms (continued)
Burst Sequences
CLK
tALH
tALS
ADV/LD
tCL
tCH
tCYC
tAH
tAS
RA1
WA2
ADDRESS
WE
RA3
tWEH
tWES
tWS
tWH
BWSx
tCES
tCEH
CE
tCLZ
tCHZ
tDH
tDOH
Q1
tCLZ
Q3
Out
Q1+2
Out
Q1+3
Out
D2
In
D2+2
In
D2+3
In
Data
In/Out
Q1+1
Out
D2+1
In
Q3+1
Out
Out
tCDV
t
tDS
DeviceCDV
originally deselected
The combination of WE & BWSx(x=a, b, c, d) define a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWSx input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
= UNDEFINED
= DON’T CARE
Document #: 38-05192 Rev. *B
Page 20 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Switching Waveforms (continued)
OE Timing
OE
tEOV
tEOHZ
Three-state
I/O’s
tEOLZ
Ordering Information
Speed
Package
Operating
Range
(MHz)
Ordering Code
CY7C1461V25-150AC
Name
Package Type
150
A101
100-pin 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1463V25-150AC
CY7C1461V25-150BGC
CY7C1463V25-150BGC
BG119
119-ball PBGA (14 x 22 x 2.4 mm)
CY7C1465V25-150BX
BG209
209-ball PBGA (14 x 22 x 2.2 mm)
165-ball FBGA (15 x 17)
CY7C1461V25-150BZC
CY7C1463V25-150BZC
BB165C
133
117
CY7C1461V25-133AC
CY7C1463V25-133AC
A101
100-pin 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball PBGA (14 x 22 x 2.4 mm)
CY7C1461V25-133BGC
CY7C1463V25-133BGC
BG119
CY7C1465V25-133BX
BG209
209-ball PBGA (14 x 22 x 2.2 mm)
165-ball FBGA (15 x 17)
CY7C1461V25-133BZC
CY7C1463V25-133BZC
BB165C
CY7C1461V25-117AC
CY7C1463V25-117AC
A101
100-pin 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball PBGA (14 x 22 x 2.4 mm)
CY7C1461V25-117BGC
CY7C1463V25-117BGC
BG119
CY7C1465V25-117BX
BG209
209-ball PBGA (14 x 22 x 2.2 mm)
165-ball FBGA (15 x 17)
CY7C1461V25-117BZC
CY7C1463V25-117BZC
BB165C
Shaded areas contain advance information.
Document #: 38-05192 Rev. *B
Page 21 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Package Diagram
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05192 Rev. *B
Page 22 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Package Diagram (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05192 Rev. *B
Page 23 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Package Diagram (continued)
209-Lead PBGA (14 x 22 x 2.20 mm) BG209
51-85143-*B
Document #: 38-05192 Rev. *B
Page 24 of 26
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Package Diagram (continued)
165-ball FBGA (15 x 17 x 1.20 mm) BB165C
51-85165-**
Zero Bus Latency, No Bus Latency, and NoBL are trademarks of Cypress Semiconductor Corporation. All products and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05192 Rev. *B
Page 25 of 26
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1461V25
CY7C1463V25
CY7C1465V25
PRELIMINARY
Document History Page
Document Title: CY7C1461V25/CY7C1463V25/CY7C1465V25 1M x 36/2M x 18/512K x 72 F/T SRAM
with NoBL™ Architecture
Document Number: 38-05192
Issue
Date
Orig. of
Change
REV.
**
ECN No.
113769
116924
Description of Change
04/19/02
08/07/02
PKS
FLX
New Data Sheet
*A
Increase Tdoh to 2.5 ns
Shaded 150-MHz device information
*B
121527
11/19/02
DSG
Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85143
(BG209) to rev. *B
Document #: 38-05192 Rev. *B
Page 26 of 26
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