CY7C1471BV33_11 [CYPRESS]
72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture; 72兆位（2M X 36/4的M× 18/1的M× 72 ）流通型SRAM与NOBL架构
| 型号： | CY7C1471BV33_11 |
| 厂家： | 
CYPRESS |
| 描述： | 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture |
| 文件： | 总35页 (文件大小：927K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Flow-Through SRAM with
NoBL™ Architecture
Features
Functional Description
■ Nobuslatency™(NoBL™)architectureeliminatesdeadcycles
between write and read cycles
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
are 3.3 V, 2M × 36/4M × 18/1M × 72 synchronous flow through
burst SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471BV33, CY7C1473BV33, and
CY7C1475BV33 are equipped with the advanced No Bus
Latency (NoBL) logic. NoBL™ is required to enable consecutive
read or write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput of
data through the SRAM, especially in systems that require
frequent write-read transitions.
■ Supports up to 133 MHz bus operations with zero wait states
■ Data is transferred on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte write capability
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
■ 3.3 V/2.5 V I/O supply (VDDQ
)
■ Fast clock-to-output times
❐ 6.5 ns (for 133 MHz device)
Write operations are controlled by two or four Byte Write Select
(BWX) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
■ Clock enable (CEN) pin to enable clock and suspend operation
■ Synchronous self-timed writes
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
■ Asynchronous output enable (OE)
■ CY7C1471BV33, CY7C1473BV33 available in
JEDEC-standard Pb-free 100-pin thin quad flat pack (TQFP),
Pb-free and non-Pb-free 165-ball fine-pitch ball grid array
(FBGA) package. CY7C1475BV33 available in Pb-free and
non-Pb-free 209-ball FBGA package
■ Three chip enables (CE1, CE2, CE3) for simple depth
expansion
■ Automatic power-down feature available using ZZ mode or CE
deselect
■ IEEE 1149.1 JTAG boundary scan compatible
■ Burst capability—linear or interleaved burst order
■ Low standby power
Selection Guide
Description
Maximum access time
133 MHz
6.5
117 MHz
8.5
Unit
ns
Maximum operating current
305
275
mA
mA
Maximum CMOS standby current
120
120
Cypress Semiconductor Corporation
Document Number: 001-15029 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 30, 2011
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Logic Block Diagram – CY7C1471BV33 (2 M × 36)
ADDRESS
REGISTER
A0, A1,
A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
MODE
BURST
LOGIC
CE
ADV/LD
CLK
CEN
C
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
E
ADV/LD
A
B
U
F
F
E
R
S
MEMORY
ARRAY
BW
BW
BW
BW
A
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
B
A
B
A
M
P
C
C
D
D
S
WE
E
N
G
INPUT
REGISTER
E
OE
CE1
CE2
CE3
READ LOGIC
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1473BV33 (4 M × 18)
ADDRESS
REGISTER
A0, A1,
A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
MODE
BURST
LOGIC
CE
ADV/LD
CLK
EN
C
C
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
A
S
E
N
S
E
ADV/LD
B
U
F
MEMORY
ARRAY
BWA
BWB
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
A
B
A
M
P
F
E
R
S
S
WE
E
N
G
INPUT
REGISTER
E
OE
CE1
CE2
CE3
READ LOGIC
SLEEP
CONTROL
ZZ
Document Number: 001-15029 Rev. *E
Page 2 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Logic Block Diagram – CY7C1475BV33 (1 M × 72)
ADDRESS
REGISTER
A0, A1,
A
0
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
CLK
CEN
C
WRITE ADDRESS
REGISTER 2
WRITE ADDRESS
REGISTER
1
O
U
T
O
U
T
P
U
T
S
E
N
S
E
P
U
T
D
A
T
A
ADV/LD
BW
BW
BW
BW
BW
BW
BW
a
R
E
G
I
MEMORY
ARRAY
B
U
F
DQ s
WRITE
DRIVERS
b
c
S
T
E
E
R
I
A
M
P
DQ Pa
DQ Pb
DQ Pc
DQ Pd
DQ Pe
DQ Pf
DQ Pg
DQ Ph
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
F
S
T
E
R
S
d
e
E
R
S
S
f
N
G
g
E
E
BW
h
WE
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
CE1
CE2
CE3
READ LOGIC
Sleep Control
ZZ
Document Number: 001-15029 Rev. *E
Page 3 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Contents
Pin Configuration .............................................................5
Pin Definitions ..................................................................9
Functional Overview ......................................................10
Single Read Accesses ..............................................10
Burst Read Accesses ................................................10
Single Write Accesses ...............................................11
Burst Write Accesses ................................................11
Sleep Mode ...............................................................11
Interleaved Burst Address Table ..................................11
Linear Burst Address Table ...........................................11
ZZ Mode Electrical Characteristics ...............................11
Truth Table ................................................................12
Truth Table for Read/Write ........................................13
Truth Table for Read/Write ........................................13
Truth Table for Read/Write ........................................13
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................14
Disabling the JTAG Feature ......................................14
Test Access Port (TAP) .............................................14
PERFORMING A TAP RESET ..................................14
TAP REGISTERS ......................................................14
TAP Instruction Set ...................................................15
TAP Controller State Diagram .......................................16
TAP Controller Block Diagram .....................................17
3.3-V TAP AC Test Conditions ......................................18
3.3-V TAP AC Output Load Equivalent .........................18
2.5-V TAP AC Test Conditions ......................................18
2.5-V TAP AC Output Load Equivalent .........................18
TAP DC Electrical Characteristics and
Operating Conditions .....................................................18
TAP AC Switching Characteristics ...............................19
TAP Timing ......................................................................19
Identification Register Definitions ................................20
Scan Register Sizes .......................................................20
Identification Codes .......................................................20
Boundary Scan Exit Order (2 M × 36) ...........................21
Boundary Scan Exit Order (4 M × 18) ...........................21
Boundary Scan Exit Order (1 M × 72) ...........................22
Maximum Ratings ...........................................................23
Operating Range .............................................................23
Electrical Characteristics ...............................................23
Capacitance ....................................................................24
Thermal Resistance ........................................................24
Switching Characteristics ..............................................25
Switching Waveforms ....................................................26
Ordering Information ......................................................29
Ordering Code Definitions ........................................29
Package Diagrams ..........................................................30
Reference Information ...................................................33
Acronyms ..................................................................33
Document Conventions .................................................33
Document History Page ................................................34
Sales, Solutions, and Legal Information ......................35
Worldwide Sales and Design Support .......................35
Products ....................................................................35
PSoC Solutions .........................................................35
Document Number: 001-15029 Rev. *E
Page 4 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Pin Configuration
Figure 1. 100-pin TQFP Pinout – CY7C1471BV33 (2 M × 36)
DQPC
DQC
DQC
VDDQ
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
DQPB
DQB
DQB
VDDQ
VSS
2
3
4
5
DQC
6
DQB
DQB
DQB
DQB
VSS
BYTE C
BYTE B
DQC
DQC
DQC
VSS
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQC
DQC
NC
VDDQ
DQB
DQB
VSS
CY7C1471BV33
VDD
NC
NC
VDD
ZZ
VSS
DQD
DQD
VDDQ
VSS
DQA
DQA
VDDQ
VSS
DQD
DQA
DQA
DQA
DQA
VSS
DQD
BYTE D
BYTE A
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
VDDQ
DQA
DQA
DQPA
Document Number: 001-15029 Rev. *E
Page 5 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Pin Configuration (continued)
Figure 2. 100-pin TQFP Pinout – CY7C1473BV33 (4 M × 18)
NC
NC
80
A
1
79
2
NC
NC
78
3
NC
VDDQ
VSS
NC
77
4
VDDQ
76
5
VSS
75
6
NC
NC
74
7
DQPA
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
73
8
DQA
72
9
DQA
71
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
70
VDDQ
69
DQA
68
DQA
CY7C1473BV33
67
VSS
BYTE A
VDD
NC
66
NC
BYTE B
65
VDD
ZZ
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
VSS
VDDQ
NC
NC
NC
NC
NC
Document Number: 001-15029 Rev. *E
Page 6 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Pin Configuration (continued)
165-ball FBGA (15 × 17 × 1.4 mm) Pinout
CY7C1471BV33 (2 M × 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE
7
8
9
A
10
A
11
NC
NC/576M
NC/1G
DQPC
DQC
CEN
WE
VSS
VSS
ADV/LD
A
B
C
D
3
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
A
A
NC
NC
DQC
VDDQ
VDDQ
NC
DQPB
DQB
VDD
DQB
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
DQD
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
M
N
P
NC/144M
TDI
TDO
NC/288M
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
CY7C1473BV33 (4 M × 18)
1
NC/576M
NC/1G
NC
2
A
3
CE1
4
BWB
5
NC
6
CE
7
8
9
A
10
A
11
A
CEN
WE
VSS
VSS
ADV/LD
A
B
C
D
3
A
CE2
VDDQ
VDDQ
NC
VSS
VDD
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
A
A
NC
NC
DQB
VDDQ
VDDQ
NC
NC
DQPA
DQA
NC
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
M
N
P
NC/144M
TDI
TDO
NC/288M
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
Document Number: 001-15029 Rev. *E
Page 7 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Pin Configuration (continued)
209-ball FBGA (14 × 22 × 1.76 mm) Pinout
CY7C1475BV33 (1 M × 72)
1
2
3
4
5
6
7
8
9
10
11
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
A
CE2
A
ADV/LD
WE
A
A
CE3
BWSb
BWSe
NC
A
DQb
DQb
DQb
DQb
DQb
DQb
A
B
BWSc
BWSh
VSS
BWSg
NC
BWSf
BWSa
VSS
BWSd NC/576M CE1
NC
NC
C
D
NC/1G
OE
NC
DQb
DQb
DQPb
DQf
E
F
DQPg
DQc
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
NC
VDD
VSS
VDD
DQPf
DQf
VSS
VDDQ
VSS
VSS
VDDQ
VSS
G
H
J
DQc
DQc
NC
VDDQ
VSS
DQf
DQf
DQf
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
DQc
DQc
NC
NC
DQf
DQf
NC
VDDQ
DQc
NC
VDDQ
VDDQ
CLK
VDDQ
NC
NC
DQf
NC
K
L
CEN
NC
NC
NC
DQh
DQh
DQh
VDDQ
VSS
VDDQ
VSS
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
DQa
DQa
DQa
M
N
P
R
T
NC
VSS
VDDQ
VSS
VDDQ
NC
DQh
DQh
DQh
VSS
VDD
VSS
DQa
DQa
DQa
VDDQ
DQh
DQh
DQPd
DQd
DQd
NC
ZZ
DQa
DQa
DQPa
DQe
DQe
VSS
VDDQ
VDDQ
VDD
NC
A
DQPh
DQd
DQd
DQd
DQd
VDDQ
VDD
DQPe
DQe
DQe
DQe
DQe
VSS
VSS
NC
A
MODE
A
U
V
W
A
NC/288M
NC/144M
A
A
A1
A
DQd
DQd
A
A
A
A
DQe
DQe
TDI
TDO
TCK
A0
A
TMS
Document Number: 001-15029 Rev. *E
Page 8 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Address inputs used to select one of the address locations. Sampled at the rising edge of
Synchronous the CLK. A[1:0] is fed to the two-bit burst counter.
BWA, BWB,
BWC, BWD,
BWE, BWF,
BWG, BWH
Input-
Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
Synchronous on the rising edge of CLK.
WE
Input-
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
Synchronous This signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Advance/load input. Advances the on-chip address counter or loads a new address. When
Synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After deselection, drive ADV/LD LOW to
load a new address.
CLK
CE1
CE2
CE3
OE
Input-
Clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Input-
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
Synchronous with CE2 and CE3 to select or deselect the device.
Input- Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
Synchronous with CE1 and CE3 to select or deselect the device.
Input- Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
Synchronous with CE1 and CE2 to select or deselect the device.
Input- Output enable, asynchronous input, active LOW. Combined with the synchronous logic
Asynchronous block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
enabled to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected.
CEN
ZZ
Input-
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the
Synchronous SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does
not deselect the device, CEN can be used to extend the previous cycle when required.
Input-
ZZ “Sleep” input. This active HIGH input places the device in a non-time critical “sleep”
Asynchronous condition with data integrity preserved. During normal operation, this pin must be LOW or left
floating. ZZ pin has an internal pull-down.
DQs
I/O-
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous read cycle. The
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
clock rise of the
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically
tri-stated during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected, regardless of the state of OE.
DQPX
MODE
VDD
I/O-
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During
Synchronous write sequences, DQPX is controlled by BWX correspondingly.
Input Strap Pin Mode input. Selects the burst order of the device. When tied to Gnd selects linear burst
sequence. When tied to VDD or left floating selects interleaved burst sequence.
Power Supply Power supply inputs to the core of the device.
VDDQ
VSS
I/O Power Supply Power supply for the I/O circuitry.
Ground Ground for the device.
Document Number: 001-15029 Rev. *E
Page 9 of 35
[+] Feedback
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Pin Definitions (continued)
Name
I/O
Description
TDO
JTAG serial
output
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not used, this pin must be left unconnected. This pin is not available on TQFP
Synchronous packages.
TDI
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
Synchronous not used, this pin can be left floating or connected to VDD through a pull-up resistor. This pin is
not available on TQFP packages.
TMS
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
Synchronous not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP
packages.
TCK
NC
JTAG
-Clock
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be connected
to VSS. This pin is not available on TQFP packages.
–
No connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
Single Read Accesses
Functional Overview
A read access is initiated when these conditions are satisfied at
clock rise:
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
are synchronous flow through burst SRAMs designed
specifically to eliminate wait states during write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
Clock Enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133 MHz
device).
■ CEN is asserted LOW
■ CE1, CE2, and CE3 are ALL asserted active
■ WE is deasserted HIGH
■ ADV/LD is asserted LOW
The address presented to the address inputs is latched into the
Address Register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133 MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW to drive out the
requested data. On the subsequent clock, another operation
(read/write/deselect) can be initiated. When the SRAM is
deselected at clock rise by one of the chip enable signals, output
is tri-stated immediately.
Accesses may be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If (CEN)
is active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE). Byte Write Select (BWX) can be used to conduct
Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Burst Read Accesses
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four reads without reasserting
the address inputs. ADV/LD must be driven LOW to load a new
address into the SRAM, as described in the Single Read Access
section. The sequence of the burst counter is determined by the
MODE input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and wrap around
when incremented sufficiently. A HIGH input on ADV/LD
increments the internal burst counter regardless of the state of
chip enable inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Document Number: 001-15029 Rev. *E
Page 10 of 35
[+] Feedback
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
subsequent clock rise, the chip enables (CE1, CE2, and CE3)
and WE inputs are ignored and the burst counter is incremented.
Drive the correct BWX inputs in each cycle of the burst write to
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) WE is asserted LOW.
The address presented to the address bus is loaded into the
Address Register. The Write signals are latched into the Control
Logic block. The data lines are automatically tri-stated
write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
and the completion of the operation is not guaranteed. The
device must be deselected before entering the “sleep” mode.
CE1, CE2, and CE3, must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for Byte Write operations, see section Truth Table for
Read/Write on page 13 for details), input is latched into the
device and the write is complete. Additional accesses
(read/write/deselect) can be initiated on this cycle.
The data written during the write operation is controlled by BWX
signals. The CY7C1471BV33, CY7C1473BV33, and
Interleaved Burst Address Table
CY7C1475BV33 provide Byte Write capability that is described
in the section Truth Table for Read/Write on page 13. The input
WE with the selected BWX input selectively writes to only the
desired bytes. Bytes not selected during a Byte Write operation
remain unaltered. A synchronous self timed write mechanism is
provided to simplify the write operations. Byte write capability is
included to greatly simplify read/modify/write sequences, which
can be reduced to simple byte write operations.
(MODE = Floating or VDD
)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Because the CY7C1471BV33, CY7C1473BV33, and
CY7C1475BV33 are common I/O devices, do not drive data into
the device when the outputs are active. The Output Enable (OE)
can be deasserted HIGH before presenting data to the DQs and
DQPX inputs. Doing so tri-states the output drivers. As a safety
precaution, DQs and DQPX are automatically tri-stated during
the data portion of a write cycle, regardless of the state of OE.
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Burst Write Accesses
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in section Single Write
Accesses on page 11. When ADV/LD is driven HIGH on the
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
Min
–
Max
120
2tCYC
–
Unit
ZZ > VDD – 0.2 V
mA
ns
ns
ns
ns
tZZS
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
tZZREC
tZZI
ZZ recovery time
2tCYC
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
–
0
2tCYC
–
tRZZI
Document Number: 001-15029 Rev. *E
Page 11 of 35
[+] Feedback
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Truth Table
The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows.[1, 2, 3, 4, 5, 6, 7]
Address
Operation
Deselect cycle
CE1 CE2
ZZ ADV/LD
WE
BWX OE
CEN CLK
DQ
CE3
Used
None
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
H
L
X
X
X
X
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L->H
L->H
L->H
L->H
Tri-state
Tri-state
Tri-state
Tri-state
Deselect cycle
None
Deselect cycle
None
Continue deselect cycle
None
X
H
Read cycle
External
L->H Data out (Q)
(begin burst)
Read cycle
(continue burst)
Next
External
Next
X
L
X
H
X
H
X
H
X
X
L
L
L
L
L
L
L
L
H
L
X
H
X
L
X
X
X
L
L
H
H
X
X
X
X
L
L
L
L
L
L
L
L->H Data out (Q)
NOP/Dummy read
(begin burst)
L->H
L->H
Tri-state
Tri-state
Dummy read
(continue burst)
X
L
X
L
H
L
Write cycle
(begin burst)
External
Next
L->H Data in (D)
L->H Data in (D)
Write cycle
(continue burst)
X
L
X
L
H
L
X
L
L
NOP/Write abort
(begin burst)
None
H
H
L->H
L->H
Tri-state
Tri-state
Write abort
Next
X
X
H
X
(continue burst)
Ignore clock edge (stall)
Sleep mode
Current
None
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
H
X
L->H
X
–
H
Tri-state
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW = L signifies at least one Byte Write Select is active, BW = Valid signifies that the desired Byte Write Selects
X
X
are asserted, see section Truth Table for Read/Write on page 13 for details.
2. Write is defined by BW , and WE. See section Truth Table for Read/Write on page 13.
X
3. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
4. The DQs and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
X
5. CEN = H, inserts wait states.
6. Device powers up deselected with the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = tri-state when OE is
X
inactive or when the device is deselected, and DQs and DQP = data when OE is active.
X
Document Number: 001-15029 Rev. *E
Page 12 of 35
[+] Feedback
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Truth Table for Read/Write
The read/write truth table for CY7C1471BV33 follows.[8, 9, 10]
Function
WE
H
L
BWA
X
BWB
X
BWC
X
BWD
X
Read
Write – No bytes written
H
H
H
H
Write byte A – (DQA and DQPA)
Write byte B – (DQB and DQPB)
Write byte C – (DQC and DQPC)
Write byte D – (DQD and DQPD)
Write all bytes
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
Truth Table for Read/Write
The read/write truth table for CY7C1473BV33 follows.[8, 9, 10]
Function
WE
H
L
BWa
X
BWb
X
Read
Write – No bytes written
Write byte a – (DQa and DQPa)
Write byte b – (DQb and DQPb)
Write both bytes
H
H
L
L
H
L
H
L
L
L
L
Truth Table for Read/Write
The read/write truth table for CY7C1475BV33 follows.[8, 9, 10]
Function
WE
H
BWx
Read
X
Write – No bytes written
Write byte X − (DQx and DQPx)
Write all bytes
L
H
L
L
L
All BW = L
Notes
8. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW = L signifies at least one Byte Write Select is active, BW = Valid signifies that the desired Byte Write
X
X
Selects are asserted, see section Truth Table for Read/Write on page 13 for details.
9. Write is defined by BW , and WE. See section Truth Table for Read/Write on page 13.
X
10. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write is based on which byte write is active.
X
Document Number: 001-15029 Rev. *E
Page 13 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Performing a TAP Reset
IEEE 1149.1 Serial Boundary Scan (JTAG)
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
incorporate a serial boundary scan test access port (TAP). This
port operates in accordance with IEEE Standard 1149.1-1990
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels.
During power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test circuitry.
Only one register is selected at a time through the instruction
register. Data is serially loaded into the TDI ball on the rising
edge of TCK. Data is output on the TDO ball on the falling edge
of TCK.
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
contain a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
nstruction Register
Disabling the JTAG Feature
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 17. During power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
must be left unconnected. During power-up, the device comes
up in a reset state, which does not interfere with the operation of
the device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Bypass Register
Test Access Port (TAP)
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows the shifting of data through the
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
SRAM with minimal delay. The bypass register is set LOW (VSS
)
when the BYPASS instruction is executed.
Test MODE SELECT (TMS)
Boundary Scan Register
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. This ball may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
Test Data-In (TDI)
The TDI ball serially inputs information into the registers and can
be connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information about loading
the instruction register, see the TAP Controller State Diagram on
page 16. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See the TAP Controller
Block Diagram on page 17.)
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the section Identification Register
Definitions on page 20.
Test Data-Out (TDO)
The TDO output ball serially clocks data-out from the registers.
The output is active depending upon the current state of the TAP
state machine. The output changes on the falling edge of TCK.
TDO is connected to the least significant bit (LSB) of any register.
(See TAP Controller State Diagram on page 16.)
Document Number: 001-15029 Rev. *E
Page 14 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
SAMPLE/PRELOAD
TAP Instruction Set
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Identification
Codes” on page 20. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail in this section.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output may undergo a
transition. The TAP may then try to capture a signal when in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
EXTEST
EXTEST is a mandatory 1149.1 instruction which must be
executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state when
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
BYPASS
IDCODE
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and enables
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
Reserved
The IDCODE instruction is loaded into the instruction register
during power-up or whenever the TAP controller is in a test logic
reset state.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Document Number: 001-15029 Rev. *E
Page 15 of 35
[+] Feedback
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
Document Number: 001-15029 Rev. *E
Page 16 of 35
[+] Feedback
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
TAP Controller Block Diagram
0
Bypass Register
2
1
0
0
0
Selection
Circuitry
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
TDI
TDO
.
.
. 2 1
x
.
.
.
.
. 2 1
Boundary Scan Register
TCK
TAP CONTROLLER
TM S
Document Number: 001-15029 Rev. *E
Page 17 of 35
[+] Feedback
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
3.3-V TAP AC Test Conditions
2.5-V TAP AC Test Conditions
Input pulse levels................................................VSS to 3.3 V
Input rise and fall times....................................................1 ns
Input timing reference levels.......................................... 1.5 V
Output reference levels ................................................. 1.5 V
Test load termination supply voltage ............................. 1.5V
Input pulse levels............................................... VSS to 2.5 V
Input rise and fall time .....................................................1 ns
Input timing reference levels........................................ 1.25 V
Output reference levels ............................................... 1.25 V
Test load termination supply voltage ........................... 1.25V
3.3-V TAP AC Output Load Equivalent
2.5-V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ±0.165 V unless otherwise noted)[11]
Parameter
VOH1
Description
Output HIGH voltage IOH = –4.0 mA, VDDQ = 3.3 V
OH = –1.0 mA, VDDQ = 2.5 V
Test Conditions
Min
2.4
2.0
2.9
2.1
–
Max
Unit
V
–
I
–
V
VOH2
VOL1
VOL2
VIH
Output HIGH voltage IOH = –100 µA
VDDQ = 3.3 V
DDQ = 2.5 V
–
V
V
–
0.4
V
Output LOW voltage IOL = 8.0 mA
IOL = 1.0 mA
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
V
–
0.4
V
Output LOW voltage IOL = 100 µA
–
0.2
V
V
DDQ = 2.5 V
VDDQ = 3.3 V
DDQ = 2.5 V
VDDQ = 3.3 V
DDQ = 2.5 V
–
0.2
V
Input HIGH voltage
Input LOW voltage
2.0
1.7
–0.3
–0.3
–5
VDD + 0.3
VDD + 0.3
0.8
V
V
V
VIL
V
V
0.7
V
IX
Input load current
GND < VIN < VDDQ
5
µA
Notes
11. All voltages refer to V (GND).
SS
Document Number: 001-15029 Rev. *E
Page 18 of 35
[+] Feedback
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
TAP AC Switching Characteristics
Over the Operating Range[12, 13]
Parameter
Clock
Description
Min
Max
Unit
tTCYC
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
–
0
5
–
ns
ns
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMs hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
TAP Timing
Figure 3. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
TM SS
TM SH
Test M ode Select
(TM S)
t
TDIS
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Notes
12. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
13. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-15029 Rev. *E
Page 19 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Identification Register Definitions
CY7C1471BV33 CY7C1473BV33 CY7C1475BV33
Instruction Field
Description
(2 M × 36)
(4 M × 18)
(1 M × 72)
Revision number (31:29)
Device depth (28:24)[14]
000
000
000
Describes the version number
Reserved for internal use
01011
01011
01011
Architecture/memory type(23:18)
Bus width/density(17:12)
001001
001001
001001
110100
Defines memory type and architecture
Defines width and density
100100
010100
Cypress JEDEC ID code (11:1)
00000110100
00000110100
00000110100 EnablesuniqueidentificationofSRAM
vendor
ID register presence indicator (0)
1
1
1
Indicates the presence of an ID
register
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
Instruction
3
1
3
1
3
1
Bypass
ID
32
71
–
32
52
–
32
–
Boundary scan order – 165FBGA
Boundary scan order – 209BGA
110
Identification Codes
Instruction
Code
Description
EXTEST
000 Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM outputs to High-Z state. This instruction is not
1149.1-compliant.
IDCODE
001 Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRAM operations.
SAMPLE Z
010 Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do not use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100 Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Does not affect SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
RESERVED
RESERVED
BYPASS
101 Do not use: This instruction is reserved for future use.
110
111
Do not use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operations.
Note
14. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 001-15029 Rev. *E
Page 20 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Boundary Scan Exit Order (2 M × 36)
Bit #
1
165-Ball ID
C1
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
165-Ball ID
R3
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
165-Ball ID
J11
Bit #
61
62
63
64
65
66
67
68
69
70
71
165-Ball ID
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
2
D1
P2
K10
J10
3
E1
R4
4
D2
P6
H11
G11
F11
E11
D10
D11
C11
G10
F10
E10
A9
5
E2
R6
6
F1
R8
7
G1
F2
P3
8
P4
9
G2
J1
P8
10
11
12
13
14
15
16
17
18
19
20
P9
K1
P10
R9
L1
J2
R10
R11
N11
M11
L11
M10
L10
K11
M1
N1
B9
K2
A10
B10
A8
L2
M2
R1
B8
R2
A7
Boundary Scan Exit Order (4 M × 18)
Bit #
1
165-Ball ID
Bit #
14
15
16
17
18
19
20
21
22
23
24
25
26
165-Ball ID
R4
Bit #
27
28
29
30
31
32
33
34
35
36
37
38
39
165-Ball ID
L10
Bit #
40
41
42
43
44
45
46
47
48
49
50
51
52
165-Ball ID
B10
A8
D2
E2
F2
G2
J1
2
P6
K10
J10
3
R6
B8
4
R8
H11
G11
F11
A7
5
P3
B7
6
K1
L1
P4
B6
7
P8
E11
A6
8
M1
N1
R1
R2
R3
P2
P9
D11
C11
A11
B5
9
P10
R9
A4
10
11
12
13
B3
R10
R11
M10
A9
A3
B9
A2
A10
B2
Document Number: 001-15029 Rev. *E
Page 21 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Boundary Scan Exit Order (1 M × 72)
Bit #
1
209-Ball ID
A1
Bit #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
209-Ball ID
T1
Bit #
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
209-Ball ID
U10
T11
Bit #
85
209-Ball ID
B11
B10
A11
A10
A7
2
A2
T2
86
3
B1
U1
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
87
4
B2
U2
88
5
C1
C2
D1
D2
E1
V1
89
6
V2
90
A5
7
W1
W2
T6
91
A9
8
92
U8
9
93
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
E2
V3
94
D6
F1
V4
95
K6
F2
U4
96
B6
G1
G2
H1
H2
J1
W5
V6
L10
97
K3
P6
98
A8
W6
V5
J11
99
B4
J10
100
101
102
103
104
105
106
107
108
109
110
B3
U5
H11
H10
G11
G10
F11
C3
J2
U6
C4
L1
W7
V7
C8
L2
C9
M1
M2
N1
N2
P1
U7
B9
V8
F10
E10
E11
D11
D10
C11
C10
B8
V9
A4
W11
W10
V11
V10
U11
C6
B7
P2
A3
R2
R1
Document Number: 001-15029 Rev. *E
Page 22 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage........................................... >2001 V
(MIL-STD-883, Method 3015)
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Latch-up current ..................................................... >200 mA
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with power applied . –55 °C to +125 °C
Supply voltage on VDD relative to GND........–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD
Operating Range
Ambient
Temperature
Range
VDD
VDDQ
DC voltage applied to
outputs in tri-state ..............................–0.5 V to VDDQ + 0.5 V
Commercial 0 °C to +70 °C 3.3 V –5%/+10% 2.5 V – 5%
to VDD
Industrial
–40 °C to +85 °C
DC input voltage..................................–0.5 V to VDD + 0.5 V
Electrical Characteristics
Over the Operating Range[15, 16]
Parameter
VDD
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
Unit
V
3.6
VDDQ
For 3.3 V I/O
For 2.5 V I/O
VDD
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH voltage[15]
Input LOW voltage[15]
For 3.3 V I/O, IOH = –4.0 mA
For 2.5 V I/O, IOH = –1.0 mA
For 3.3 V I/O, IOL = 8.0 mA
For 2.5 V I/O, IOL = 1.0 mA
For 3.3 V I/O
–
V
2.0
–
0.4
V
–
V
–
0.4
V
2.0
VDD + 0.3 V
V
For 2.5 V I/O
1.7
V
DD + 0.3 V
V
For 3.3 V I/O
–0.3
–0.3
–5
0.8
0.7
5
V
For 2.5 V I/O
V
Input leakage current except GND ≤ VI ≤ VDDQ
ZZ and MODE
μA
Input current of MODE
Input = VSS
–30
–
–
5
μA
μA
μA
μA
μA
mA
Input = VDD
Input current of ZZ
Input = VSS
–5
–
Input = VDD
30
5
IOZ
Output leakage current
GND ≤ VI ≤ VDD, output disabled
–5
–
[17]
IDD
VDD operating supply current VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5 ns cycle, 133 MHz
305
–
10 ns cycle, 117 MHz
7.5 ns cycle, 133 MHz
–
275
200
mA
mA
ISB1
Automatic CE
power-down
current—TTL inputs
VDD = Max, device deselected,
VIN ≥ VIH or VIN ≤ VIL
–
–
f = fMAX, inputs switching
10 ns cycle, 117 MHz
All speeds
–
200
120
mA
mA
ISB2
Automatic CE
power-down
current—CMOS inputs
VDD = Max, device deselected,
VIN ≤ 0.3 V or VIN > VDD – 0.3 V,
f = 0, inputs static
–
ISB3
Automatic CE
power-down
current—CMOS inputs
V
DD = Max, device deselected, or 7.5 ns cycle, 133 MHz
–
–
–
200
200
mA
mA
VIN ≤ 0.3 V or VIN > VDDQ – 0.3 V
f = fMAX, inputs switching
10 ns cycle, 117 MHz
Notes
15. Overshoot: V (AC) < V +1.5 V (pulse width less than t
/2). Undershoot: V (AC) > –2 V (pulse width less than t
/2).
CYC
IH
DD
CYC
IL
16. T
: assumes a linear ramp from 0 V to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
17. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-15029 Rev. *E
Page 23 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Electrical Characteristics
Over the Operating Range[15, 16] (continued)
Parameter
Description
Automatic CE
Test Conditions
DD = Max, device deselected, All Speeds
Min
Max
Unit
ISB4
V
–
165
mA
power-down
current—TTL inputs
VIN ≥ VDD – 0.3 V or VIN ≤ 0.3 V,
f = 0, inputs static
Capacitance
Tested initially and after any design or process change that may affect these parameters.
100-pinTQFP 165-ball FBGA 209-ball BGA
Parameter
Description
Test Conditions
Unit
Package
Package
Package
CADDRESS Address input capacitance
TA = 25 °C, f = 1 MHz,
6
5
8
6
5
6
5
8
6
5
6
5
8
6
5
pF
pF
pF
pF
pF
V
DD = 3.3 V
CDATA
CCTRL
CCLK
CI/O
Data input capacitance
Control input capacitance
Clock input capacitance
I/O capacitance
VDDQ = 2.5 V
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
100-pin
TQFP Max
165-ball
FBGA Max
209-ball
FBGA Max
Parameter
Description
Test Conditions
Unit
θJA
Thermal resistance
(junction to ambient)
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
according to EIA/JESD51.
24.63
16.3
2.1
15.2
1.7
°C/W
θJC
Thermal resistance
(junction to case)
2.28
°C/W
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 Ω
3.3 V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50 Ω
0
10%
R = 50 Ω
L
GND
5 pF
R = 351 Ω
≤ 1 ns
≤ 1 ns
V = 1.5 V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
2.5 V I/O Test Load
(b)
R = 1667 Ω
2.5 V
OUTPUT
R = 50 Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50 Ω
0
10%
L
5 pF
R = 1538 Ω
≤ 1 ns
≤ 1 ns
V = 1.25 V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document Number: 001-15029 Rev. *E
Page 24 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Switching Characteristics
Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5 V when VDDQ = 3.3 V and is
1.25 V when VDDQ = 2.5 V. Test conditions shown in (a) of AC Test Loads and Waveforms on page 24 unless otherwise noted.
133 MHz
Max
117 MHz
Parameter
Description
Unit
Min
Min
Max
[18]
tPOWER
1
–
1
–
ms
Clock
tCYC
tCH
Clock cycle time
Clock HIGH
7.5
2.5
2.5
–
–
–
10
3.0
3.0
–
–
–
ns
ns
ns
tCL
Clock LOW
Output Times
tCDV
Data output valid after CLK rise
–
2.5
3.0
–
6.5
–
–
2.5
3.0
–
8.5
–
ns
ns
ns
ns
ns
ns
ns
tDOH
Data output hold after CLK rise
Clock to low-Z [19, 20, 21]
Clock to high-Z [19, 20, 21]
tCLZ
–
–
tCHZ
3.8
3.0
–
4.5
3.8
–
tOEV
OE LOW to output valid
–
–
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to output low-Z [19, 20, 21]
OE HIGH to output high-Z [19, 20, 21]
0
0
–
3.0
–
4.0
Address setup before CLK rise
ADV/LD setup before CLK rise
WE, BWX setup before CLK rise
CEN setup before CLK rise
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tALS
tWES
tCENS
tDS
Data input setup before CLK rise
Chip enable setup before CLK rise
tCES
Hold Times
tAH
Address hold after CLK rise
ADV/LD hold after CLK rise
WE, BWX hold after CLK rise
CEN hold after CLK rise
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tALH
tWEH
tCENH
tDH
Data input hold after CLK rise
Chip enable hold after CLK rise
tCEH
Notes
18. This part has an internal voltage regulator; t
is the time that the power must be supplied above V (minimum) initially, before a read or write operation is initiated.
DD
POWER
19. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 24. Transition is measured ±200 mV
CHZ CLZ OELZ
OEHZ
from steady-state voltage.
20. At any supplied voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z before Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document Number: 001-15029 Rev. *E
Page 25 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Switching Waveforms
Figure 5 shows read-write timing waveform.[22, 23, 24]
Figure 5. Read/Write Timing
t
1
2
3
4
5
6
7
8
9
10
CYC
t
CLK
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CEN
CE
ADV/LD
W E
BW
X
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COM M AND
W RITE
D(A1)
W RITE
D(A2)
BURST
W RITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
W RITE
D(A5)
READ
Q(A6)
W RITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes
For this waveform ZZ is tied LOW.
22.
23. When CE is LOW, CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH, CE is HIGH, CE is LOW or CE is HIGH.
1
2
3
1
2
3
24. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 001-15029 Rev. *E
Page 26 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Switching Waveforms (continued)
Figure 6 shows NOP, STALL and DESELECT Cycles waveform.[25, 26, 27]
Figure 6. NOP, STALL, and DESELECT Cycles
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A1
A2
A3
A4
A5
t
CHZ
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
DQ
t
DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
Notes
For this waveform ZZ is tied LOW.
25.
26. When CE is LOW, CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH, CE is HIGH, CE is LOW or CE is HIGH.
1
2
3
1
2
3
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 001-15029 Rev. *E
Page 27 of 35
[+] Feedback
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Switching Waveforms (continued)
Figure 7 shows ZZ Mode timing waveform.[28, 29]
Figure 7. ZZ Mode Timing
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
28. Device must be deselected when entering ZZ mode. See the Truth Table on page 12 for all possible signal conditions to deselect the device.
29. DQs are in high-Z when exiting ZZ sleep mode.
Document Number: 001-15029 Rev. *E
Page 28 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Ordering Information
Table 1 lists the CY7C1471BV33, CY7C1473BV33, CY7C1475BV33 key package features and ordering codes. The table contains
only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more
information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products.
Table 1. CY7C1471BV33, CY7C1473BV33, CY7C1475BV33 Key Features and Ordering Information
Speed
(MHz)
Package
Diagram
Operating
Ranges
Package
Ordering Code
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1471BV33-133AXC
CY7C1473BV33-133AXC
133
51-85050
Commercial
Ordering Code Definitions
CY 7C 14XX
B
V33 - XXX AX
C
Temperature Range:
C = Commercial
Package Type:
AX = 100-pin TQFP (Pb-free)
Speed Grade: XXX = 133 MHz
V33 = 3.3 V
Die Revision
Part Identifier: 14XX = 1471 (2 M × 36) or 1473 (4 M × 18)
Marketing Code: 7C = SRAM
Company ID: CY = Cypress
Document Number: 001-15029 Rev. *E
Page 29 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm)
51-85050 *D
Document Number: 001-15029 Rev. *E
Page 30 of 35
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Package Diagrams (continued)
Figure 9. 165-ball FBGA (15 × 17 × 1.4 mm)
51-85165 *C
Document Number: 001-15029 Rev. *E
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Package Diagrams (continued)
Figure 10. 209-ball FBGA (14 × 22 × 1.76 mm)
51-85167 *A
Document Number: 001-15029 Rev. *E
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Reference Information
Document Conventions
Units of Measure
Acronyms
Table 3. Units of Measure
Table 2. Acronyms
Symbol
°C
Unit of Measure
Acronym
Description
fine-pitch ball grid array
input/output
degree Celcius
kilo ohm
FBGA
I/O
kW
MHz
µA
µs
megahertz
microampere
microsecond
milliampere
millimeter
millisecond
millivolt
JTAG
LSB
joint test action group
least significant bit
most significant bit
phase-locked loop
static random access memory
test access port
test clock
MSB
PLL
mA
mm
ms
mV
ns
SRAM
TAP
TCK
TDI
nanosecond
ohm
test data-in
W
TDO
TMS
TQFP
test data-out
%
percent
test mode select
thin quad flat pack
pF
V
picofarad
volt
W
watt
Document Number: 001-15029 Rev. *E
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Document History Page
Document Title: CY7C1471BV33/CY7C1473BV33/CY7C1475BV33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-Through SRAM
with NoBL™ Architecture
Document Number: 001-15029
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
1024500
VKN/KKVT
MP
See ECN New Datasheet
*A
*B
1274731 VKN/AESA
2183566 VKN/PYRS
See ECN Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform
See ECN Converted from preliminary to final
Added footnote 16 related to IDD
*C
*D
*E
2898663
2905600
3298193
NJY
VKN
OSN
03/24/2010 Removed inactive parts from Ordering Information table; Updated package
diagrams.
04/06/2010 Removed inactive part CY7C1471BV33-117AXC from the ordering information
table.
06/30/2011 Updated template and styles to meet current CY standards.
Added table of contents.
Added Acronyms, Units and Ordering Information table.
Updated package diagrams:
51-85050 – *C to *D revision
51-85165 – *B to *C revision
Document Number: 001-15029 Rev. *E
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CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-15029 Rev. *E
Revised June 30, 2011
Page 35 of 35
All products and company names mentioned in this document may be the trademarks of their respective holders.
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