CY7C1471V33-100AXI [CYPRESS]
ZBT SRAM, 2MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-100;
| 型号： | CY7C1471V33-100AXI |
| 厂家： | 
CYPRESS |
| 描述： | ZBT SRAM, 2MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-100 静态存储器 |
| 文件： | 总30页 (文件大小：374K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through
SRAM with NoBL™ Architecture
• JTAG boundary scan for BGA and fBGA packages
• Burst Capability—linear or interleaved burst order
Features
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles.
• Low standby power
Functional Description[1]
• Can support up to 133-MHz bus operations with zero
wait states
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through
Burst SRAMs designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1471V33, CY7C1473V33 and
CY7C1475V33 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 8.5 ns (for 100-MHz device)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
• Offered in JEDEC-standard lead-free 100 TQFP, and
165-ball fBGA packages for CY7C1471V33 and
CY7C1473V33. Lead-free 209-ball fBGA package for
CY7C1475V33.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ
mode or CE deselect.
Selection Guide
133 MHz
6.5
100 MHz
8.5
Unit
ns
Maximum Access Time
Maximum Operating Current
335
305
mA
mA
Maximum CMOS Standby Current
150
150
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05288 Rev. *G
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 10, 2005
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Logic Block Diagram – CY7C1471V33 (2M x 36)
ADDRESS
REGISTER
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
MODE
C
BURST
LOGIC
CE
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD
A
B
U
F
MEMORY
ARRAY
BWA
BWB
BWC
BWD
WRITE
DRIVERS
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
A
B
C
D
A
M
P
F
E
R
S
S
WE
E
N
G
INPUT
REGISTER
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1473V33 (4M x 18)
ADDRESS
A0, A1, A
A1
A1'
A0'
REGISTER
D1
A0
Q1
Q0
D0
MODE
BURST
LOGIC
CE
ADV/LD
C
CLK
CEN
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD
A
B
U
F
MEMORY
ARRAY
BW
A
B
WRITE
DRIVERS
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
BW
A
B
A
M
P
F
E
R
S
S
WE
E
N
G
INPUT
REGISTER
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
ZZ
CONTROL
Document #: 38-05288
Page 2 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Logic Block Diagram – CY7C1475V33 (1M x 72)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
S
E
N
S
P
U
T
D
A
T
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
BW
BW
BW
a
R
E
G
I
S
T
E
R
S
MEMORY
ARRAY
E
B
U
F
DQs
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
WRITE
DRIVERS
b
S
T
E
E
R
I
A
M
P
a
b
c
d
e
f
c
F
BW
d
E
R
S
S
BW
e
BW
BW
f
N
G
g
E
E
BW
h
g
h
WE
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Document #: 38-05288
Page 3 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Pin Configurations
100-lead TQFP
DQPC
DQC
DQC
VDDQ
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
DQPB
DQB
DQB
VDDQ
VSS
2
3
4
5
DQC
6
DQB
BYTE C
BYTE B
DQB
DQC
DQC
DQC
VSS
7
8
DQB
DQB
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQC
DQC
NC
VDDQ
DQB
DQB
VSS
CY7C1471V33
VDD
NC
NC
VDD
ZZ
VSS
DQD
DQD
VDDQ
VSS
DQA
DQA
VDDQ
VSS
DQD
DQA
DQA
DQD
BYTE D
BYTE A
DQD
DQD
VSS
DQA
DQA
VSS
VDDQ
DQD
DQD
DQPD
VDDQ
DQA
DQA
DQPA
Document #: 38-05288
Page 4 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Pin Configurations (continued)
100-lead TQFP
NC
1
NC
2
NC
3
VDDQ
4
VSS
5
NC
6
NC
7
DQB
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
DQB
9
VSS
10
VDDQ
11
DQB
DQB
NC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1473V33
BYTE A
NC
VDD
NC
BYTE B
VDD
ZZ
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
VSS
VDDQ
NC
NC
NC
NC
NC
Document #: 38-05288
Page 5 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Pin Configurations (continued)
165-ball fBGA (3 Chip Enable with JTAG)
CY7C1471V33 (2M x 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE3
7
8
9
A
10
A
11
NC
NC / 576M
NC/1G
DQPC
CEN
WE
VSS
VSS
VSS
ADV/LD
A
B
C
D
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
A
A
NC
NC
DQC
VDDQ
VDDQ
NC
DQPB
DQB
DQC
VDD
DQB
DQC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
E
F
DQC
DQC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQB
ZZ
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
DQD
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
M
N
P
NC/144M
TDI
TDO
NC/288M
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
CY7C1473V33 (4M x 18)
1
NC / 576M
NC/1G
NC
2
A
3
CE1
4
BWB
5
NC
6
CE3
7
8
9
A
10
A
11
A
CEN
WE
VSS
VSS
ADV/LD
A
B
C
D
A
CE2
VDDQ
VDDQ
NC
VSS
VDD
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
A
A
NC
NC
DQB
VDDQ
VDDQ
NC
NC
DQPA
DQA
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
E
F
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQA
DQA
ZZ
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
M
N
P
NC/144M
TDI
TDO
NC/288M
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
Document #: 38-05288
Page 6 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Pin Configurations (continued)
209-ball PBGA
CY7C1475V33 (1M × 72)
1
2
3
4
5
6
7
8
9
10
11
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
A
CE2
A
ADV/LD
WE
A
A
CE3
BWSb
BWSe
NC
A
DQb
DQb
DQb
DQb
DQb
DQb
A
B
BWSc
BWSh
VSS
BWSg
NC
BWSf
BWSa
VSS
BWSd NC/576M CE1
NC
NC
C
D
NC/1G
OE
NC
DQb
DQb
DQPb
DQf
E
F
DQPg
DQc
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
NC
VDD
VSS
VDD
DQPf
DQf
VSS
VDDQ
VSS
VSS
VDDQ
VSS
G
H
J
DQc
DQc
NC
VDDQ
VSSQ
VDDQ
DQf
DQf
DQf
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
DQc
DQc
NC
NC
DQf
DQf
NC
VDDQ
DQc
NC
VDDQ
CLK
VDDQ
NC
NC
DQf
NC
K
L
CEN
NC
NC
NC
DQh
DQh
DQh
VDDQ
VSS
VDDQ
VSS
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
DQa
DQa
DQa
M
N
P
R
T
NC
VSS
VDDQ
VSS
VDDQ
NC
DQh
DQh
DQh
VSS
VDD
VSS
DQa
DQa
DQa
VDDQ
DQh
DQh
DQPd
DQd
DQd
NC
ZZ
DQa
DQa
DQPa
DQe
DQe
VSS
VDDQ
VDDQ
VDD
NC
A
DQPh
DQd
DQd
DQd
DQd
VDDQ
VDD
DQPe
DQe
DQe
DQe
DQe
VSS
VSS
NC
A
MODE
A
U
V
W
A
NC/288M
NC/144M
A
A
A1
A
DQd
DQd
A
A
A
A
DQe
DQe
TDI
TDO
TCK
A0
A
TMS
Document #: 38-05288
Page 7 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK. A[1:0] are fed to the two-bit burst counter.
BWA,BWB,BWC,
BWD, BWE, BWF,
BWG, BWH
Input-
Synchronous
Byte Write Inputs, active LOW. Qualified withWE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an access. After being deselected,
ADV/LD should be driven LOW in order to load a new address.
CLK
CE1
CE2
CE3
OE
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2, and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.
Input-
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic
Asynchronous block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, when the device has been deselected.
CEN
ZZ
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by
the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
does not deselect the device, CEN can be used to extend the previous cycle when required.
Input-
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
Asynchronous condition with data integrity preserved. During normal operation, this pin can be connected
to Vss or left floating.
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
DQs
memory location specified by the addresses presented during the previous
clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The
outputs are automatically tri-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs.During
write sequences, DQPX is controlled by BWX correspondingly.
DQPX
MODE
Input Strap Pin Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects
interleaved burst sequence.
VDD
VDDQ
VSS
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground
Ground for the device.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous
JTAG feature is not being utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be left floating or connected to VDD through a pull up
resistor. This pin is not available on TQFP packages.
Document #: 38-05288
Page 8 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Pin Definitions (continued)
Name
I/O
Description
TMS
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
NC
JTAG
-Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
-
No Connects. Not internally connected to the die. 144M, 288M, 576M and 1G are address
expansion pins and are not internally connected to the die.
supply a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD must be driven LOW
Functional Overview
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are
synchronous flow-through burst SRAMs designed specifically
to eliminate wait states during Write-Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133-MHz
device).
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and will wrap around when incre-
mented sufficiently. A HIGH input on ADV/LD will increment
the internal burst counter regardless of the state of chip enable
inputs or WE. WE is latched at the beginning of a burst cycle.
Therefore, the type of access (Read or Write) is maintained
throughout the burst sequence.
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct Byte Write operations.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The Write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs and DQPX.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
On the next clock rise the data presented to DQs and DQPX
(or a subset for Byte Write operations, see Truth Table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
Single Read Accesses
The data written during the Write operation is controlled by
BWX signals. The CY7C1471V33, CY7C1473V33 and
CY7C1475V33 provides Byte Write capability that is described
in the Truth Table. Asserting the Write Enable input (WE) with
the selected Byte Write Select input will selectively write to
only the desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the Write
operations. Byte Write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple byte write operations.
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Because
the
CY7C1471V33,
CY7C1473V33
and
CY7C1475V33 are common I/O devices, data should not be
driven into the device while the outputs are active. The Output
Enable (OE) can be deasserted HIGH before presenting data
to the DQs and DQPX inputs. Doing so will tri-state the output
drivers. As a safety precaution, DQs and DQPX are automati-
cally tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Read Accesses
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 have
an on-chip burst counter that allows the user the ability to
Document #: 38-05288
Page 9 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Burst Write Accesses
Interleaved Burst Address Table
(MODE = Floating or VDD
)
The CY7C1471V33, CY7C1473V33, and CY7C1475V33
have an on-chip burst counter that allows the user the ability
to supply a single address and conduct up to four Write opera-
tions without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
driven HIGH on the subsequent clock rise, the Chip Enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BWX inputs must be
driven in each cycle of the burst write, in order to write the
correct bytes of data.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
Unit
mA
ns
150
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ recovery time
ZZ < 0.2V
2tCYC
0
ns
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ns
Truth Table [2, 3, 4, 5, 6, 7, 8]
Address
Used
Operation
Deselect Cycle
CE1 CE2
ZZ ADV/LD
WE
X
BWX OE
CEN CLK
DQ
CE3
X
None
None
H
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L->H
L->H
L->H
L->H
Tri-State
Tri-State
Tri-State
Tri-State
Deselect Cycle
H
X
Deselect Cycle
None
X
X
Continue Deselect Cycle
None
X
H
X
X
Read Cycle
External
L
H
L->H Data Out (Q)
(Begin Burst)
Read Cycle
(Continue Burst)
Next
External
Next
X
L
X
H
X
H
X
L
L
L
L
L
H
L
X
H
X
L
X
X
X
L
L
H
H
X
L
L
L
L
L->H Data Out (Q)
NOP/Dummy Read
(Begin Burst)
L->H
L->H
Tri-State
Tri-State
Dummy Read
(Continue Burst)
X
L
X
L
H
L
Write Cycle (Begin Burst)
External
L->H Data In (D)
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
Selects are asserted, see Truth Table for details.
3. Write is defined by BW , and WE. See Truth Table for Read/Write.
X
4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQs and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
X
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQs and DQP = Tri-state when OE
X
is inactive or when the device is deselected, and DQs and DQP = data when OE is active.
X
Document #: 38-05288
Page 10 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Truth Table (continued)[2, 3, 4, 5, 6, 7, 8]
Address
Operation
Used
CE1 CE2
ZZ ADV/LD
WE
X
BWX OE
CEN CLK
DQ
CE3
X
Write Cycle (Continue Burst)
Next
X
L
X
H
X
X
X
L
L
L
L
H
H
L
L
H
H
X
X
X
X
X
X
X
L
L
L->H Data In (D)
NOP/Write Abort (Begin Burst) None
L
L
L->H
L->H
L->H
X
Tri-State
Tri-State
-
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Next
Current
None
X
X
X
X
H
X
X
X
L
X
X
H
X
X
X
Tri-State
Truth Table for Read/Write[2, 3, 9]
Function (CY7C1471V33)
Read
WE
H
L
BWA
BWB
BWC
BWD
X
X
H
L
X
H
H
L
X
H
H
H
L
Write No bytes written
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Byte C – (DQC and DQPC)
Write Byte D – (DQD and DQPD)
Write All Bytes
L
H
L
H
H
H
L
H
L
H
H
L
H
L
H
L
L
L
L
Truth Table for Read/Write[2, 3, 9]
Function (CY7C1473V33)
WE
H
L
BWB
BWA
X
Read
X
H
H
L
Write – No Bytes Written
H
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
L
L
L
H
L
L
L
Truth Table for Read/Write[2, 3, 9]
Function (CY7C1475V33)
WE
BWx
Read
H
L
L
L
X
Write – No Bytes Written
Write Byte X − (DQx and DQPx)
H
L
Write All Bytes
All BW = L
Note:
9. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.
X
Document #: 38-05288
Page 11 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Test MODE SELECT (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1471V33, CY7C1473V33, and CY7C1475V33
incorporate a serial boundary scan test access port (TAP).
This port operates in accordance with IEEE Standard
1149.1-1990 but does not have the set of functions required
for full 1149.1 compliance. These functions from the IEEE
specification are excluded because their inclusion places an
added delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not conflict
with the operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V
I/O logic levels.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See Tap Controller Block Diagram.)
The CY7C1471V33, CY7C1473V33, and CY7C1475V33
contain a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
TAP Controller State Diagram
Bypass Register
TEST-LOGIC
1
2
1
0
0
0
RESET
0
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
Selection
TDI
TDO
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
Circuitr
y
.
.
. 2 1
0
0
1
1
CAPTURE-DR
CAPTURE-IR
x
.
.
.
.
. 2 1
0
0
Boundary Scan Register
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
0
0
TAP CONTROLLER
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05288
Page 12 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
TAP Instruction Set
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold time (tCS plus tCH).
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
Document #: 38-05288
Page 13 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
possible to capture all other signals and simply ignore the
BYPASS
value of the CLK captured in the boundary scan register.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Clock
tTCYC
tTF
Description
Min.
Max
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
5
tTH
25
25
tTL
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
ns
ns
0
5
5
5
ns
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes:
10.t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
11.Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document #: 38-05288
Page 14 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50W
50W
TDO
TDO
ZO= 50W
ZO= 50W
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[12]
Parameter
VOH1
Description
Output HIGH Voltage IOH = –4.0 mA, VDDQ = 3.3V
OH = –1.0 mA, VDDQ = 2.5V
Test Conditions
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
I
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage IOH = –100 µA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
V
V
Output LOW Voltage IOL = 8.0 mA
0.4
0.4
V
IOL = 1.0 mA
V
Output LOW Voltage IOL = 100 µA
0.2
V
VDDQ = 2.5V
0.2
V
Input HIGH Voltage
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
2.0
1.7
VDD + 0.3
VDD + 0.3
0.8
V
V
VIL
Input LOW Voltage
–0.3
–0.3
–5
V
VDDQ = 2.5V
0.7
V
IX
Input Load Current
GND < VIN < VDDQ
5
µA
Identification Register Definitions
CY7C1471V33 CY7C1473V33 CY7C1475V33
Instruction Field
Revision Number (31:29)
Device Depth (28:24)[13]
(2Mx36)
(4Mx18)
(1Mx72)
Description
000
000
000
Describes the version number
Reserved for internal use
01011
01011
01011
001001
110100
Architecture/Memory Type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
001001
100100
00000110100
001001
010100
00000110100
Defines memory type and architecture
Defines width and density
00000110100 Allows unique identification of SRAM
vendor
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID register
Notes:
12. All voltages referenced to V (GND).
SS
13. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05288
Page 15 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
Instruction
3
1
3
1
3
1
Bypass
ID
32
71
-
32
52
-
32
-
Boundary Scan Order–165FBGA
Boundary Scan Order– 209BGA
110
Identification Codes
Instruction
EXTEST
Code
Description
000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE
001 Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
RESERVED
BYPASS
101 Do Not Use: This instruction is reserved for future use.
110 Do Not Use: This instruction is reserved for future use.
111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05288
Page 16 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Boundary Scan Exit Order (x36) (continued)
Boundary Scan Exit Order (x36)
Bit #
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
165-Ball ID
M11
L11
M10
L10
K11
J11
K10
J10
H11
G11
F11
E11
D10
D11
C11
G10
F10
E10
A10
B10
A9
Bit #
1
165-Ball ID
C1
D1
E1
D2
E2
F1
2
3
4
5
6
7
G1
F2
8
9
G2
J1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
K1
L1
J2
M1
N1
K2
L2
M2
R1
R2
R3
P2
R4
P6
R6
N6
P11
R8
P3
P4
P8
P9
P10
R9
R10
R11
N11
B9
A8
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
Document #: 38-05288
Page 17 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Boundary Scan Exit Order (x18) (continued)
Boundary Scan Exit Order (x18)
Bit #
45
46
47
48
49
50
51
52
53
54
165-Ball ID
Bit #
1
165-Ball ID
A7
B7
B6
A6
B5
A4
B3
A3
A2
B2
D2
E2
2
3
F2
4
G2
J1
5
6
K1
7
L1
8
M1
N1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
R1
R2
Boundary Scan Exit Order (x72)
R3
Bit #
1
209-Ball ID
P2
A1
A2
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
G1
G2
H1
H2
J1
R4
2
P6
3
R6
4
N6
5
P11
R8
6
7
P3
8
P4
9
P8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
P9
P10
R9
R10
R11
M10
L10
K10
J10
H11
G11
F11
E11
D11
C11
A11
A10
B10
A9
J2
L1
L2
M1
M2
N1
N2
P1
P2
R2
R1
T1
T2
U1
B9
A8
B8
Document #: 38-05288
Page 18 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Boundary Scan Exit Order (x72) (continued)
Boundary Scan Exit Order (x72) (continued)
Bit #
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
209-Ball ID
U2
Bit #
76
209-Ball ID
H10
G11
G10
F11
F10
E10
E11
D11
D10
C11
C10
B11
B10
A11
A10
A9
V1
77
V2
78
W1
W2
T6
79
80
81
V3
82
V4
83
U4
84
W5
V6
85
86
W6
U3
87
88
U9
89
V5
90
U5
91
U6
92
U8
W7
V7
93
A7
94
A5
U7
95
A6
V8
96
D6
V9
97
B6
W11
W10
V11
V10
U11
U10
T11
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
L10
P6
98
D7
99
K3
100
101
102
103
104
105
106
107
108
109
110
111
112
A8
B4
B3
C3
C4
C8
C9
B9
B8
A4
C6
B7
A3
J11
J10
H11
Document #: 38-05288
Page 19 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Range
Temperature
VDD
VDDQ
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
to VDD
Industrial
-40°C to +85°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range[14, 15]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
Unit
V
VDDQ
for 3.3V I/O
for 2.5V I/O
VDD
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
for 3.3V I/O, IOH = –4.0 mA
for 2.5V I/O, IOH = –1.0 mA
for 3.3V I/O, IOL = 8.0 mA
for 2.5V I/O, IOL = 1.0 mA
V
2.0
V
0.4
0.4
V
V
Input HIGH Voltage[14] for 3.3V I/O
2.0
1.7
VDD + 0.3V
VDD + 0.3V
0.8
V
for 2.5V I/O
V
Input LOW Voltage[14]
for 3.3V I/O
–0.3
–0.3
–5
V
for 2.5V I/O
0.7
V
Input Load Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
5
µA
Input Current of MODE Input = VSS
Input = VDD
–5
–30
–5
µA
µA
30
Input Current of ZZ
Input = VSS
Input = VDD
µA
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
5
µA
VDD Operating Supply VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
335
305
200
200
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX, inputs switching
Automatic CE
Power-down
Current—CMOS Inputs f = 0, inputs static
VDD = Max, Device Deselected,
VIN ≤ 0.3V or VIN > VDD – 0.3V,
All speeds
150
mA
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX, inputs switching
V
DD = Max, Device Deselected, or 7.5-ns cycle, 133 MHz
200
200
mA
mA
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
10-ns cycle, 100 MHz
ISB4
Automatic CE
Power-down
Current—TTL Inputs
V
DD = Max, Device Deselected,
All Speeds
165
mA
VIN ≥ VDD – 0.3V or VIN
f = 0, inputs static
≤
,
0.3V
Notes:
14. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
15. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05288
Page 20 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Thermal Resistance[16]
100 TQFP 165 fBGA
209 BGA
Typ.
Parameter
Description
Test Conditions
Typ.
Typ.
Unit
ΘJA
Thermal Resistance Test conditions follow standard test
(Junction to Ambient) methods and procedures for
24.63
16.3
15.2
°C/W
measuringthermalimpedance, per
EIA / JESD51.
ΘJC
Thermal Resistance
(Junction to Case)
2.28
2.1
1.7
°C/W
Capacitance[16]
100 TQFP 165-fBGA 209-BGA
Parameter
CADDRESS
CDATA
Description
Test Conditions
Max.
Max.
Max.
Unit
Address Input Capacitance
Data Input Capacitance
Control Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
TA = 25°C, f = 1 MHz,
VDD = 3.3V
DDQ = 2.5V
6
5
8
6
5
6
5
8
6
5
6
5
8
6
5
pF
pF
pF
pF
pF
V
CCTRL
CCLK
CI/O
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
16. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05288
Page 21 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Switching Characteristics Over the Operating Range[21, 22]
133 MHz
100 MHz
Parameter
tPOWER‘
Clock
tCYC
Description
Min.
Max.
Min.
Max.
Unit
1
1
ms
Clock Cycle Time
7.5
2.5
2.5
10
3.0
3.0
ns
ns
ns
tCH
Clock HIGH
Clock LOW
tCL
Output Times
tCDV
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[18, 19, 20]
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
tDOH
2.5
3.0
2.5
3.0
tCLZ
tCHZ
Clock to High-Z[18, 19, 20]
3.8
3.0
4.5
3.8
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low-Z[18, 19, 20]
OE HIGH to Output High-Z[18, 19, 20]
0
0
3.0
4.0
Address Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
WE, BWX Set-up Before CLK Rise
CEN Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tALS
tWES
tCENS
tDS
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADV/LD Hold After CLK Rise
WE, BWX Hold After CLK Rise
CEN Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tALH
tWEH
tCENH
tDH
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes:
17. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially, before a Read or Write operation
DD
POWER
can be initiated.
18. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
19. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
20. This parameter is sampled and not 100% tested.
21. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05288
Page 22 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Switching Waveforms
Read/Write Waveforms[23, 24, 25]
t
1
2
3
4
5
6
7
8
9
10
CYC
t
CLK
CEN
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CE
ADV/LD
WE
BW
X
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
For this waveform ZZ is tied LOW.
23.
24. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
25. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05288
Page 23 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Switching Waveforms (continued)
NOP, STALL and DESELECT Cycles[23, 24, 26]
t
1
2
3
4
5
6
7
8
9
10
CYC
CLK
CEN
t
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CE
ADV/LD
WE
BW
X
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Note:
26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A Write is not performed during this cycle.
Document #: 38-05288
Page 24 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Switching Waveforms (continued)
ZZ Mode Timing[27, 28]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Part and Package Type
133
CY7C1471V33-133AXC
CY7C1473V33-133AXC
CY7C1471V33-133BZC
CY7C1473V33-133BZC
CY7C1475V33-133BGC
A101
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BB165C 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
BB165C 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1471V33-133BZXC BB165C Lead-Free 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4
mm)
CY7C1473V33-133BZXC BB165C Lead-Free 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4
mm)
CY7C1475V33-133BGXC BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
100
CY7C1471V33-100AXC
CY7C1473V33-100AXC
CY7C1471V33-100BZC
CY7C1473V33-100BZC
CY7C1475V33-100BGC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
BB165C 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
BB165C 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1471V33-100BZXC BB165C Lead-Free 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4
mm)
CY7C1473V33-100BZXC BB165C Lead-Free 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4
mm)
CY7C1475V33-100BGXC BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
Please contact your local Cypress sales representative for availability of these parts.
Notes:
27. Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device.
28. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05288
Page 25 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Part and Package Type
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
133
CY7C1471V33-133AXI
CY7C1473V33-133AXI
CY7C1471V33-133BZI
CY7C1473V33-133BZI
CY7C1475V33-133BGI
CY7C1471V33-133BZXI
A101
Industrial
BB165C 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
BB165C 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
BB165C Lead-Free 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4
mm)
CY7C1473V33-133BZXI
BB165C Lead-Free 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4
mm)
CY7C1475V33-133BGXI
CY7C1471V33-100AXI
CY7C1473V33-100AXI
CY7C1471V33-100BZI
CY7C1473V33-100BZI
CY7C1475V33-100BGI
CY7C1471V33-100BZXI
BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
100
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
BB165C 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
BB165C 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
BB165C Lead-Free 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4
mm)
CY7C1473V33-100BZXI
CY7C1475V33-100BGXI
BB165C Lead-Free 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4
mm)
BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05288
Page 26 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05288
Page 27 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Package Diagrams (continued)
165-Ball FBGA (15 x 17 x 1.40 mm) BB165C
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45 0.05ꢀ1ꢁ5ꢂX
1
2
3
4
5
ꢁ
7
8
9
10
11
11 10
9
8
7
ꢁ
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15ꢀ4ꢂX
SEATING PLANE
C
51-85165-*A
Document #: 38-05288
Page 28 of 30
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Package Diagrams (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) BB209A
51-85167-**
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05288
Page 29 of 30
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Cypressproductsarenotwarrantednorintendedtobeusedformedical, life-support, life-saving, criticalcontrolorsafetyapplications, unlesspursuanttoanexpresswrittenagreementwithCypress.
CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Document History Page
Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
with NoBL™ Architecture
Document #: 38-05288
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
114675
121521
08/06/02
02/07/03
PKS
CJM
New Data Sheet
*A
Updated features for package offering
Updated ordering information
Changed Advanced Information to Preliminary
*B
223721
See ECN
NJY
Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Removed 150-MHz speed grade offering
Included ISB and IDD values
Changed package outline for 165FBGA package and 209-ball BGA package
Removed 119-BGA package offering
*C
*D
*E
235012
243572
299511
See ECN
See ECN
See ECN
RYQ
NJY
SYT
Minor Change: The data sheets do not match on the spec system and
external web.
Changed ball H2 from VDD to NC in the 165-ball FBGA package in page 6
Modified capacitance values on page 21
Removed 117-MHz Speed Bin
Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100
TQFP Package on Page # 21
Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA
Packages
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
*F
320197
331513
See ECN
See ECN
PCI
PCI
Corrected part number typos in the logic block diagram on page# 2
*G
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Added Industrial Operating Range
Modified VOL, VOH Test Conditions
Updated Ordering Information Table
Document #: 38-05288
Page 30 of 30
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