CY7C1472V33-250AXC [CYPRESS]
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; 72兆位（ 2M ×36 / 4M ×18 / 1M X 72 ）流水线SRAM与NOBL架构
| 型号： | CY7C1472V33-250AXC |
| 厂家： | 
CYPRESS |
| 描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| 文件： | 总28页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined
SRAM with NoBL™ Architecture
Features
Functional Description
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200, and 167 MHz
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write operations with no wait states. The
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1470V33, CY7C1472V33,
and CY7C1474V33 are pin compatible and functionally equiv-
alent to ZBT devices.
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output time
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
— 3.0 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
Write operations are controlled by the Byte Write Selects
(BWa–BWh for CY7C1474V33, BWa–BWd for CY7C1470V33
and BWa–BWb for CY7C1472V33) and a Write Enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
• CY7C1470V33 and CY7C1472V33 available in lead-free
100 TQFP, and 165-ball fBGA packages. CY7C1474V33
available in 209-ball fBGA package
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Logic Block Diagram-CY7C1470V33 (2M x 36)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
WRITE
DRIVERS
BW
BW
a
a
b
c
d
A
M
P
b
BW
BW
c
S
T
E
R
S
F
d
E
R
S
S
WE
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
Document #: 38-05289 Rev. *E
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 23, 2004
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Logic Block Diagram-CY7C1474V33 (1M x 72)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
BWa
BWb
BWc
BWd
BWe
BWf
BWg
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
S
T
E
R
S
MEMORY
ARRAY
E
B
U
F
DQs
WRITE
DRIVERS
S
T
E
E
R
I
A
M
P
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
a
b
c
d
e
f
F
E
R
S
S
N
G
E
E
BWh
g
h
WE
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
CE1
CE2
CE3
READ LOGIC
Sleep
Control
ZZ
Logic Block Diagram-CY7C1472V33 (4M x 18)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
Q1
D1
D0
A0'
BURST
LOGIC
Q0
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
O
U
T
P
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
S
T
E
R
S
MEMORY
ARRAY
E
B
U
F
DQs
DQP
DQP
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
a
F
b
b
E
R
S
S
N
G
WE
E
E
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Selection Guide
CY7C1470V33-250 CY7C1470V33-200 CY7C1470V33-167
CY7C1472V33-250 CY7C1472V33-200 CY7C1472V33-167
CY7C1474V33-250 CY7C1474V33-200 CY7C1474V33-167
Unit
ns
Maximum Access Time
3.0
500
120
3.0
500
120
3.4
450
120
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information.
mA
mA
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05289 Rev. *E
Page 2 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Pin Configurations
100-pin TQFP Packages
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
78
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
V
V
DDQ
VDDQ
VSS
V
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
V
SS
SS
DQc
DQc
NC
NC
DQb
NC
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
DQPa
DQa
DQa
DQc
DQc
9
DQb
9
V
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
V
V
DDQ
DDQ
V
DQa
DQa
DDQ
DQc
DQc
NC
DQb
DQb
NC
V
CY7C1470V33
(2M × 36)
SS
V
V
DD
DD
NC
CY7C1472V33
(4M × 18)
NC
NC
VDD
ZZ
DQa
DQa
V
DD
V
V
SS
SS
ZZ
DQd
DQb
DQb
DQa
DQa
DQd
V
V
DDQ
DDQ
VDDQ
VSS
DQa
DQa
V
DDQ
V
V
SS
SS
V
SS
DQd
DQd
DQd
DQd
DQb
DQb
DQa DQPb
DQa
DQa
NC
DQa
VSS
VDDQ
DQa
DQa
DQPa
NC
NC
V
SS
V
V
SS
SS
V
V
DDQ
DQd
DDQ
V
DDQ
NC
NC
NC
NC
NC
NC
DQd
DQPd
Document #: 38-05289 Rev. *E
Page 3 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Pin Configurations (continued)
165-Ball fBGA Pinout
CY7C1470V33 (2M × 36)
1
2
A
3
4
5
6
7
8
9
A
10
A
11
NC
E(288)
ADV/LD
A
B
C
D
CE1
BWc
BWd
VSS
VDD
BWb
BWa
VSS
VSS
CE3
CLK
VSS
VSS
CEN
WE
NC
A
CE2
VDDQ
VDDQ
OE
VSS
VDD
A
A
E(144)
DQPb
DQb
DQPc
DQc
NC
DQc
VSS
VSS
VDDQ
VDDQ
NC
DQb
DQc
DQc
DQc
NC
DQc
DQc
DQc
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
E
F
G
H
J
DQd
DQd
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
K
L
DQd
DQPd
NC
DQd
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
DQa
DQPa
NC
M
N
P
TDI
TDO
A
MODE
A
A
TMS
A0
TCK
A
A
A
A
R
CY7C1472V33 (4M × 18)
1
E(288)
NC
2
A
3
4
5
NC
6
CE3
7
8
9
A
10
A
11
A
A
B
C
D
CE1
BWb
NC
CEN
ADV/LD
A
CE2
VDDQ
VDDQ
BWa
VSS
VSS
CLK
VSS
VSS
A
A
E(144)
DQPa
DQa
WE
VSS
VSS
OE
VSS
VDD
NC
NC
DQb
VSS
VDD
VDDQ
VDDQ
NC
NC
NC
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQa
DQa
DQa
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
NC
NC
NC
K
L
NC
NC
DQb
DQPb
NC
NC
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
NC
NC
NC
M
N
P
TDI
TDO
A
MODE
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05289 Rev. *E
Page 4 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Pin Configurations (continued)
209-ball PBGA
CY7C1474V33 (1M X 72)
1
2
3
4
5
6
7
8
9
10
11
DQg
DQg
DQg
DQg
A
CE2
A
ADV/LD
WE
A
A
CE3
A
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
B
BWSc
BWSg
BWSd
NC
BWSb
BWSf
DQg
DQg
DQg
DQg
BWSh
VSS
NC
NC
CE1
OE
NC
NC
BWSe
NC
BWSa
VSS
C
D
NC
DQb
DQPb
DQf
E
F
DQPg
DQc
DQPc
DQc
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
NC
VDD
VSS
VDD
DQPf
DQf
VSS
VDDQ
VSS
VSS
VDDQ
VSS
G
H
J
DQc
DQc
DQc
NC
VDDQ
VSSQ
VDDQ
DQf
DQf
DQf
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
DQc
DQc
NC
NC
DQf
DQf
NC
VDDQ
DQc
NC
VDDQ
CLK
VDDQ
NC
NC
DQf
NC
K
L
CEN
NC
NC
VDDQ
VSS
NC
DQh
DQh
DQh
VDDQ
VSS
VDDQ
VSS
VDDQ
VDDQ
VSS
VDDQ
VSS
DQa
DQa
DQa
M
N
P
R
T
NC
VSS
VDDQ
VSS
VDDQ
NC
DQh
DQh
DQh
VSS
VDD
VSS
DQa
DQa
DQa
VDDQ
DQh
DQh
DQPd
DQd
DQd
NC
ZZ
DQa
DQa
DQPa
DQe
DQe
VSS
VDDQ
VSS
VDDQ
VDD
NC
A
DQPh
DQd
DQd
DQd
DQd
VDDQ
VDD
DQPe
DQe
DQe
DQe
DQe
VSS
NC
A
MODE
A
U
V
W
A
NC
NC
A
A
A1
A
DQd
DQd
A
A
A
A
DQe
DQe
TDI
TDO
TCK
A0
A
TMS
Document #: 38-05289 Rev. *E
Page 5 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Pin Definitions
Pin Name
I/O Type
Input-
Synchronous the CLK.
Pin Description
A0
A1
A
Address Inputs used to select one of the address locations. Sampled at the rising edge of
BWa
BWb
BWc
BWd
BWe
BWf
Input-
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Synchronous Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf
controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
BWg
BWh
Input-
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
WE
Synchronous signal must be asserted LOW to initiate a write sequence.
Input- Advance/Load Input used to advance the on-chip address counter or load a new address.
ADV/LD
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
CLK
CE1
CE2
CE3
OE
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select/deselect the device.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select/deselect the device.
Input-
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
CEN
DQS
Input-
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
Synchronous SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automat-
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
DQPX
I/O-
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQX. During write
Synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg
is controlled by BWg, DQPh is controlled by BWh.
MODE
TDO
TDI
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
JTAG Serial
Output
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
JTAG Serial Input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
Document #: 38-05289 Rev. *E
Page 6 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
JTAG Clock
Clock input to the JTAG circuitry.
VDD
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
VDDQ
VSS
Ground
Ground for the device. Should be connected to ground of the system.
NC
–
–
No connects. This pin is not connected to the die.
E(144, 288)
ZZ
These pins are not connected. They will be used for expansion to the 144M and 288M densities.
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. During normal operation, this pin can be connected to Vss or left
floating.
OE and the internal control logic. OE must be driven LOW in
Functional Overview
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will tri-state following the
next clock rise.
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
synchronous-pipelined Burst NoBL SRAMs designed specifi-
cally to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 3.0 ns (225-MHz device).
Burst Read Accesses
The CY7C1470V33/CY7C1472V33/CY7C1474V33 have an
on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and will wrap-around when incre-
mented sufficiently. A HIGH input on ADV/LD will increment
the internal burst counter regardless of the state of chip
enables inputs or WE. WE is latched at the beginning of a burst
cycle. Therefore, the type of access (Read or Write) is
maintained throughout the burst sequence.
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BW[x] can be used to
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
Writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to the address inputs
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 3.0 ns
(225-MHz device) provided OE is active LOW. After the first
clock of the Read access the output buffers are controlled by
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1474V33,
DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for
CY7C1472V33). In addition, the address for the subsequent
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1474V33,
DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 & DQa,b/DQPa,b for
CY7C1472V33) (or a subset for byte write operations, see
Document #: 38-05289 Rev. *E
Page 7 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
CY7C1472V33) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
The data written during the Write operation is controlled by BW
Sleep Mode
(BWa,b,c,d,e,f,g,h
for
CY7C1474V33,
BWa,b,c,d
for
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
CY7C1470V33 and BWa,b for CY7C1472V33) signals. The
CY7C1470V33/CY7C1472V33/CY7C1474V33 provides Byte
Write capability that is described in the Write Cycle Description
table. Asserting the Write Enable input (WE) with the selected
Byte Write Select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
Write mechanism has been provided to simplify the Write
operations. Byte Write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple Byte Write operations.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
Because the CY7C1470V33/CY7C1472V33/CY7C1474V33
are common I/O devices, data should not be driven into the
device while the outputs are active. The Output Enable (OE)
can be deasserted HIGH before presenting data to the DQ and
DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V33,
DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for
CY7C1472V33) inputs. Doing so will tri-state the output
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
00
A1,A0
01
A1,A0
10
A1,A0
11
01
00
11
10
drivers. As a safety precaution, DQ and DQP (DQa,b,c,d,e,f,g,h
/
10
11
00
01
DQPa,b,c,d,e,f,g,h for CY7C1474V33, DQa,b,c,d/ DQPa,b,c,d for
CY7C1470V33 and DQa,b/DQPa,b for CY7C1472V33) are
automatically tri-stated during the data portion of a Write cycle,
regardless of the state of OE.
11
10
01
00
Linear Burst Address Table
(MODE = GND)
Burst Write Accesses
The CY7C1470V33/CY7C1472V33/CY7C1474V33 has an
on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four Write operations
without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
driven HIGH on the subsequent clock rise, the Chip Enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for
CY7C1474V33, BWa,b,c,d for CY7C1470V33 and BWa,b for
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
00
A1,A0
01
A1,A0
10
A1,A0
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min.
Max
Unit
mA
ns
ZZ > VDD − 0.2V
120
tZZS
ZZ > VDD − 0.2V
2tCYC
tZZREC
tZZI
ZZ < 0.2V
2tCYC
0
ns
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ns
Document #: 38-05289 Rev. *E
Page 8 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Truth Table[1, 2, 3, 4, 5, 6, 7]
Address
Used
Operation
CE
H
ZZ
L
ADV/LD WE BWx
OE
CEN CLK
L-H
DQ
Deselect Cycle
None
L
X
X
X
X
X
L
L
Tri-State
Tri-State
Continue
None
X
L
H
X
L-H
Deselect Cycle
Read Cycle
(Begin Burst)
External
Next
L
X
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
X
H
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Data Out (Q)
Data Out (Q)
Tri-State
Tri-State
Data In (D)
Data In (D)
Tri-State
Tri-State
-
Read Cycle
(Continue Burst)
L
NOP/Dummy Read External
(Begin Burst)
H
H
X
X
X
X
X
X
Dummy Read
(Continue Burst)
Next
X
L
H
L
Write Cycle
(Begin Burst)
External
Next
Write Cycle
(Continue Burst)
X
L
H
L
X
L
L
NOP/Write Abort
(Begin Burst)
None
Next
H
H
X
X
Write Abort
(Continue Burst)
X
X
X
H
X
X
X
X
X
Ignore Clock Edge
(Stall)
Current
None
H
X
L-H
X
Sleep Mode
Tri-State
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW
. See Write Cycle Description table for details.
[a:d]
3. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ and DQP
= Tri-state when
s
[a:d]
OE is inactive or when the device is deselected, and DQ = data when OE is active.
s
Document #: 38-05289 Rev. *E
Page 9 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1470V33)
Read
BWd
BWc
X
BWb
X
H
H
L
BWa
X
H
L
WE
H
L
X
H
H
H
H
H
H
H
H
L
Write – No bytes written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Bytes b, a
H
H
H
H
L
L
L
H
L
L
L
Write Byte c – (DQc and DQPc)
Write Bytes c, a
L
H
H
L
H
L
L
L
Write Bytes c, b
L
LL
L
H
L
Write Bytes c, b, a
L
L
Write Byte d – (DQd and DQPd)
Write Bytes d, a
L
H
H
H
H
L
H
H
L
H
L
L
L
Write Bytes d, b
L
L
H
L
Write Bytes d, b, a
L
L
L
Write Bytes d, c
L
L
H
H
L
H
L
Write Bytes d, c, a
L
L
L
Write Bytes d, c, b
L
L
L
H
L
Write All Bytes
L
L
L
L
Function (CY7C1472V33)
Read
WE
H
L
BWb
BWa
x
H
H
L
x
H
L
Write – No Bytes Written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
L
L
H
L
L
L
Function (CY7C1474V33)
Read
WE
BWx
H
L
L
L
x
Write – No Bytes Written
H
L
Write Byte X − (DQx and DQPx)
Write All Bytes
All BW = L
Note:
8. Table only lists a partial listing of the Byte Write combinations. Any combination of BW
active.
is valid. Appropriate Write will be done based on which Byte Write is
[a:d]
Document #: 38-05289 Rev. *E
Page 10 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Test MODE SELECT (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1470V33/CY7C1472V33/CY7C1474V33 incorpo-
rates a serial boundary scan test access port (TAP). This port
operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See Tap Controller Block Diagram.)
The CY7C1470V33/CY7C1472V33/CY7C1474V33 contains
a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
TEST-LOGIC
1
RESET
0
2
1
0
0
0
1
1
1
Selection
Circuitry
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
Instruction Register
31 30 29
Identification Register
0
S
election
TDI
TDO
Circuitr
y
0
0
.
.
. 2 1
1
1
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
. 2 1
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
0
0
TAP CONTROLLER
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Test Access Port (TAP)
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05289 Rev. *E
Page 11 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
TAP Instruction Set
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold time (tCS plus tCH).
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
Document #: 38-05289 Rev. *E
Page 12 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
possible to capture all other signals and simply ignore the
BYPASS
value of the CLK captured in the boundary scan register.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Clock
tTCYC
tTF
Description
Min.
Max
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
5
tTH
25
25
tTL
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
ns
ns
0
5
5
5
ns
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes:
t
9.
and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CH
CS
10. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document #: 38-05289 Rev. *E
Page 13 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
ZO= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11]
Parameter
VOH1
Description
Output HIGH Voltage IOH = –4.0 mA,VDDQ = 3.3V
OH = –1.0 mA,VDDQ = 2.5V
Test Conditions
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
I
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage IOH = –100 µA
VDDQ = 3.3V
DDQ = 2.5V
V
V
V
Output LOW Voltage IOL = 8.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
0.4
0.4
V
IOL = 1.0 mA
V
Output LOW Voltage IOL = 100 µA
0.2
V
0.2
V
Input HIGH Voltage
2.0
1.7
VDD + 0.3
VDD + 0.3
0.8
V
V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
V
VIL
Input LOW Voltage
–0.3
–0.3
–5
V
V
0.7
V
IX
Input Load Current
GND < VIN < VDDQ
5
µA
Note:
11. All voltages referenced to V (GND.
SS
Document #: 38-05289 Rev. *E
Page 14 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Identification Register Definitions
CY7C1470V33
CY7C1472V33
(4M x 18)
CY7C1474V33
Instruction Field
Revision Number (31:29)
Device Depth (28:24)[12]
(2M x 36)
(1M x 72)
Description
000
000
000
Describes the version number
Reserved for internal use
01011
01011
001000
01011
Architecture/Memory
Type(23:18)
001000
001000
Defines memory type and archi-
tecture
Bus Width/Density(17:12)
100100
010100
110100
Defines width and density
Cypress JEDEC ID Code
(11:1)
00000110100
00000110100
00000110100
Allows unique identification of
SRAM vendor
ID Register Presence
Indicator (0)
1
1
1
Indicates the presence of an ID
register
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
Instruction
3
1
3
1
3
1
Bypass
ID
32
71
-
32
52
-
32
-
Boundary Scan Order-165FBGA
Boundary Scan Order- 209BGA
110
Identification Codes
Instruction
EXTEST
Code
Description
000
001
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
Note:
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05289 Rev. *E
Page 15 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Boundary Scan Exit Order (x36) (continued)
Boundary Scan Exit Order (x36)
Bit #
165-Ball ID
J10
H11
G11
F11
E11
D10
D11
C11
G10
F10
E10
A10
B10
A9
Bit #
1
165-Ball ID
C1
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
2
D1
3
E1
4
D2
5
E2
6
F1
7
G1
F2
8
9
G2
J1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
K1
L1
J2
M1
N1
B9
A8
K2
B8
L2
A7
M2
R1
B7
B6
R2
A6
R3
B5
P2
A5
R4
A4
P6
B4
R6
B3
N6
A3
P11
R8
A2
B2
P3
P4
Boundary Scan Exit Order (x72)
P8
Bit #
1
209-Ball ID
P9
A1
A2
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
P10
R9
2
3
R10
R11
N11
M11
L11
M10
L10
K11
J11
K10
4
5
6
7
8
9
10
11
12
Document #: 38-05289 Rev. *E
Page 16 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Boundary Scan Exit Order (x72) (continued)
Boundary Scan Exit Order (x72) (continued)
Bit #
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
209-Ball ID
G1
G2
H1
H2
J1
Bit #
209-Ball ID
V10
U11
U10
T11
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
L10
P6
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
J2
L1
L2
M1
M2
N1
N2
P1
P2
R2
R1
T1
J11
T2
J10
H11
H10
G11
G10
F11
F10
E10
E11
D11
D10
C11
C10
B11
B10
A11
A10
A9
U1
U2
V1
V2
W1
W2
T6
V3
V4
U4
W5
V6
W6
U3
U9
V5
U5
U6
W7
V7
U8
A7
A5
U7
V8
A6
D6
V9
B6
W11
W10
V11
D7
K3
A8
Document #: 38-05289 Rev. *E
Page 17 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Boundary Scan Exit Order (x72) (continued)
Boundary Scan Exit Order (x18) (continued)
Bit #
101
102
103
104
105
106
107
108
109
110
111
209-Ball ID
30
K10
J10
H11
G11
F11
E11
D11
C11
A11
A10
B10
A9
B4
B3
C3
C4
C8
C9
B9
B8
A4
C6
B7
A3
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
112
B9
A8
Boundary Scan Exit Order (x18)
B8
Bit #
1
165-Ball ID
D2
A7
B7
2
E2
B6
3
F2
A6
4
G2
B5
5
J1
A4
6
K1
B3
7
L1
A3
8
M1
N1
A2
9
B2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
R1
R2
R3
P2
R4
P6
R6
N6
P11
R8
P3
P4
P8
P9
P10
R9
R10
R11
M10
L10
Document #: 38-05289 Rev. *E
Page 18 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Temperature
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC to Outputs in Tri-State................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Range
VDD
VDDQ
Commercial 0°C to +70°C
Industrial -40°C to +85°C
3.3V –
5%/+10%
2.5V – 5%
to VDD
Electrical Characteristics Over the Operating Range[13, 14]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
Unit
V
3.6
VDD
VDDQ
VOH
VOL
VIH
VIL
VDDQ = 3.3V
VDDQ = 2.5V
V
2.625
V
Output HIGH Voltage
Output LOW Voltage
VDD = Min., IOH = −4.0 mA, VDDQ = 3.3V
VDD = Min., IOH= −1.0 mA, VDDQ = 2.5V
VDD = Min., IOL= 8.0 mA, VDDQ = 3.3V
VDD = Min., IOL= 1.0 mA, VDDQ = 2.5V
V
2.0
V
0.4
0.4
V
V
Input HIGH Voltage[13] VDDQ = 3.3V
2.0
1.7
VDD + 0.3V
V
VDDQ = 2.5V
VDD + 0.3V
V
Input LOW Voltage[13] VDDQ = 3.3V
VDDQ = 2.5V
–0.3
–0.3
–5
0.8
0.7
5
V
V
IX
Input Load Current ex- GND ≤ VI ≤ VDDQ
cept ZZ and MODE
µA
Input Current of MODE Input = VSS
Input = VDD
–5
–30
–5
µA
µA
30
Input Current of ZZ
Input = VSS
Input = VDD
µA
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
5
µA
VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
500
500
450
245
245
245
120
mA
mA
mA
mA
mA
mA
mA
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX =
1/tCYC
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB2
Automatic CE
Power-down
Current—CMOS Inputs f = 0
Max. VDD, Device Deselected, All speed grades
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
ISB3
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX = 1/tCYC
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
245
245
245
135
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB4
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL, f = 0
Shaded areas contain advance information.
Notes:
13. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
.
14. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
Power-up
DD
IH
DD
DDQ DD
Document #: 38-05289 Rev. *E
Page 19 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Capacitance[15]
TQFP
Max.
209-BGA 165-fBGA
Parameter
Description
Test Conditions
Max.
Max.
Unit
pF
CADDRESS
CDATA
CCTRL
CCLK
Address Input Capacitance
Data Input Capacitance
Control Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
TA = 25°C, f = 1 MHz,
DD = 3.3V
DDQ = 2.5V
6
5
8
6
5
6
5
8
6
5
6
5
8
6
5
V
V
pF
pF
pF
CI/O
pF
Thermal Resistance[15]
165 fBGA
Package
209 BGA
TQFP
Parameters
Description
Test Conditions
Package Package Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA / JESD51.
16.3
15.2
1.7
24.63
2.28
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
2.1
°C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
10%
L
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
10%
L
GND
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
15. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05289 Rev. *E
Page 20 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
[16, 17]
Switching Characteristics Over the Operating Range
-250
-200
Max.
-167
Parameter
Description
Min.
Max.
Min.
Min.
Max. Unit
[18]
tPower
VCC (typical) to the First Access Read or Write
1
1
1
ms
Clock
tCYC
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
4.0
5.0
6.0
ns
FMAX
tCH
250
200
167
MHz
ns
2.0
2.0
2.0
2.0
2.2
2.2
tCL
Clock LOW
ns
Output Times
tCO
Data Output Valid After CLK Rise
OE LOW to Output Valid
3.0
3.0
3.0
3.0
3.4
3.4
ns
ns
ns
ns
ns
ns
ns
tOEV
tDOH
Data Output Hold After CLK Rise
Clock to High-Z[19, 20, 21]
Clock to Low-Z[19, 20, 21]
OE HIGH to Output High-Z[19, 20, 21]
OE LOW to Output Low-Z[19, 20, 21]
1.3
1.3
0
1.3
1.3
0
1.5
1.5
0
tCHZ
3.0
3.0
3.0
3.0
3.4
3.4
tCLZ
tEOHZ
tEOLZ
Set-up Times
tAS
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
CEN Set-up Before CLK Rise
WE, BWx Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tDS
tCENS
tWES
tALS
tCES
Hold Times
tAH
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
WE, BWx Hold After CLK Rise
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
tALH
tCEH
Shaded areas contain advance information.
Notes:
16. Timing reference is 1.5V when V
3.3V and is 1.25V when V
2.5V.
DDQ=
DDQ=
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18. This part has a voltage regulator internally; t
is the time power needs to be supplied above V minimum initially, before a Read or Write operation can be
power
DD
initiated.
19. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
EOHZ
CHZ CLZ EOLZ
20. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
EOHZ
EOLZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document #: 38-05289 Rev. *E
Page 21 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Switching Waveforms
Read/Write/Timing[22, 23, 24]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
x
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
22. For this waveform ZZ is tied LOW.
23. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
24. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1= Interleaved). Burst operations are optional.
Document #: 38-05289 Rev. *E
Page 22 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Switching Waveforms (continued)
NOP, STALL and DESELECT Cycles[22, 23, 25]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
ZZ Mode Timing[26, 27]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
25. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A Write is not performed during this cycle
26. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
27. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05289 Rev. *E
Page 23 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
250
CY7C1470V33-250AXC
CY7C1472V33-250AXC
CY7C1470V33-250BZC
CY7C1472V33-250BZC
CY7C1474V33-250BGC
CY7C1470V33-250BZXC
CY7C1472V33-250BZXC
CY7C1474V33-250BGXC
CY7C1470V33-200AXC
CY7C1472V33-200AXC
CY7C1470V33-200BZC
CY7C1472V33-200BZC
CY7C1474V33-200BGC
CY7C1470V33-200BZXC
CY7C1472V33-200BZXC
CY7C1474V33-200BGXC
CY7C1470V33-167AXC
CY7C1472V33-167AXC
CY7C1470V33-167BZC
CY7C1472V33-167BZC
CY7C1474V33-167BGC
CY7C1470V33-167BZXC
CY7C1472V33-167BZXC
CY7C1474V33-167BGXC
CY7C1470V33-167AXI
CY7C1472V33-167AXI
CY7C1470V33-167BZI
CY7C1472V33-167BZI
CY7C1474V33-167BGI
CY7C1470V33-167BZXI
CY7C1472V33-167BZXI
CY7C1474V33-167BGXI
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
Commercial
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
BB165C Lead-Free 165-ball Fine Pitch Ball Grid Array
(15 x 17 x 1.4 mm)
BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
200
167
167
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
BB165C Lead-Free 165-ball Fine Pitch Ball Grid Array
(15 x 17 x 1.4 mm)
BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
BB165C Lead-Free 165-ball Fine Pitch Ball Grid Array
(15 x 17 x 1.4 mm)
BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
Industrial
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
BB165C Lead-Free 165-ball Fine Pitch Ball Grid Array
(15 x 17 x 1.4 mm)
BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
Shaded area contains advance information
Please contact your local Cypress sales representative for availability of these parts.
Lead-free BG packages (Ordering Code: BGX) will be available in 2005.
Document #: 38-05289 Rev. *E
Page 24 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05289 Rev. *E
Page 25 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Package Diagrams (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) BB209A
51-85167-**
Document #: 38-05289 Rev. *E
Page 26 of 28
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Package Diagrams (continued)
165-Ball FBGA (15 x 17 x 1.40 mm) BB165C
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45 0.05ꢀ1ꢁ5ꢂX
1
2
3
4
5
ꢁ
7
8
9
10
11
11 10
9
8
7
ꢁ
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15ꢀ4ꢂX
SEATING PLANE
C
51-85165-*A
ZBT is a trademark of Integrated Device Technology. No Bus Latency and NoBL are trademarks of Cypress Semiconductor
Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05289 Rev. *E
Page 27 of 28
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Cypressproductsarenotwarrantednorintendedtobeusedformedical, life-support, life-saving, criticalcontrolorsafetyapplications, unlesspursuanttoanexpresswrittenagreementwithCypress.
CY7C1470V33
CY7C1472V33
CY7C1474V33
PRELIMINARY
Document History Page
Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with
NoBL™ Architecture
Document Number: 38-05289
Orig. of
REV.
**
ECN No. Issue Date Change
Description of Change
114676
121520
08/06/02
01/27/03
PKS
CJM
New Data Sheet
*A
Updated features for package offering
Removed 300-MHz offering
Changed tCO, tEOV, tCHZ, tEOHZ from 2.4 ns to 2.6 ns (250 MHz),
tDOH, tCLZ from 0.8 ns to 1.0 ns (250 MHz), tDOH, tCLZ from 1.0 ns
to 1.3 ns (200 MHz)
Updated ordering information
Changed Advanced Information to Preliminary
*B
223721
See ECN
NJY
Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Included IDD and ISB values
Removed 250-MHz offering and included 225-MHz speed bin
Changed package outline for 165FBGA package and 209-ball BGA package
Removed 119-BGA package offering
*C
*D
235012
243572
See ECN
See ECN
RYQ
NJY
Minor Change: The data sheets do not match on the spec system and
external web.
Changed ball C11,D11,E11,F11,G11 from DQPb,DQb,DQb,DQb,DQb to
DQPa,DQa,DQa,DQa,DQa in page 4
Modified capacitance values in page 20
*E
299511
See ECN
SYT
Removed 225-MHz offering and included 250-MHz speed bin
Changed tCYC from 4.4 ns to 4.0 ns for 250-MHz Speed Bin
Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for
100 TQFP Package on Page # 20
Added lead-free information for 100-Pin TQFP and 165 FBGA Packages
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
VBL
Add Industrial part numbers in Ordering Info section.
Document #: 38-05289 Rev. *E
Page 28 of 28
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