CY7C1473BV25-100BZI [CYPRESS]
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture; 72兆位（ 2M ×36 / 4M ×18 / 1M X 72 ）流通型SRAM与NoBL⑩架构
| 型号： | CY7C1473BV25-100BZI |
| 厂家： | 
CYPRESS |
| 描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture |
| 文件： | 总30页 (文件大小：848K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
■ No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous flow through
burst SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471BV25, CY7C1473BV25, and
CY7C1475BV25 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive read or
write operations with data transferred on every clock cycle. This
feature dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent write-read
transitions.
■ Supports up to 133 MHz bus operations with zero wait states
■ Data transfers on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte Write capability
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
■ 2.5V IO supply (VDDQ
)
■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
Write operations are controlled by two or four Byte Write Select
(BWX) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
■ Clock Enable (CEN) pin to enable clock and suspend operation
■ Synchronous self timed writes
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. To avoid bus contention, the output
drivers are synchronously tri-stated during the data portion of a
write sequence.
■ Asynchronous Output Enable (OE)
■ CY7C1471BV25, CY7C1473BV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1475BV25
available in Pb-free and non-Pb-free 209-ball FBGA package.
For best practice recommendations, refer to the Cypress appli-
cation note AN1064, SRAM System Guidelines.
■ Three Chip Enables (CE1, CE2, CE3) for simple depth
expansion.
■ Automatic power down feature available using ZZ mode or CE
deselect.
■ IEEE 1149.1 JTAG Boundary Scan compatible
■ Burst Capability - linear or interleaved burst order
■ Low standby power
Selection Guide
Description
Maximum Access Time
133 MHz
6.5
100 MHz
8.5
Unit
ns
Maximum Operating Current
305
275
mA
mA
Maximum CMOS Standby Current
120
120
Cypress Semiconductor Corporation
Document #: 001-15013 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 29, 2008
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Logic Block Diagram – CY7C1471BV25 (2M x 36)
ADDRESS
REGISTER
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
MODE
C
BURST
LOGIC
CE
ADV/LD
CLK
CEN
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
E
ADV/LD
A
B
U
F
F
E
R
S
MEMORY
ARRAY
BW
BW
BW
BW
A
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
B
A
B
A
M
P
C
D
C
D
S
WE
E
N
G
INPUT
REGISTER
E
OE
CE1
CE2
CE3
READ LOGIC
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1473BV25 (4M x 18)
ADDRESS
REGISTER
A0, A1,
A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
MODE
BURST
LOGIC
CE
ADV/LD
CLK
EN
C
C
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
A
S
E
N
S
E
ADV/LD
B
U
F
MEMORY
ARRAY
BWA
BWB
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
A
A
M
P
F
DQPB
E
R
S
S
WE
E
N
G
INPUT
REGISTER
E
OE
CE1
CE2
CE3
READ LOGIC
SLEEP
CONTROL
ZZ
Document #: 001-15013 Rev. *E
Page 2 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Logic Block Diagram – CY7C1475BV25 (1M x 72)
ADDRESS
REGISTER
A0, A1,
A
0
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
CLK
CEN
C
WRITE ADDRESS
REGISTER 2
WRITE ADDRESS
REGISTER
1
O
U
T
O
U
T
P
U
T
S
E
N
S
E
P
U
T
D
A
T
A
ADV/LD
BW
BW
BW
BW
BW
BW
BW
a
R
E
G
I
MEMORY
ARRAY
B
U
F
DQ s
WRITE
DRIVERS
b
c
S
T
E
E
R
I
A
M
P
DQ Pa
DQ Pb
DQ Pc
DQ Pd
DQ Pe
DQ Pf
DQ Pg
DQ Ph
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
F
S
T
E
R
S
d
e
E
R
S
S
f
N
G
g
E
E
BW
h
WE
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
CE1
CE2
CE3
READ LOGIC
Sleep Control
ZZ
Document #: 001-15013 Rev. *E
Page 3 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Pin Configurations
Figure 1. 100- Pin TQFP Pinout
DQPC
DQC
DQC
VDDQ
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
DQPB
DQB
DQB
VDDQ
VSS
2
3
4
5
DQC
6
DQB
DQB
DQB
DQB
VSS
BYTE C
BYTE B
DQC
DQC
DQC
VSS
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQC
DQC
NC
VDDQ
DQB
DQB
VSS
CY7C1471BV25
VDD
NC
NC
VDD
ZZ
VSS
DQD
DQD
VDDQ
VSS
DQA
DQA
VDDQ
VSS
DQD
DQA
DQA
DQA
DQA
VSS
DQD
BYTE D
BYTE A
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
VDDQ
DQA
DQA
DQPA
Document #: 001-15013 Rev. *E
Page 4 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Pin Configurations (continued)
Figure 2. 100-Pin TQFP Pinout
NC
1
NC
2
NC
3
VDDQ
4
VSS
5
NC
6
NC
7
DQB
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
DQB
9
VSS
VDDQ
DQB
DQB
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
BYTE A
VDD
NC
CY7C1473BV25
BYTE B
VDD
ZZ
VSS
DQB
DQB
VDDQ
VSS
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
DQB
DQB
DQPB
NC
NC
VSS
VSS
VDDQ
NC
VDDQ
NC
NC
NC
NC
NC
Document #: 001-15013 Rev. *E
Page 5 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1471BV25 (2M x 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE3
7
CEN
8
9
A
10
A
11
NC
NC/576M
NC/1G
DQPC
DQC
ADV/LD
A
B
C
D
CE2
VDDQ
VDDQ
CLK
VSS
VSS
A
A
NC
A
BWD
VSS
BWA
VSS
VSS
WE
VSS
VSS
OE
VSS
VDD
NC
DQC
VDDQ
VDDQ
NC
DQPB
DQB
VDD
DQB
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
DQD
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
M
N
P
NC/144M
TDI
TDO
NC/288M
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
CY7C1473BV25 (4M x 18)
1
NC/576M
NC/1G
NC
2
A
3
CE1
4
BWB
5
NC
6
CE3
7
CEN
8
9
A
10
A
11
A
ADV/LD
A
B
C
D
A
CE2
VDDQ
VDDQ
NC
VSS
VDD
CLK
VSS
VSS
A
A
NC
BWA
VSS
VSS
WE
VSS
VSS
OE
VSS
VDD
NC
DQB
VDDQ
VDDQ
NC
NC
DQPA
DQA
NC
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
M
N
P
NC/144M
TDI
TDO
NC/288M
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
Document #: 001-15013 Rev. *E
Page 6 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Pin Configurations (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1475BV25 (1M × 72)
1
2
3
4
5
6
7
8
9
10
11
DQb
DQb
DQb
DQb
DQg
DQg
DQg
DQg
A
CE2
A
ADV/LD
WE
A
A
CE3
A
DQb
DQb
A
B
BWSc
BWSg
NC
BWSb
BWSf
DQg
DQg
BWSh
VSS
BWSd NC/576M CE1
NC
BWSe
NC
BWSa
VSS
DQb
DQb
C
DQg
DQPg
DQc
DQg
DQPc
DQc
NC
NC/1G
VDD
VSS
OE
VDD
NC
NC
VDD
VSS
VDD
D
E
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
DQPf
DQf
DQPb
DQf
F
VSS
VDDQ
VSS
VSS
VDDQ
VSS
G
H
J
DQc
DQc
DQc
VDD
VSS
NC
VDDQ
VSS
DQf
DQf
DQf
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
DQc
DQc
NC
NC
DQf
DQf
NC
VDDQ
DQc
NC
VDD
VSS
VDDQ
VDDQ
CLK
VDDQ
NC
NC
DQf
NC
K
L
CEN
NC
NC
NC
DQh
DQh
DQh
VDDQ
VSS
VDDQ
VSS
VDD
VDDQ
VDDQ
VSS
VDDQ
VSS
DQa
DQa
DQa
M
N
P
R
T
NC
VSS
VDDQ
VSS
VDDQ
NC
DQh
DQh
DQh
VSS
VDD
VSS
DQa
DQa
DQa
VDDQ
DQh
DQh
DQPd
DQd
DQd
VDDQ
VSS
NC
ZZ
DQa
DQa
DQPa
DQe
DQe
VSS
VDDQ
VDDQ
VDD
NC
A
DQPh
DQd
DQd
DQd
DQd
VDDQ
VDD
DQPe
DQe
DQe
DQe
DQe
VSS
VSS
NC
A
MODE
A
U
V
W
A
NC/288M
NC/144M
A
A
A1
A
DQd
DQd
A
A
A
A
DQe
DQe
TDI
TDO
TCK
A0
A
TMS
Document #: 001-15013 Rev. *E
Page 7 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Table 1. Pin Definitions
Name
IO
Description
A0, A1, A
Input-
Synchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge
of the CLK. A[1:0] are fed to the two-bit burst counter.
BWA, BWB,
BWC, BWD,
BWE, BWF,
BWG, BWH
Input-
Synchronous
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.
WE
Input-
Synchronous
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD must
be driven LOW to load a new address.
CLK
CE1
CE2
CE3
OE
Input-
Clock
Clock Input. Captures all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
Input-
Synchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select or deselect the device.
Input-
Synchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select or deselect the device.
Input-
Synchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select or deselect the device.
Input-
Asynchronous
Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic
block inside the device to control the direction of the IO pins. When LOW, the IO pins are enabled
to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins.
OE is masked during the data portion of a write sequence, during the first clock when emerging
from a deselected state, when the device has been deselected.
CEN
ZZ
Input-
Synchronous
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does
not deselect the device, CEN can be used to extend the previous cycle when required.
Input-
Asynchronous
ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep”
condition with data integrity preserved. For normal operation, this pin must be LOW or left
floating. ZZ pin has an internal pull down.
IO-
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically
tri-stated during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected, regardless of the state of OE.
DQs
Synchronous
IO-
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During
write sequences, DQPX is controlled by BWX correspondingly.
DQPX
Synchronous
MODE
Input Strap Pin
Mode Input. Selects the Burst Order of the Device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects inter-
leaved burst sequence.
VDD
Power Supply
Power Supply Inputs to the Core of the Device.
VDDQ
VSS
IO Power Supply Power Supply for the IO Circuitry.
Ground Ground for the Device.
JTAG serial output Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG
TDO
Synchronous
feature is not used, this pin must be left unconnected. This pin is not available on TQFP
packages.
Document #: 001-15013 Rev. *E
Page 8 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Table 1. Pin Definitions (continued)
Name IO
Description
TDI
JTAG serial input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is
Synchronous
not used, leave this pin floating or connected to VDD through a pull up resistor. This pin is not
available on TQFP packages.
TMS
JTAG serial input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is
Synchronous
JTAG-Clock
-
not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP
packages.
TCK
NC
Clock Input to the JTAG Circuitry. If the JTAG feature is not used, connect this pin to VSS.
This pin is not available on TQFP packages.
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
deselected at clock rise by one of the chip enable signals, the
output is tri-stated immediately.
Functional Overview
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
are synchronous flow through burst SRAMs designed specifi-
cally to eliminate wait states during write read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
Clock Enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133-MHz
device).
Burst Read Accesses
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
has an on-chip burst counter that enables the user the ability to
supply a single address and conduct up to four reads without
reasserting the address inputs. ADV/LD must be driven LOW to
load a new address into the SRAM, as described in the Single
Read Access section. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD increments the internal burst counter
regardless of the state of chip enable inputs or WE. WE is latched
at the beginning of a burst cycle. Therefore, the type of access
(read or write) is maintained throughout the burst sequence.
Accesses are initiated by asserting all three Chip Enables (CE1,
CE2, CE3) active at the rising edge of the clock. If CEN is active
LOW and ADV/LD is asserted LOW, the address presented to
the device is latched. The access is either a read or write
operation, depending on the status of the Write Enable (WE).
Use Byte Write Select (BWX) to conduct Byte Write operations.
Write operations are qualified by the WE. All writes are simplified
with on-chip synchronous self- timed write circuitry.
Single Write Accesses
Write accesses are initiated when these conditions are satisfied
at clock rise:
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
■ CEN is asserted LOW
■ CE1, CE2, and CE3 are ALL asserted active
■ WE is asserted LOW.
Single Read Accesses
The address presented to the address bus is loaded into the
Address Register. The write signals are latched into the Control
Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQPX.
A read access is initiated when the following conditions are
satisfied at clock rise:
■ CEN is asserted LOW
■ CE1, CE2, and CE3 are ALL asserted active
■ WE is deasserted HIGH
On the next clock rise the data presented to DQs and DQPX (or
a subset for Byte Write operations, see “Truth Table for
Read/Write” on page 12 for details) inputs is latched into the
device and the write is complete. Additional accesses
(read/write/deselect) can be initiated on this cycle.
■ ADV/LD is asserted LOW.
The address presented to the address inputs is latched into the
Address Register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW to drive out the
requested data. On the subsequent clock, another operation
(read/write/deselect) can be initiated. When the SRAM is
The data written during the write operation is controlled by BWX
signals.
The
CY7C1471BV25,
CY7C1473BV25, and
CY7C1475BV25 provide Byte Write capability that is described
in the “Truth Table for Read/Write” on page 12. The input WE
with the selected BWx input selectively writes to only the desired
bytes. Bytes not selected during a Byte Write operation remain
unaltered. A synchronous self timed write mechanism is
provided to simplify the write operations. Byte Write capability is
Document #: 001-15013 Rev. *E
Page 9 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
included to greatly simplify read/modify/write sequences, which
can be reduced to simple byte write operations.
Table 2. Interleaved Burst Address Table
(MODE = Floating or VDD
)
Because the CY7C1471BV25, CY7C1473BV25, and
CY7C1475BV25 are common IO devices, data must not be
driven into the device while the outputs are active. The OE can
be deasserted HIGH before presenting data to the DQs and
DQPX inputs. This tri-states the output drivers. As a safety
precaution, DQs and DQPX are automatically tri-stated during
the data portion of a write cycle, regardless of the state of OE.
First
Second
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Burst Write Accesses
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
have an on-chip burst counter that makes it possible to supply a
single address and conduct up to four Write operations without
reasserting the address inputs. Drive ADV/LD LOW to load the
initial address, as described in the Single Write Access section.
When ADV/LD is driven HIGH on the subsequent clock rise, the
Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored
and the burst counter is incremented. You must drive the correct
BWX inputs in each cycle of the Burst Write to write the correct
data bytes.
Table 3. Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. You must
select the device before entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
Min
Max
Unit
mA
ns
120
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
0
ns
Document #: 001-15013 Rev. *E
Page 10 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Table 4. Truth Table
The truth table for CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 follows.[1, 2, 3, 4, 5, 6, 7]
Address
Operation
Deselect Cycle
CE1 CE2
ZZ ADV/LD
WE
BWX
OE
CEN CLK
DQ
CE3
Used
None
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
H
L
X
X
X
X
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L->H
L->H
L->H
L->H
Tri-State
Tri-State
Tri-State
Tri-State
Deselect Cycle
None
Deselect Cycle
None
Continue Deselect Cycle
None
X
H
Read Cycle
External
L->H Data Out (Q)
(Begin Burst)
Read Cycle
(Continue Burst)
Next
External
Next
X
L
X
H
X
H
X
H
X
X
L
L
L
L
L
L
L
L
H
L
X
H
X
L
X
X
X
L
L
H
H
X
X
X
X
L
L
L
L
L
L
L
L->H Data Out (Q)
NOP/Dummy Read
(Begin Burst)
L->H
L->H
Tri-State
Tri-State
Dummy Read
(Continue Burst)
X
L
X
L
H
L
Write Cycle
(Begin Burst)
External
Next
L->H Data In (D)
L->H Data In (D)
Write Cycle
(Continue Burst)
X
L
X
L
H
L
X
L
L
NOP/Write Abort
(Begin Burst)
None
H
H
L->H
L->H
Tri-State
Tri-State
Write Abort
Next
X
X
H
X
(Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Current
None
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
H
X
L->H
X
-
H
Tri-State
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW = L signifies at least one Byte Write Select is active, BW = Valid signifies that the desired Byte Write Selects
X
X
are asserted, see “Truth Table for Read/Write” on page 12 for details.
2. Write is defined by BW , and WE. See “Truth Table for Read/Write” on page 12.
X
3. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
4. The DQs and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
X
5. CEN = H, inserts wait states.
6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = tri-state when OE is inactive
X
or when the device is deselected, and DQs and DQP = data when OE is active.
X
Document #: 001-15013 Rev. *E
Page 11 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Table 5. Truth Table for Read/Write
The read-write truth table for CY7C1471BV25 follows.[1, 2, 8]
Function
WE
H
L
BWA
X
BWB
X
BWC
X
BWD
X
Read
Write No bytes written
H
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Byte C – (DQC and DQPC)
Write Byte D – (DQD and DQPD)
Write All Bytes
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
Table 6. Truth Table for Read/Write
The read-write truth table for CY7C1473BV25 follows.[1, 2, 8]
Function
WE
BWb
X
BWa
Read
H
L
L
L
L
X
H
L
Write – No Bytes Written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
H
H
L
H
L
L
Table 7. Truth Table for Read/Write
The read-write truth table for CY7C1475BV25 follows.[1, 2, 8]
Function
WE
H
BWx
Read
X
Write – No Bytes Written
Write Byte X − (DQx and DQPx)
Write All Bytes
L
H
L
L
L
All BW = L
Note
8. This table is only a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write is based on which byte write is active.
X
Document #: 001-15013 Rev. *E
Page 12 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Test Access Port (TAP)
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Clock (TCK)
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
incorporate a serial boundary scan Test Access Port (TAP). This
port operates in accordance with IEEE Standard 1149.1-1990
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V IO logic levels.
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up inter-
nally, resulting in a logic HIGH level.
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
contain a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Test Data In (TDI)
The TDI ball serially inputs information into the registers and is
connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information about loading
the instruction register, see the TAP Controller State Diagram.
TDI is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant
bit (MSB) of any register. (See TAP Controller Block Diagram.)
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent clocking of the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be connected
to VDD through a pull up resistor. TDO must be left unconnected.
During power up, the device comes up in a reset state, which
does not interfere with the operation of the device.
Test Data Out (TDO)
The TDO output ball serially clocks data out from the registers.
The output is active depending upon the current state of the TAP
state machine. The output changes on the falling edge of TCK.
TDO is connected to the least significant bit (LSB) of any register.
(See Tap Controller State Diagram.)
Figure 3. TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
Figure 4. TAP Controller Block Diagram
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
0
Bypass Register
SHIFT-DR
0
SHIFT-IR
0
2
1
0
0
0
1
1
Selection
Circuitry
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
TDI
TDO
1
1
EXIT1-DR
EXIT1-IR
.
.
. 2 1
0
0
PAUSE-DR
0
PAUSE-IR
1
0
x
.
.
.
.
. 2 1
1
Boundary Scan Register
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
TCK
1
0
1
0
TAP CONTROLLER
TM S
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
During power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
Document #: 001-15013 Rev. *E
Page 13 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable the scanning of data into and out of the SRAM test
circuitry. Only one register is selectable at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
You cannot use the TAP controller to load address data or control
signals into the SRAM and you cannot preload the IO buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the IO ring when these instruc-
tions are executed.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the “TAP Controller Block Diagram”
on page 13. During power up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
EXTEST
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.
EXTEST is a mandatory 1149.1 instruction which is executed
whenever the instruction register is loaded with all 0s. EXTEST
is not implemented in this SRAM TAP controller making this
device not compliant with 1149.1. The TAP controller does
recognize an all-0 instruction.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts the data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction is loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
Boundary Scan Register
IDCODE
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The IDCODE instruction causes a vendor specific, 32-bit code to
load into the instruction register. It also places the instruction
register between the TDI and TDO balls and enables the
IDCODE for shifting out of the device when the TAP controller
enters the Shift-DR state.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the IO ring.
The IDCODE instruction is loaded into the instruction register
during power up or whenever the TAP controller is in a test logic
reset state.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High-Z
state.
Identification (ID) Register
The ID register is loaded with a vendor specific, 32-bit code
during the Capture DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift DR state. The ID register has a vendor code and other
information described in “Identification Register Definitions” on
page 17.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
TAP Instruction Set
Overview
Be aware that the TAP controller clock only operates at a
frequency up to 20 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that, during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Identification
Codes” on page 17. Three of these instructions are listed as
RESERVED and are not for use. The other five instructions are
described in this section in detail.
Document #: 001-15013 Rev. *E
Page 14 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
no guarantee as to the value that is captured. Repeatable results
may not be possible.
Note that since the PRELOAD part of the command is not imple-
mented, putting the TAP to the Update-DR state while performing
a SAMPLE/PRELOAD instruction has the same effect as the
Pause-DR command.
To guarantee that the boundary scan register captures the
correct signal value, make certain that the SRAM signal is stabi-
lized long enough to meet the TAP controller’s capture setup plus
hold time (tCS plus tCH).
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
Reserved
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Figure 5. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TM SS
TDIS
TM SH
Test M ode Select
(TM S)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document #: 001-15013 Rev. *E
Page 15 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
TAP AC Switching Characteristics
Over the Operating Range[9, 10]
Parameter
Clock
tTCYC
tTF
Description
Min
Max
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH Time
TCK Clock LOW Time
50
ns
MHz
ns
20
tTH
20
20
tTL
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
10
ns
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
Setup Times
tTMSS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Figure 6. 2.5V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
1.25V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.375 to 2.625 unless otherwise noted) [11]
Parameter
VOH1
Description
Test Conditions
Min
2.0
2.1
Max
Unit
V
Output HIGH Voltage IOH = –1.0 mA, VDDQ = 2.5V
Output HIGH Voltage IOH = –100 µA, VDDQ = 2.5V
VOH2
VOL1
VOL2
VIH
V
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOL = 1.0 mA, VDDQ = 2.5V
IOL = 100 µA, VDDQ = 2.5V
VDDQ = 2.5V
0.4
0.2
V
V
1.7
–0.3
–5
VDD + 0.3
V
VIL
VDDQ = 2.5V
0.7
5
V
IX
GND < VIN < VDDQ
µA
Notes
9.t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
10.Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
11.All voltages refer to V (GND).
SS
Document #: 001-15013 Rev. *E
Page 16 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Table 8. Identification Register Definitions
Instruction Field
CY7C1471BV25 CY7C1473BV25 CY7C1475BV25
Description
(2MX36)
(4MX18)
(1MX72)
Revision Number (31:29)
Device Depth (28:24)
000
000
000
Describes the version number
Reserved for internal use
01011
001001
01011
01011
001001
110100
Architecture/Memory Type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
001001
Defines memory type and architecture
Defines width and density
100100
010100
00000110100
00000110100
00000110100 Allows unique identification of SRAM
vendor
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID register
Table 9. Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
Instruction
3
1
3
1
3
1
Bypass
ID
32
71
-
32
52
-
32
-
Boundary Scan Order – 165FBGA
Boundary Scan Order – 209BGA
110
Table 10. Identification Codes
Instruction
Code
Description
EXTEST
000
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Document #: 001-15013 Rev. *E
Page 17 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Table 11. Boundary Scan Exit Order (2M x 36)
Bit #
1
165-Ball ID
C1
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
165-Ball ID
R3
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
165-Ball ID
J11
Bit #
61
62
63
64
65
66
67
68
69
70
71
165-Ball ID
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
2
D1
P2
K10
J10
3
E1
R4
4
D2
P6
H11
G11
F11
E11
D10
D11
C11
G10
F10
E10
A9
5
E2
R6
6
F1
R8
7
G1
F2
P3
8
P4
9
G2
J1
P8
10
11
12
13
14
15
16
17
18
19
20
P9
K1
P10
R9
L1
J2
R10
R11
N11
M11
L11
M10
L10
K11
M1
N1
B9
K2
A10
B10
A8
L2
M2
R1
B8
R2
A7
Table 12. Boundary Scan Exit Order (4M x 18)
Bit #
1
165-Ball ID
Bit #
14
15
16
17
18
19
20
21
22
23
24
25
26
165-Ball ID
R4
Bit #
27
28
29
30
31
32
33
34
35
36
37
38
39
165-Ball ID
L10
Bit #
40
41
42
43
44
45
46
47
48
49
50
51
52
165-Ball ID
B10
A8
D2
E2
F2
G2
J1
2
P6
K10
J10
3
R6
B8
4
R8
H11
G11
F11
A7
5
P3
B7
6
K1
L1
P4
B6
7
P8
E11
A6
8
M1
N1
R1
R2
R3
P2
P9
D11
C11
A11
B5
9
P10
R9
A4
10
11
12
13
B3
R10
R11
M10
A9
A3
B9
A2
A10
B2
Document #: 001-15013 Rev. *E
Page 18 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Table 13. Boundary Scan Exit Order (1M x 72)
Bit #
1
209-Ball ID
A1
Bit #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
209-Ball ID
T1
Bit #
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
209-Ball ID
U10
T11
Bit #
85
209-Ball ID
B11
B10
A11
A10
A7
2
A2
T2
86
3
B1
U1
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
87
4
B2
U2
88
5
C1
C2
D1
D2
E1
V1
89
6
V2
90
A5
7
W1
W2
T6
91
A9
8
92
U8
9
93
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
E2
V3
94
D6
F1
V4
95
K6
F2
U4
96
B6
G1
G2
H1
H2
J1
W5
V6
L10
97
K3
P6
98
A8
W6
V5
J11
99
B4
J10
100
101
102
103
104
105
106
107
108
109
110
B3
U5
H11
H10
G11
G10
F11
C3
J2
U6
C4
L1
W7
V7
C8
L2
C9
M1
M2
N1
N2
P1
U7
B9
V8
F10
E10
E11
D11
D10
C11
C10
B8
V9
A4
W11
W10
V11
V10
U11
C6
B7
P2
A3
R2
R1
Document #: 001-15013 Rev. *E
Page 19 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........–0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
Ambient
Range
VDD
VDDQ
Temperature
0°C to +70°C
–40°C to +85°C
Commercial
Industrial
2.5V –5%/+5% 2.5V–5% to
VDD
DC Voltage Applied to Outputs
in Tri-State ...........................................–0.5V to VDDQ + 0.5V
Electrical Characteristics
Over the Operating Range [12, 13]
Parameter
VDD
Description
Test Conditions
Min
2.375
2.375
2.0
Max
2.625
VDD
Unit
V
Power Supply Voltage
IO Supply Voltage
VDDQ
VOH
For 2.5V IO
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[12]
Input LOW Voltage[12]
For 2.5V IO, IOH = –1.0 mA
For 2.5V IO, IOL= 1.0 mA
For 2.5V IO
V
VOL
0.4
V
VIH
1.7
–0.3
–5
VDD + 0.3V
V
VIL
For 2.5V IO
0.7
5
V
IX
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
μA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
μA
μA
5
Input Current of ZZ
Input = VSS
Input = VDD
μA
30
5
μA
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
μA
[14]
IDD
VDD Operating Supply
Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
6.5 ns cycle, 133 MHz
8.5 ns cycle, 100 MHz
6.5 ns cycle, 133 MHz
8.5 ns cycle, 100 MHz
305
275
170
170
mA
mA
mA
mA
ISB1
ISB2
ISB3
ISB4
Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX, inputs switching
Automatic CE
Power Down
Current—CMOS Inputs f = 0, inputs static
VDD = Max, Device Deselected,
VIN ≤ 0.3V or VIN > VDD – 0.3V,
All speeds
120
mA
Automatic CE
Power Down
Current—CMOS Inputs f = fMAX, inputs switching
VDD = Max, Device Deselected, or 6.5 ns cycle, 133 MHz
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
170
170
mA
mA
8.5 ns cycle, 100 MHz
Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
All Speeds
135
mA
Notes
12. Overshoot: V (AC) < V +1.5V (pulse width less than t
/2). Undershoot: V (AC) > –2V (pulse width less than t
/2).
CYC
IH
DD
CYC
IL
13. T
: assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
14. The operation current is calculated with 50% read cycle and 50% write cycle.
Document #: 001-15013 Rev. *E
Page 20 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Capacitance
Tested initially and after any design or process change that may affect these parameters.
100 TQFP 165 FBGA 209 FBGA
Parameter
CADDRESS
Description
Test Conditions
Unit
Max
Max
Max
Address Input Capacitance
Data Input Capacitance
Control Input Capacitance
Clock Input Capacitance
Input-Output Capacitance
TA = 25°C, f = 1 MHz,
DD = 2.5V
DDQ = 2.5V
6
5
8
6
5
6
5
8
6
5
6
5
8
6
5
pF
pF
pF
pF
pF
V
V
CDATA
CCTRL
CCLK
CIO
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
100 TQFP 165 FBGA 209 FBGA
Parameter
Description
Test Conditions
Unit
Package
Package
Package
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow
24.63
16.3
15.2
°C/W
standard test methods and
procedures for measuring
thermal impedance,
ΘJC
Thermal Resistance
(Junction to Case)
2.28
2.1
1.7
°C/W
according to EIA/JESD51.
Figure 7. AC Test Loads and Waveforms
2.5V IO Test Load
R = 1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document #: 001-15013 Rev. *E
Page 21 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Switching Characteristics
Over the Operating Range. Timing reference level is 1.25V when VDDQ = 2.5V. Test conditions shown in (a) of “AC Test Loads and
Waveforms” on page 21 unless otherwise noted.
133 MHz
100 MHz
Parameter
Description
Unit
Min
Max
Min
Max
tPOWER
Clock
tCYC
tCH
1
1
ms
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
10
3.0
3.0
ns
ns
ns
tCL
Clock LOW
Output Times
tCDV
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z [16, 17, 18]
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
tDOH
2.5
3.0
2.5
3.0
tCLZ
tCHZ
Clock to High-Z [16, 17, 18]
3.8
3.0
4.5
3.8
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to Output Low-Z [16, 17, 18]
OE HIGH to Output High-Z [16, 17, 18]
0
0
3.0
4.0
Address Setup Before CLK Rise
ADV/LD Setup Before CLK Rise
WE, BWX Setup Before CLK Rise
CEN Setup Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tALS
tWES
tCENS
tDS
Data Input Setup Before CLK Rise
Chip Enable Setup Before CLK Rise
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADV/LD Hold After CLK Rise
WE, BWX Hold After CLK Rise
CEN Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tALH
tWEH
tCENH
tDH
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes
15. This part has a voltage regulator internally; t
is the time that the power is supplied above V (minimum) initially, before a read or write operation can be initiated.
DD
POWER
16. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ±200 mV
CHZ CLZ OELZ
OEHZ
from steady-state voltage.
17. At any supplied voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
OEHZ
OELZ
CHZ
CLZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z before Low-Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document #: 001-15013 Rev. *E
Page 22 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Switching Waveforms
Figure 8 shows read-write timing waveform.[19, 20, 21]
Figure 8. Read/Write Timing
t
1
2
3
4
5
6
7
8
9
10
CYC
t
CLK
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CEN
CE
ADV/LD
W E
BW
X
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COM M AND
W RITE
D(A1)
W RITE
D(A2)
BURST
W RITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
W RITE
D(A5)
READ
Q(A6)
W RITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes
For this waveform ZZ is tied LOW.
19.
20. When CE is LOW, CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH, CE is HIGH, CE is LOW or CE is HIGH.
1
2
3
1
2
3
21. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 001-15013 Rev. *E
Page 23 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Switching Waveforms (continued)
Figure 9 shows NOP, STALL and DESELECT Cycles waveform.[19, 20, 22]
Figure 9. NOP, STALL and DESELECT Cycles
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A1
A2
A3
A4
A5
t
CHZ
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
DQ
t
DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
Note
22. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document #: 001-15013 Rev. *E
Page 24 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Switching Waveforms (continued)
Figure 10 shows ZZ Mode timing waveform.[23, 24]
Figure 10. ZZ Mode Timing
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
23. Device must be deselected when entering ZZ mode. See “Truth Table” on page 11 for all possible signal conditions to deselect the device.
24. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 001-15013 Rev. *E
Page 25 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
133 CY7C1471BV25-133AXC
CY7C1473BV25-133AXC
CY7C1471BV25-133BZC
CY7C1473BV25-133BZC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1471BV25-133BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1473BV25-133BZXC
CY7C1475BV25-133BGC
CY7C1475BV25-133BGXC
CY7C1471BV25-133AXI
CY7C1473BV25-133AXI
CY7C1471BV25-133BZI
CY7C1473BV25-133BZI
CY7C1471BV25-133BZXI
CY7C1473BV25-133BZXI
CY7C1475BV25-133BGI
CY7C1475BV25-133BGXI
100 CY7C1471BV25-100AXC
CY7C1473BV25-100AXC
CY7C1471BV25-100BZC
CY7C1473BV25-100BZC
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1471BV25-100BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1473BV25-100BZXC
CY7C1475BV25-100BGC
CY7C1475BV25-100BGXC
CY7C1471BV25-100AXI
CY7C1473BV25-100AXI
CY7C1471BV25-100BZI
CY7C1473BV25-100BZI
CY7C1471BV25-100BZXI
CY7C1473BV25-100BZXI
CY7C1475BV25-100BGI
CY7C1475BV25-100BGXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
Document #: 001-15013 Rev. *E
Page 26 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Package Diagrams
Figure 11. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
1.00 REF.
51-85050-*B
DETAIL
A
Document #: 001-15013 Rev. *E
Page 27 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Package Diagrams (continued)
Figure 12. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45 0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15(4X)
SEATING PLANE
C
51-85165-*A
Document #: 001-15013 Rev. *E
Page 28 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Package Diagrams (continued)
Figure 13. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167
51-85167-**
Document #: 001-15013 Rev. *E
Page 29 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Document History Page
Document Title: CY7C1471BV25/CY7C1473BV25/CY7C1475BV25, 72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-15013
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
1024500
1274731
1562503
1897447
2082487
2159486
See ECN VKN/KKVTMP New Data Sheet
*A
*B
*C
*D
*E
See ECN
See ECN
See ECN
See ECN
See ECN
VKN/AESA Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform
VKN/AESA Removed 1.8V IO offering from the data sheet
VKN/AESA Added footnote 14 related to IDD
VKN
Converted from preliminary to final
VKN/PYRS Minor Change-Moved to the external web
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15013 Rev. *E
Revised February 29, 2008
Page 30 of 30
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this
document may be the trademarks of their respective holders.
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