CY7C1481BV33-133AXI [CYPRESS]
Cache SRAM, 2MX36, 6.5ns, CMOS, PQFP100, TQFP-100;
| 型号： | CY7C1481BV33-133AXI |
| 厂家： | 
CYPRESS |
| 描述： | Cache SRAM, 2MX36, 6.5ns, CMOS, PQFP100, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总31页 (文件大小：711K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1481BV33
72-Mbit (2M × 36) Flow-Through SRAM
72-Mbit (2M
× 36) Flow-Through SRAM
Features
Functional Description
■ Supports 133 MHz bus operations
■ 2M × 36 common I/O
The CY7C1481BV33 is a 3.3 V, 2M × 36 synchronous flow
through SRAM designed to interface with high speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive edge triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address pipelining
Chip Enable (CE1), depth expansion Chip Enables (CE2 and
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write
■ 3.3 V core power supply (VDD
)
■ 2.5 V or 3.3 V I/O supply (VDDQ
)
■ Fast clock to output time
❐ 6.5 ns (133 MHz version)
■ Provide high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
Enables (BWx and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
■ Separate processor and controller address strobes
■ Synchronous self timed write
The CY7C1481BV33 enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs. Address advancement is controlled by the
Address Advancement (ADV) input.
■ Asynchronous output enable
■ CY7C1481BV33 available in JEDEC standard Pb-free 100-pin
TQFP, Pb-free and non Pb-free 165-ball FBGA package.
■ IEEE 1149.1 JTAG compatible boundary scan
■ ZZ sleep mode option
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller
(
) are active. Subsequent burst
ADSC
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1481BV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC standard JESD8-5 compatible.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum Access Time
133 MHz Unit
6.5
335
150
ns
Maximum Operating Current
mA
mA
Maximum CMOS Standby Current
Cypress Semiconductor Corporation
Document Number: 001-74857 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 2, 2018
CY7C1481BV33
Logic Block Diagram – CY7C1481BV33
ADDRESS
REGISTER
A0, A1,
A
A
[1:0]
MODE
ADV
CLK
Q1
Q0
BURST
COUNTER
AND LOGIC
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQP D
DQ
BYTE
WRITE REGISTER
D, DQP D
BW
D
DQ
BYTE
WRITE REGISTER
C, DQP C
DQ
BYTE
WRITE REGISTER
C, DQP C
BW
C
OUTPUT
BUFFERS
DQ s
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQP B
B
C
D
DQ
BYTE
WRITE REGISTER
B, DQP B
BW
B
DQ
BYTE
WRITE REGISTER
A, DQP A
DQ
A, DQPA
BW
A
BYTE
BWE
WRITE REGISTER
INPUT
GW
REGISTERS
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Document Number: 001-74857 Rev. *F
Page 2 of 31
CY7C1481BV33
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................6
Functional Overview ........................................................8
Single Read Accesses ................................................8
Single Write Accesses Initiated by ADSP ...................8
Single Write Accesses Initiated by ADSC ...................8
Burst Sequences .........................................................8
Sleep Mode .................................................................8
Interleaved Burst Address Table .................................8
Linear Burst Address Table .........................................8
ZZ Mode Electrical Characteristics ..............................9
Truth Table ........................................................................9
Truth Table for Read/Write ............................................10
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11
Disabling the JTAG Feature ......................................11
Test Access Port (TAP) .............................................11
PERFORMING A TAP RESET ..................................11
TAP REGISTERS ......................................................11
TAP Instruction Set ...................................................11
TAP Controller State Diagram .......................................13
TAP Controller Block Diagram ......................................14
TAP Timing ......................................................................15
TAP AC Switching Characteristics ...............................15
3.3 V TAP AC Test Conditions .......................................16
3.3 V TAP AC Output Load Equivalent .........................16
2.5 V TAP AC Test Conditions .......................................16
2.5 V TAP AC Output Load Equivalent .........................16
TAP DC Electrical Characteristics
and Operating Conditions .............................................16
Identification Register Definitions ................................17
Scan Register Sizes .......................................................17
Identification Codes .......................................................17
Boundary Scan Exit Order .............................................18
Maximum Ratings ...........................................................19
Operating Range .............................................................19
Electrical Characteristics ...............................................19
Capacitance ....................................................................20
Thermal Resistance ........................................................20
AC Test Loads and Waveforms .....................................20
Switching Characteristics ..............................................21
Timing Diagrams ............................................................22
Ordering Information ......................................................26
Ordering Code Definitions .........................................26
Package Diagrams ..........................................................27
Acronyms ........................................................................29
Document Conventions .................................................29
Units of Measure .......................................................29
Document History Page .................................................30
Sales, Solutions, and Legal Information ......................31
Worldwide Sales and Design Support .......................31
Products ....................................................................31
PSoC® Solutions ......................................................31
Cypress Developer Community .................................31
Technical Support .....................................................31
Document Number: 001-74857 Rev. *F
Page 3 of 31
CY7C1481BV33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
VSS
NC
VDD
ZZ
CY7C1481BV33
(2M × 36)
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
Document Number: 001-74857 Rev. *F
Page 4 of 31
CY7C1481BV33
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1481BV33 (2M × 36)
1
2
A
3
4
5
6
CE3
7
8
9
ADV
10
A
11
NC
NC/288M
NC/144M
DQPC
CE1
CE2
VDDQ
VDDQ
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
DQC
NC/1G
DQB
DQC
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
TDI
A1
TDO
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
Document Number: 001-74857 Rev. *F
Page 5 of 31
CY7C1481BV33
Pin Definitions
Pin Name
I/O
Description
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK
A0, A1, A
Input-
Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
BWA, BWB,
Input- Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
BWC, BWD Synchronous Sampled on the rising edge of CLK.
GW
CLK
CE1
Input-
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
Input-
Clock
Clock Input. Captures all synchronous inputs to the device. Also used to increment the burst counter
when ADV is asserted LOW during a burst operation.
Input-
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE to select or deselect the device. ADSP is ignored
CE is sampled only when a
if CE1 is HIGH.
3
1
new external address is loaded.
CE2
CE3
OE
Input-
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
Input- Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
Input- Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically
Synchronous increments the address in a burst cycle.
ADSP
Input-
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
Input-
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
.
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
BWE
ZZ
Input-
Input-
ZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a non time-critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ
pin has an internal pull down.
I/O-
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
DQs
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed
in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence,
the first clock when emerging from a deselected state, and when the device is deselected, regardless of
the state of OE.
I/O-
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
DQPX
Synchronous sequences, DQPx is controlled by BWX correspondingly.
MODE
Input-Static Selects Burst Order. When tied to GND, selects linear burst sequence. When tied to VDD or left floating,
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode Pin has an internal pull up.
Document Number: 001-74857 Rev. *F
Page 6 of 31
CY7C1481BV33
Pin Definitions (continued)
Pin Name
VDD
I/O
Description
Power Supply Power Supply Inputs to the Core of the Device.
VDDQ
I/O Power Power Supply for the I/O Circuitry.
Supply
VSS
Ground
I/O Ground Ground for the I/O Circuitry.
JTAG Serial Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature
Ground for the Core of the Device.
[1]
VSSQ
TDO
Output
is not used, this pin must be left unconnected. This pin is not available on TQFP packages.
Synchronous
TDI
JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
Input this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on
Synchronous TQFP packages.
TMS
JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
Input
this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Synchronous
TCK
NC
JTAG Clock Clock Input to the JTAG Circuit. If the JTAG feature is not used, this pin must be connected to VSS.
This pin is not available on TQFP packages.
–
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion
pins and are not internally connected to the die.
Note
1. Applicable for TQFP package. For BGA package V serves as ground for the core and the I/O circuitry.
SS
Document Number: 001-74857 Rev. *F
Page 7 of 31
CY7C1481BV33
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCDV) is 6.5 ns (133 MHz device).
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQs is written into the
specified address location. The device allows byte writes. All
I/Os are tri-stated when a write is detected, even a byte write.
Because this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/Os must be tri-stated
before the data is presented to DQs. As a safety precaution, the
data lines are tri-stated after a write cycle is detected, regardless
of the state of OE.
The CY7C1481BV33 supports secondary cache in systems
using either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™ processors.
The linear burst sequence is suited for processors that use a
linear burst sequence. The burst order is user selectable and is
determined by sampling the MODE input. Accesses are initiated
with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
2-bit on-chip wraparound burst counter captures the first address
in a burst sequence and automatically increments the address
for the rest of the burst access.
Burst Sequences
The CY7C1481BV33 provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0], and
can follow either a linear or interleaved burst order. The burst
order is determined by the state of the MODE input. A LOW on
MODE selects a linear burst sequence. A HIGH on MODE
selects an interleaved burst order. Leaving MODE unconnected
causes the device to default to an interleaved burst sequence.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Sleep Mode
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. ADSP is ignored if CE1 is HIGH.
The ZZ input pin is asynchronous. Asserting ZZ places the
SRAM in a power conservation “sleep” mode. Two clock cycles
are required to enter into or exit from this “sleep” mode. While in
this mode, data integrity is guaranteed.
Single Read Accesses
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed.
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic. It is then presented to the memory core. If the OE input is
asserted LOW, the requested data is available at the data
outputs a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
The device must be deselected before entering the “sleep”
mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1:A0
Second
Third
Address
A1:A0
Fourth
Address
A1:A0
Single Write Accesses Initiated by ADSP
Address
A1:A0
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX) are ignored during this first clock cycle. If the write
inputs are asserted active (see Truth Table for Read/Write on
page 10 for appropriate states that indicate a write) on the next
clock rise, the appropriate data is latched and written into the
device. The device allows byte writes. All I/Os are tri-stated
during a byte write. Because this is a common I/O device, the
asynchronous OE input signal must be deasserted and the I/Os
must be tri-stated prior to the presentation of data to DQs. As a
safety precaution, the data lines are tri-stated after a write cycle
is detected, regardless of the state of OE.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
Document Number: 001-74857 Rev. *F
Page 8 of 31
CY7C1481BV33
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD– 0.2 V
Min
Max
150
2tCYC
–
Unit
mA
ns
–
tZZS
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ inactive to exit sleep current This parameter is sampled
0
ns
Truth Table
The truth table for CY7C1481BV33 follows. [2, 3, 4, 5, 6]
Cycle Description
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
None
None
H
L
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L–H Tri-State
L–H Tri-State
L–H Tri-State
L–H Tri-State
L–H Tri-State
None
L
X
L
L
None
L
H
H
X
L
None
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L–H
Read Cycle, Begin Burst
L
L
L
H
X
L
L–H Tri-State
Write Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L–H
L–H
D
Q
Read Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Read Cycle, Begin Burst
L
L
L
H
L
L–H Tri-State
L–H
L–H Tri-State
L–H
L–H Tri-State
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L–H
L–H
L–H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L–H Tri-State
L–H
L–H Tri-State
Q
H
X
X
L–H
L–H
D
D
L
Notes
2. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after the
X
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a do not care
for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document Number: 001-74857 Rev. *F
Page 9 of 31
CY7C1481BV33
Truth Table for Read/Write
The read-write truth table for CY7C1481BV33 follows. [7, 8]
Function (CY7C1481BV33)
Read
GW
H
BWE
BWD
X
BWC
X
BWB
X
BWA
X
H
L
L
L
L
L
L
L
L
Read
H
H
H
H
H
Write Byte A (DQA, DQPA)
H
H
H
H
L
Write Byte B(DQB, DQPB)
H
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
Write Byte C (DQC, DQPC)
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
H
H
L
L
H
H
L
H
H
H
H
L
H
L
H
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
H
H
L
L
L
Write Byte D (DQD, DQPD)
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
H
L
L
L
L
L
L
H
H
H
L
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
L
L
H
Write All Bytes
Write All Bytes
H
L
L
L
L
L
L
X
X
X
X
X
Notes
7. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
8. Table only includes a partial listing of the byte write combinations. Any combination of BW is valid. An appropriate write is performed based on which byte write is active.
X
Document Number: 001-74857 Rev. *F
Page 10 of 31
CY7C1481BV33
TAP Registers
IEEE 1149.1 Serial Boundary Scan (JTAG)
Registers are connected between the TDI and TDO balls to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction register. Data is
serially loaded into the TDI ball on the rising edge of TCK. Data
is output on the TDO ball on the falling edge of TCK.
The CY7C1481BV33 incorporates a serial boundary scan test
access port (TAP). This port operates in accordance with IEEE
Standard 1149.1-1990 but does not have the set of functions
required for full 1149.1 compliance. These functions from the
IEEE specification are excluded because their inclusion places
an added delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not conflict
with the operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC standard 3.3 V or 2.5 V
I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls, as shown in the TAP Controller Block Diagram
on page 14. At power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
The CY7C1481BV33 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board level serial test data path.
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be connected
to VDD through a pull up resistor. TDO must be left unconnected.
At power up, the device comes up in a reset state, which does
not interfere with the operation of the device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that is placed between the TDI and
TDO balls. This shifts the data through the SRAM with minimal
delay. The bypass register is set LOW (VSS) when the BYPASS
instruction is executed.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The × 36 configuration has a
73-bit long register.
Test Mode Select (TMS)
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions are used to
capture the contents of the I/O ring.
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball serially inputs information into the registers and can
be connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information on loading the
instruction register, see the TAP Controller State Diagram on
page 13. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register.
The Boundary Scan Exit Order on page 18 show the order in
which the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.
Test Data-Out (TDO)
The TDO output ball serially clocks data-out from the registers.
Whether the output is active depends on the current state of the
TAP state machine (see Identification Codes on page 17). The
output changes on the falling edge of TCK. TDO is connected to
the least significant bit (LSB) of any register.
TAP Instruction Set
Overview
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Identification
Codes on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
To perform a RESET, force TMS HIGH (VDD) for five rising edges
of TCK. This RESET does not affect the operation of the SRAM
and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
Document Number: 001-74857 Rev. *F
Page 11 of 31
CY7C1481BV33
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
Be aware that the TAP controller clock only operates at a
frequency up to 10 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that may be captured. Repeatable
results may not be possible.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction that is executed
whenever the instruction register is loaded with all zeros.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-zero instruction.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction is loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High Z state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
IDCODE
The IDCODE instruction loads a vendor specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
The IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is in a test logic reset
state.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO balls when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High Z
state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-74857 Rev. *F
Page 12 of 31
CY7C1481BV33
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 001-74857 Rev. *F
Page 13 of 31
CY7C1481BV33
TAP Controller Block Diagram
0
Bypass Register
2 1 0
Selection
Circuitry
Selection
Circuitry
Instruction Register
TDI
TDO
31 30 29 .
Identification Register
2 1 0
.
. 2 1 0
x
.
.
.
.
.
Boundary Scan Register
TCK
TAP CONTROLLER
TM S
Document Number: 001-74857 Rev. *F
Page 14 of 31
CY7C1481BV33
TAP Timing
Figure 3 shows the TAP timing diagram.
Figure 3. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TM SS
TDIS
TM SH
Test M ode Select
(TM S)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
Parameter [9, 10]
Clock
Description
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH Time
TCK Clock LOW Time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
TCK Clock LOW to TDO Valid
–
0
10
–
ns
ns
TCK Clock LOW to TDO Invalid
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes
9.
t
and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS CH
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document Number: 001-74857 Rev. *F
Page 15 of 31
CY7C1481BV33
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times ...................................................1 ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)
Parameter [11]
Description
IOH = –4.0 mA
Conditions
VDDQ = 3.3 V
Min
2.4
2.0
2.9
2.1
–
Max
Unit
V
VOH1
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
–
IOH = –1.0 mA
IOH = –100 µA
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
–
V
VOH2
VOL1
VOL2
VIH
–
V
–
0.4
V
IOL = 8.0 mA
IOL = 1.0 mA
IOL = 100 µA
V
–
0.4
V
–
0.2
V
–
0.2
V
2.0
1.7
–0.3
–0.3
–5
VDD + 0.3
VDD + 0.3
0.8
V
V
VIL
V
0.7
V
IX
GND < VIN < VDDQ
5
µA
Note
11. All voltages refer to V (GND).
SS
Document Number: 001-74857 Rev. *F
Page 16 of 31
CY7C1481BV33
Identification Register Definitions
Bit# 24 is “1” in the ID Register definitions for both 2.5 V and 3.3 V versions of the device.
CY7C1481BV33
Instruction Field
(2M × 36)
Description
Revision Number (31:29)
000
01011
Describes the version number
Device Depth (28:24)
Reserved for internal use
Architecture/Memory Type (23:18)
Bus Width/Density (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
000001
100100
00000110100
1
Defines memory type and architecture
Defines width and density
Enables unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction Bypass
3
1
Bypass
ID
32
73
Boundary Scan Order – 165-ball FBGA
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 001-74857 Rev. *F
Page 17 of 31
CY7C1481BV33
Boundary Scan Exit Order
(2M × 36)
Bit #
1
165-ball ID
C1
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
165-ball ID
R3
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
165-ball ID
L10
K11
J11
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
165-ball ID
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
2
D1
P2
3
E1
R4
4
D2
P6
K10
J10
5
E2
R6
6
F1
N6
H11
G11
F11
7
G1
F2
P11
R8
8
9
G2
J1
P3
E11
D10
D11
C11
G10
F10
E10
A10
B10
A9
10
11
12
13
14
15
16
17
18
19
20
P4
K1
P8
L1
P9
J2
P10
R9
M1
N1
R10
R11
N11
M11
L11
M10
K2
L2
M2
R1
B9
R2
A8
Document Number: 001-74857 Rev. *F
Page 18 of 31
CY7C1481BV33
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Storage Temperature ............................... –65 C to +150 C
Latch Up Current ................................................... >200 mA
Ambient Temperature
with Power Applied .................................. –55 C to +125 C
Operating Range
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
Ambient
Range
VDD
VDDQ
Temperature
0 °C to +70 °C
–40 °C to +85 °C
Commercial
Industrial
3.3 V– 5% / 2.5 V – 5% to
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
+ 10% VDD
Electrical Characteristics
Over the Operating Range
Parameter [12, 13]
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min
Max
3.6
VDD
2.625
–
Unit
V
VDD
3.135
3.135
2.375
2.4
VDDQ
For 3.3 V I/O
For 2.5 V I/O
V
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[12]
Input LOW Voltage[12]
For 3.3 V I/O, IOH = –4.0 mA
For 2.5 V I/O, IOH = –1.0 mA
For 3.3 V I/O, IOL = 8.0 mA
For 2.5 V I/O, IOL = 1.0 mA
For 3.3 V I/O
V
2.0
–
V
–
0.4
0.4
V
–
V
2.0
VDD + 0.3 V
V
For 2.5 V I/O
1.7
VDD + 0.3 V
V
For 3.3 V I/O
–0.3
–0.3
–5
0.8
0.7
5
V
For 2.5 V I/O
V
Input Leakage Current Except ZZ GND VI VDDQ
and MODE
A
Input Current of MODE
Input = VSS
–30
–
–
5
A
A
A
A
A
mA
Input = VDD
Input Current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
Output Leakage Current
GND VI VDD, Output Disabled
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
–5
–
[14]
IDD
VDD Operating Supply Current
7.5 ns cycle,
133 MHz
335
ISB1
ISB2
ISB3
ISB4
Notes
Automatic CE Power Down
Current – TTL Inputs
Max VDD, Device Deselected, 7.5 ns cycle,
VIN VIH or VIN VIL, f = fMAX, 133 MHz
inputs switching
–
–
–
–
200
150
200
165
mA
mA
mA
mA
Automatic CE Power Down
Current – CMOS Inputs
Max VDD, Device Deselected, 7.5 ns cycle,
VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz
f = 0, inputs static
Automatic CE Power Down
Current – CMOS Inputs
Max VDD, Device Deselected, 7.5 ns cycle,
VIN VDDQ – 0.3 V or VIN 0.3 V, 133 MHz
f = fMAX, inputs switching
Automatic CE Power Down
Current – TTL Inputs
Max VDD, Device Deselected, 7.5 ns cycle,
VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz
f = 0, inputs static
12. Overshoot: V
< V +1.5 V (pulse width less than t
/2). Undershoot: V
> –2 V (pulse width less than t
/2).
IH(AC)
DD
CYC
IL(AC)
CYC
13. T
: assumes a linear ramp from 0 V to V
within 200 ms. During this time V < V and V
< V
.
Power-up
DD(minimum)
IH
DD
DDQ
DD
14. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-74857 Rev. *F
Page 19 of 31
CY7C1481BV33
Capacitance
100-pin TQFP 165-ball FBGA
Parameter [15]
Description
Test Conditions
Unit
Max
Max
CADDRESS
CDATA
CCTRL
CCLK
Address Input Capacitance
Data Input Capacitance
Control Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
6
5
8
6
5
6
5
8
6
5
pF
pF
pF
pF
pF
CIO
Thermal Resistance
100-pin TQFP 165-ballFBGA
Parameter [15]
Description
Test Conditions
Unit
Package
Package
JA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
24.63
16.3
C/W
JC
Thermal Resistance
(Junction to Case)
2.28
2.1
C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.3V IO Test Load
R = 317
3.3V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
10%
L
GND
5 pF
R = 351
1 ns
1 ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V IO Test Load
R = 1667
2.5V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50
0
10%
L
5 pF
R = 1538
1 ns
1 ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note
15. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-74857 Rev. *F
Page 20 of 31
CY7C1481BV33
Switching Characteristics
Over the Operating Range
133 MHz
Unit
Parameter [16, 17]
Description
VDD(typical) to the First Access [18]
Min
Max
tPOWER
Clock
tCYC
1
–
ms
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
–
–
–
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low Z [19, 20, 21]
–
2.5
3.0
–
6.5
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
tCHZ
Clock to High Z [19, 20, 21]
3.8
3.0
–
tOEV
OE LOW to Output Valid
–
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to Output Low Z [19, 20, 21]
OE HIGH to Output High Z [19, 20, 21]
0
–
3.0
Address Setup Before CLK Rise
ADSP, ADSC Setup Before CLK Rise
ADV Setup Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX Setup Before CLK Rise
Data Input Setup Before CLK Rise
Chip Enable Setup
tDS
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
GW, BWE, BWX Hold After CLK Rise
ADV Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
tWEH
tADVH
tDH
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes
16. Timing reference level is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
17. Test conditions shown in (a) of Figure 4 on page 20 unless otherwise noted.
18. This part has an internal voltage regulator; t is the time that the power is supplied above V
initially, before a read or write operation can be initiated.
DD(minimum)
POWER
19. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of Figure 4 on page 20. Transition is measured ±200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
20. At any supplied voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
CLZ
OEHZ
OELZ
CHZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. The device is designed to
achieve High Z before Low Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document Number: 001-74857 Rev. *F
Page 21 of 31
CY7C1481BV33
Timing Diagrams
Figure 5. Read Cycle Timing [22]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE, BWX
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2
+
3)
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
22. On this diagram, when CE is LOW: CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH: CE is HIGH, CE is LOW, or CE is HIGH.
1
2
3
1
2
3
Document Number: 001-74857 Rev. *F
Page 22 of 31
CY7C1481BV33
Timing Diagrams (continued)
Figure 6. Write Cycle Timing [23, 24]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE, BWX
GW
t
t
WEH
WES
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Notes
23. On this diagram, when CE is LOW: CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH: CE is HIGH, CE is LOW, or CE is HIGH.
1
2
3
1
2
3
24.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BW LOW.
X
Document Number: 001-74857 Rev. *F
Page 23 of 31
CY7C1481BV33
Timing Diagrams (continued)
Figure 7. Read/Write Cycle Timing [25, 26, 27]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
Notes
25. On this diagram, when CE is LOW: CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH: CE is HIGH, CE is LOW, or CE is HIGH.
1
2
3
1
2
3
26. The data bus (Q) remains in High Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
27. GW is HIGH.
Document Number: 001-74857 Rev. *F
Page 24 of 31
CY7C1481BV33
Timing Diagrams (continued)
Figure 8. ZZ Mode Timing [28, 29]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
28. Device must be deselected when entering ZZ mode. See Truth Table on page 9 for all possible signal conditions to deselect the device.
29. DQs are in High Z when exiting ZZ sleep mode.
Document Number: 001-74857 Rev. *F
Page 25 of 31
CY7C1481BV33
Ordering Information
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
133 CY7C1481BV33-133AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
lndustrial
Ordering Code Definitions
CY
7
C
1481 B V33 - 133 XX
X X
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C
X = Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP (3 chip enable); BZ = 165-ball FBGA
Speed Grade: 133 MHz
V33 = 3.3 V VDD
Die Revision: B errata fix PCN084636
Part Identifier: 1481 = SCD, 2Mb × 36 (72Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-74857 Rev. *F
Page 26 of 31
CY7C1481BV33
Package Diagrams
Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș 2
ș
1
ș
DIMENSIONS
MIN. NOM. MAX.
1.60
NOTE:
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
MOLD PROTRUSION/END FLASH SHALL
A
0.05
0.15
A1
A2
D
1.35 1.40 1.45
15.80 16.00 16.20
13.90 14.00 14.10
21.80 22.00 22.20
19.90 20.00 20.10
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
D1
E
E1
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
0.08
0.08
0°
R
R
ș
0.20
0.20
7°
1
2
ș 1
ș 2
c
0°
11° 12° 13°
0.20
0.22 0.30 0.38
0.45 0.60 0.75
1.00 REF
b
L
L1
L 2
L 3
e
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 001-74857 Rev. *F
Page 27 of 31
CY7C1481BV33
Package Diagrams (continued)
Figure 10. 165-ball FBGA (15 × 17 × 1.4 mm (0.45 Ball Diameter)) Package Outline, 51-85165
51-85165 *E
Document Number: 001-74857 Rev. *F
Page 28 of 31
CY7C1481BV33
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
Chip Enable
Symbol
°C
Unit of Measure
CMOS
EIA
Complementary Metal Oxide Semiconductor
Electronic Industries Alliance
Fine-Pitch Ball Grid Array
Input/Output
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
millivolt
MHz
µA
mA
mm
ms
mV
ns
FBGA
I/O
JEDEC
OE
Joint Electron Devices Engineering Council
Output Enable
SRAM
TQFP
TTL
Static Random Access Memory
Thin Quad Flat Pack
nanosecond
ohm
Transistor-Transistor Logic
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 001-74857 Rev. *F
Page 29 of 31
CY7C1481BV33
Document History Page
Document Title: CY7C1481BV33, 72-Mbit (2M × 36) Flow-Through SRAM
Document Number: 001-74857
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
3466988
3508574
3862706
GOPA
GOPA
PRIT
01/17/2012 New data sheet.
*A
*B
01/25/2012 Changed status from Preliminary to Final.
01/09/2013 No technical updates.
Completing Sunset Review.
*C
4575228
PRIT
11/20/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
*D
5071457
PRIT
01/04/2016 Updated Package Diagrams:
spec 51-85165 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*E
*F
5309766
6010395
PRIT
CNX
06/15/2016 Updated Truth Table.
Updated to new template.
01/02/2018 Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
Completing Sunset Review.
Document Number: 001-74857 Rev. *F
Page 30 of 31
CY7C1481BV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Memory
cypress.com/support
cypress.com/memory
cypress.com/mcu
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2012-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-74857 Rev. *F
Revised January 2, 2018
Page 31 of 31
i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation.
相关型号：
CY7C1481BV33-133BZI
Cache SRAM, 2MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CYPRESS
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