CY7C1486BV25-167BGC [CYPRESS]
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; 72兆位（ 2M ×36 / 4M ×18 / 1M X 72 ），流水线同步SRAM
| 型号： | CY7C1486BV25-167BGC |
| 厂家： | 
CYPRESS |
| 描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| 文件： | 总31页 (文件大小：933K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined Sync SRAM
Features
Functional Description
■ Supports bus operation up to 250 MHz
■ Available speed grades are 250, 200, and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ 2.5V core power supply
The
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1]
SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
■ 2.5V IO operation
■ Fast clock-to-output time
❐ 3.0 ns (for 250 MHz device)
■ Provide high performance 3-1-1-1 access rate
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) is active. Subsequent burst addresses
can be internally generated as controlled by the Advance pin
(ADV).
■ User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self timed writes
Address, data inputs, and write controls are registered on-chip
to initiate a self timed Write cycle. This part supports Byte Write
operations (see “Pin Definitions” on page 7 and “Truth Table” on
page 10 for further details). Write cycles can be one to two or four
bytes wide, as controlled by the byte write control inputs. When
it is active LOW, GW writes all bytes.
■ Asynchronous output enable
■ Single cycle chip deselect
■ CY7C1480BV25, CY7C1482BV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1486BV25
available in Pb-free and non-Pb-free 209-ball FBGA package
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ “ZZ” Sleep Mode option
Selection Guide
Description
Maximum Access Time
250 MHz
3.0
200 MHz
3.0
167 MHz
3.4
Unit
ns
Maximum Operating Current
Maximum CMOS Standby Current
450
450
400
mA
mA
120
120
120
Note
1. For best practices recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 001-15143 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 29, 2008
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Logic Block Diagram – CY7C1480BV25 (2M x 36)
A0, A1,
A
ADDRESS
REGISTER
2
A
[1:0]
MODE
Q1
Q0
ADV
CLK
BURST
COUNTER
AND
CLR
LOGIC
ADSC
ADSP
DQ D ,DQP D
BYTE
WRITE REGISTER
DQ D ,DQP
BYTE
WRITE DRIVER
D
BW
BW
D
DQ C ,DQP
BYTE
C
DQ C ,DQP
BYTE
C
C
OUTPUT
BUFFERS
WRITE DRIVER
OUTPUT
MEMORY
WRITE REGISTER
DQs
SENSE
AMPS
ARRAY
REGISTERS
DQP
DQP
DQP
DQP
A
DQ B ,DQP
BYTE
WRITE DRIVER
B
E
DQ B ,DQP
BYTE
WRITE REGISTER
B
B
C
D
BW
B
A
DQ A ,DQP
BYTE
WRITE DRIVER
A
DQ A ,DQP
BYTE
WRITE REGISTER
A
BW
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1482BV25 (4M x 18)
ADDRESS
REGISTER
A0, A1,
A
A[1:0]
2
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ B, DQP
WRITE DRIVER
B
DQ B, DQP
WRITE REGISTER
B
OUTPUT
BUFFERS
BW
B
DQs
DQP
DQP
OUTPUT
REGISTERS
SENSE
AMPS
MEMORY
ARRAY
A
B
DQ A, DQP
WRITE DRIVER
A
E
DQ A, DQP
WRITE REGISTER
A
BW
A
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
1
PIPELINED
ENABLE
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Document #: 001-15143 Rev. *D
Page 2 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Logic Block Diagram – CY7C1486BV25 (1M x 72)
ADDRESS
REGISTER
A0, A1,A
A[1:0]
MODE
Q1
Q0
ADV
CLK
BINARY
COUNTER
CLR
ADSC
ADSP
DQ
H
, DQP
H
DQ
H, DQPH
BW
BW
H
G
WRITE DRIVER
WRITE DRIVER
DQ
G, DQPG
DQ
F, DQPF
WRITE DRIVER
WRITE DRIVER
DQ
F, DQPF
DQ
F, DQPF
BW
BW
BW
BW
F
E
WRITE DRIVER
WRITE DRIVER
DQ E
E
,
DQP
DQ
E, DQPE
WRITE DRIVER
WRITE DRIVER
MEMORY
ARRAY
DQ
D, DQPD
DQ
D, DQPD
D
WRITE DRIVER
WRITE DRIVER
DQ
C, DQPC
DQ
C, DQPC
C
WRITE DRIVER
WRITE DRIVER
OUTPUT
OUTPUT
REGISTERS
SENSE
AMPS
DQs
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
BUFFERS
E
A
B
C
D
E
DQ
B, DQPB
DQ
B, DQPB
WRITE DRIVER
BW
BW
B
WRITE DRIVER
DQ
A, DQPA
DQ
A
, DQP
A
F
WRITE DRIVER
A
WRITE DRIVER
G
H
BWE
INPUT
GW
CE1
CE2
CE3
OE
REGISTERS
ENABLE
REGISTER
PIPELINED
ENABLE
SLEEP
CONTROL
ZZ
Document #: 001-15143 Rev. *D
Page 3 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Pin Configurations
Figure 1. 100-Pin TQFP Pinout
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQc
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
NC
14
VDD
NC
VSS
NC
VDD
ZZ
15
CY7C1482BV25
(4M x 18)
CY7C1480BV25
(2M x 36)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
ZZ
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
Document #: 001-15143 Rev. *D
Page 4 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1480BV25 (2M x 36)
1
2
3
4
5
6
7
8
9
10
A
11
NC
NC/288M
NC/144M
DQPC
A
B
C
D
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
A
BWE
GW
VSS
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
A
CE2
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
VSS
NC/1G
DQB
DQC
DQC
VSS
VDD
DQC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
E
F
DQC
DQC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQB
ZZ
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
TDI
A1
TDO
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
CY7C1482BV25 (4M x 18)
1
2
A
3
4
5
NC
6
7
8
9
10
A
11
A
NC/288M
NC/144M
NC
A
B
C
D
BWB
NC
CE3
CLK
VSS
VSS
CE1
CE2
BWE
GW
VSS
VSS
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
A
BWA
VSS
VSS
A
NC/576M
DQPA
DQA
NC
VDDQ
VDDQ
VSS
VDD
VSS
NC/1G
NC
NC
DQB
VDD
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
TDI
A1
TDO
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 001-15143 Rev. *D
Page 5 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Pin Configurations (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1486BV25 (1M × 72)
1
2
3
4
5
6
7
8
9
10
11
DQG
DQG
DQG
A
B
C
D
E
F
DQG
DQG
A
DQB
DQB
CE2
ADSP ADSC
ADV
A
A
CE3
DQB
DQB
NC/288M
NC/144M
BWE
CE1
BWSF
BWSG
BWSD
BWSB
BWSE
NC
BWSC
BWSH
VSS
DQG
DQG
NC/576M
GW
BWSA DQB
DQB
DQB
DQG
NC/1G OE
VSS
NC
DQB
DQPG DQPC
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VDD
VSS
VDD
DQPF DQPB
DQC
DQC
VSS
DQF
DQF
VSS
VDDQ
VSS
NC
NC
NC
NC
VSS
NC
NC
VSS
G
H
J
DQC
DQC
DQC
VDDQ
VSS
VDDQ
VSS
DQF
DQF
DQF
DQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
DQC
DQC
NC
F
VDDQ
DQC
NC
VDDQ
VDDQ
CLK
VDDQ
NC
DQF
NC
DQF
NC
K
L
NC
NC
DQH
DQH
DQH
VDDQ
VSS
VDDQ
VSS
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
DQA
DQA
DQ
A
M
N
P
R
T
VSS
VDDQ
VSS
VDDQ
NC
DQH
DQH
DQH
VSS
VDD
VSS
DQA
DQA
DQA
VDDQ
DQH
DQH
DQPD
DQD
DQD
NC
ZZ
DQA
DQA
DQPA
DQE
DQE
VSS
VDDQ
VSS
A
VDDQ
VDD
NC
A
DQPH
DQD
DQD
DQD
DQD
VDDQ
VDD
DQPE
DQE
DQE
DQE
DQE
VSS
NC
A
MODE
A
U
V
W
A
A
A
A
A1
A
DQD
DQD
A
A
A
A
DQE
DQE
TDI
TDO
TCK
A0
A
TMS
Document #: 001-15143 Rev. *D
Page 6 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Table 1. Pin Definitions
Pin Name
IO
Description
A0, A1, A
Input-
Synchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:
A0 are fed to the two-bit counter.
Input-
Synchronous
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
BWA, BWB, BWC,
BWD, BWE, BWF,
BWG, BWH
GW
Input-
Synchronous
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
BWE
CLK
CE1
Input-
Synchronous
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Captures all synchronous inputs to the device. Also increments the burst counter
when ADV is asserted LOW during a burst operation.
Input-
Synchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
sampled only when a new external address is loaded.
CE2
CE3
OE
Input-
Synchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external
address is loaded.
Input-
Synchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external
address is loaded.
Input-
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins.
Asynchronous When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
Input-
Synchronous
Advance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When asserted,
it automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ
Input-
ZZ “Sleep” Input, Active HIGH. When asserted HIGH places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin must be LOW
or left floating. ZZ pin has an internal pull down.
IO-
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
DQs, DQPs
Synchronous
VDD
VSS
Power Supply Power Supply Inputs to the Core of the Device.
Ground
Ground for the Core of the Device.
Ground for the IO Circuitry.
[2]
VSSQ
IO Ground
VDDQ
IO Power Supply Power Supply for the IO Circuitry.
Note
2. Applicable for TQFP package. For BGA package V serves as ground for the core and the IO circuitry.
SS
Document #: 001-15143 Rev. *D
Page 7 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Table 1. Pin Definitions (continued)
Pin Name
IO
Description
MODE
Input Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.
TDO
TDI
JTAG Serial
Output
Synchronous
Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not used, this pin must be disconnected. This pin is not available on TQFP packages.
JTAG Serial Input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not used, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TMS
JTAG Serial Input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
JTAG Clock
-
is not used, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TCK
NC
Clock Input to the JTAG Circuitry. If the JTAG feature is not used, this pin must be connected
to VSS. This pin is not available on TQFP packages.
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
propagate through the output register and onto the data bus
within 3.0 ns (250-MHz device) if OE is active LOW. The only
Functional Overview
exception occurs when the SRAM is emerging from a deselected
state to a selected state; its outputs are always tri-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive single
read cycles are supported. After the SRAM is deselected at clock
rise by the chip select and either ADSP or ADSC signals, its
output tri-states immediately.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.0 ns (250 MHz device).
The
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25
supports secondary cache in systems using either a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium and i486™ processors. The linear burst
sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the Processor Address Strobe (ADSP) or the Controller
Address Strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the memory array. The write signals
(GW, BWE, and BWX) and ADV inputs are ignored during this
first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the BWE and BWX signals control the write operation.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
The
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25
provides Byte Write capability that is described in the “Truth
Table for Read/Write” on page 11. Asserting the Byte Write
Enable input (BWE) with the selected Byte Write (BWX) input,
selectively writes to only the desired bytes. Bytes not selected
during a byte write operation remain unaltered. A synchronous
self-timed write mechanism is provided to simplify the write
operations.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs (A) is stored
into the address advancement logic and the Address Register
while being presented to the memory array. The corresponding
data is allowed to propagate to the input of the Output Registers.
At the rising edge of the next clock the data is allowed to
Because CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 is
a common IO device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so tri-states the output drivers. As a safety precaution,
DQs are automatically tri-stated whenever a write cycle is
detected, regardless of the state of OE.
Document #: 001-15143 Rev. *D
Page 8 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Single Write Accesses Initiated by ADSC
Sleep Mode
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the write inputs (GW, BWE, and
BWX) are asserted active to conduct a write to the desired
byte(s). ADSC-triggered write accesses need a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
The ZZ input pin is asynchronous. Asserting ZZ places the
SRAM in a power conservation “sleep” mode. Two clock cycles
are required to enter into or exit from this “sleep” mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the “sleep” mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the “sleep” mode. CE1, CE2, CE3,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Table 2. Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Because CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 is
a common IO device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so tri-states the output drivers. As a safety precaution,
DQs are automatically tri-stated whenever a write cycle is
detected, regardless of the state of OE.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Burst Sequences
Table 3. Linear Burst Address Table
(MODE = GND)
The
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25
provides a two-bit wraparound counter, fed by A1: A0, that imple-
ments either an interleaved or linear burst sequence. The inter-
leaved burst sequence is designed specifically to support Intel
Pentium applications. The linear burst sequence is designed to
support processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep Mode Standby Current
Device Operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
Min
Max
Unit
mA
ns
120
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ Recovery Time
ZZ < 0.2V
2tCYC
ns
ZZ Active to Sleep Current
ZZ Inactive to Exit Sleep Current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
0
ns
Document #: 001-15143 Rev. *D
Page 9 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Table 4. Truth Table
The truth table for CY7C1480BV25, CY7C1482BV25, and CY7C1486BV25 follows.[3, 4, 5, 6, 7]
Operation
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
None
None
H
L
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L-H
L
L
L
H
X
L
L-H Tri-State
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State
L-H
L-H Tri-State
Q
H
X
X
L-H
L-H
D
D
L
Notes
3. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after the
X
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to enable the outputs to tri-state. OE is a do not care for
the remainder of the write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document #: 001-15143 Rev. *D
Page 10 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Table 5. Truth Table for Read/Write
The read-write truth table for the CY7C1480BV25 follows.[5]
Function (CY7C1480BV25)
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
X
H
H
L
BWA
X
H
L
Read
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
L
L
H
L
L
L
Write Byte C – (DQC and DQPC)
Write Bytes C, A
L
H
H
L
H
L
L
L
Write Bytes C, B
L
L
H
L
Write Bytes C, B, A
Write Byte D – (DQD and DQPD)
Write Bytes D, A
L
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
Write Bytes D, B
L
L
H
L
Write Bytes D, B, A
Write Bytes D, C
L
L
L
L
L
H
H
L
H
L
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes
X
X
X
X
X
Table 6. Truth Table for Read/Write
The read-write truth table for the CY7C1482BV25 follows.[5]
Function (CY7C1482BV25)
GW
H
BWE
BWB
X
BWA
Read
H
L
L
L
L
L
X
X
H
L
Read
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
Write All Bytes
H
H
H
L
H
L
H
L
H
L
L
Write All Bytes
L
X
X
Table 7. Truth Table for Read/Write
The read-write truth table for the CY7C1486BV25 follows.[8]
Function (CY7C1486BV25)
GW
H
BWE
BWX
Read
H
L
L
L
X
X
Read
H
All BW = H
Write Byte x – (DQx and DQPx)
Write All Bytes
H
L
All BW = L
X
H
Write All Bytes
L
Note
8. BWx represents any byte write signal BW[0..7]. To enable any byte write BWx, a Logic LOW signal must be applied at clock rise. Any number of byte writes can be
enabled at the same time for a supplied write.
Document #: 001-15143 Rev. *D
Page 11 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Test Mode Select (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up inter-
nally, resulting in a logic HIGH level.
The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 incor-
porates a serial boundary scan test access port (TAP). This port
operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V IO logic levels.
Test Data-In (TDI)
The TDI ball serially inputs information into the registers and can
be connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information about loading
the instruction register, see the TAP Controller State Diagram.
TDI is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant
bit (MSB) of any register. (See TAP Controller Block Diagram.)
The
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be connected
to VDD through a pull up resistor. TDO must be left unconnected.
At power up, the device comes up in a reset state, which does
not interfere with the operation of the device.
The TDO output ball is used to serially clock data-out from the
registers. Whether the output is active depends on the current
state of the TAP state machine. The output changes on the falling
edge of TCK. TDO is connected to the least significant bit (LSB)
of any register. (See TAP Controller State Diagram.)
Figure 3. TAP Controller Block Diagram
Figure 2. TAP Controller State Diagram
0
TEST-LOGIC
1
Bypass Register
RESET
0
2
1
0
0
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
Selection
Circuitry
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
TDI
TDO
0
0
.
.
. 2 1
1
1
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
. 2 1
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
TCK
PAUSE-DR
0
PAUSE-IR
1
0
TAP CONTROLLER
TM S
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
UPDATE-DR
UPDATE-IR
Perform a RESET by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
1
0
1
0
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Test Access Port (TAP)
Registers are connected between the TDI and TDO balls to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction register. Data is
serially loaded into the TDI ball on the rising edge of TCK. Data
is output on the TDO ball on the falling edge of TCK.
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Document #: 001-15143 Rev. *D
Page 12 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Instruction Register
rather, it performs a capture of the IO ring when these instruc-
tions are executed.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the “TAP Controller Block Diagram”
on page 12. At power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board-level serial test data path.
EXTEST
EXTEST is a mandatory 1149.1 instruction that is executed
whenever the instruction register is loaded with all zeros.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-zero instruction.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
Boundary Scan Register
IDCODE
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The x36 configuration has a
73-bit-long register, and the x18 configuration has a 54-bit-long
register.
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller moves to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used
to capture the contents of the IO ring.
The IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is in a test logic reset
state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO balls when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High-Z
state.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
SAMPLE/PRELOAD
Identification (ID) Register
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in “Identification Register Definitions” on
page 15.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
Be aware that the TAP controller clock can only operate at a
frequency up to 10 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that may be captured. Repeatable
results may not be possible.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Identification
Codes” on page 16. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (tCS plus tCH).
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the IO buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
Document #: 001-15143 Rev. *D
Page 13 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Figure 4. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range[9, 10]
Parameter
Clock
tTCYC
tTF
Description
Min
Max
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH Time
TCK Clock LOW Time
50
ns
MHz
ns
20
tTH
20
20
tTL
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
10
ns
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
Setup Times
tTMSS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Notes
9.
t
and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS CH
10. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document #: 001-15143 Rev. *D
Page 14 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Figure 5. 2.5V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
1.25V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[11]
Parameter
VOH1
Description
Test Conditions
Min
1.7
2.1
Max
Unit
V
Output HIGH Voltage IOH = –1.0 mA, VDDQ = 2.5V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage IOH = –100 μA, VDDQ = 2.5V
V
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOL = 1.0 mA, VDDQ = 2.5V
IOL = 100 μA, VDDQ = 2.5V
VDDQ = 2.5V
0.4
0.2
V
V
1.7
–0.3
–5
VDD + 0.3
V
VIL
VDDQ = 2.5V
0.7
5
V
IX
GND ≤ VI ≤ VDDQ
μA
Table 8. Identification Register Definitions
CY7C1480BV25
(2M x36)
CY7C1482BV25
(4M x 18)
CY7C1486BV25
Instruction Field
Description
(1M x72)
Revision Number (31:29)
Device Depth (28:24)
000
000
000
Describes the version number
Reserved for internal use
01011
000000
01011
000000
01011
000000
Architecture/Memory
Type(23:18)
Defines memory type and
architecture
Bus Width/Density(17:12)
100100
010100
110100
Defines width and density
Cypress JEDEC ID Code
(11:1)
00000110100
00000110100
00000110100
Enablesunique identification of
SRAM vendor
ID Register Presence
Indicator (0)
1
1
1
Indicates the presence of an ID
register
Table 9. Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
Instruction
Bypass
ID
3
1
3
1
3
1
32
73
-
32
54
-
32
-
Boundary Scan Order – 165FBGA
Boundary Scan Order – 209BGA
112
Note
11. All voltages refer to V (GND).
SS
Document #: 001-15143 Rev. *D
Page 15 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Table 10. Identification Codes
Instruction Code
EXTEST
Description
000
001
Captures the IO ring contents.
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures the IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Table 11. Boundary Scan Exit Order (2M x 36)
Bit #
1
165-Ball ID
C1
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
165-Ball ID
R3
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
165-Ball ID
L10
K11
J11
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
165-Ball ID
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
2
D1
P2
3
E1
R4
4
D2
P6
K10
J10
5
E2
R6
6
F1
N6
H11
G11
F11
7
G1
F2
P11
R8
8
9
G2
J1
P3
E11
D10
D11
C11
G10
F10
E10
A10
B10
A9
10
11
12
13
14
15
16
17
18
19
20
P4
K1
P8
L1
P9
J2
P10
R9
M1
N1
R10
R11
N11
M11
L11
M10
K2
L2
M2
R1
B9
R2
A8
Document #: 001-15143 Rev. *D
Page 16 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Boundary Scan Exit Order (4M x 18)
Bit #
1
165-Ball ID
D2
Bit #
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
165-Ball ID
R8
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
165-Ball ID
C11
A11
A10
B10
A9
2
E2
P3
3
F2
P4
4
G2
P8
5
J1
P9
6
K1
P10
R9
B9
7
L1
A8
8
M1
N1
R10
R11
M10
L10
K10
J10
H11
G11
F11
E11
D11
B8
9
A7
10
11
12
13
14
15
16
17
18
R1
B7
R2
B6
R3
A6
P2
B5
R4
A4
P6
B3
R6
A3
N6
A2
P11
B2
Document #: 001-15143 Rev. *D
Page 17 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Boundary Scan Exit Order (1M x 72)
Bit #
1
209-Ball ID
A1
Bit #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
209-Ball ID
T1
Bit #
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
209-Ball ID
V10
U11
U10
T11
Bit #
85
209-Ball ID
C11
C10
B11
B10
A11
A10
A9
2
A2
T2
86
3
B1
U1
87
4
B2
U2
88
5
C1
C2
D1
D2
E1
V1
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
89
6
V2
90
7
W1
W2
T6
91
8
92
U8
9
93
A7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
E2
V3
94
A5
F1
V4
95
A6
F2
U4
96
D6
G1
G2
H1
H2
J1
W5
V6
97
B6
98
D7
W6
U3
L10
99
K3
P6
100
101
102
103
104
105
106
107
108
109
110
111
112
A8
U9
J11
B4
J2
V5
J10
B3
L1
U5
H11
H10
G11
G10
F11
C3
L2
U6
C4
M1
M2
N1
N2
P1
W7
V7
C8
C9
U7
B9
V8
F10
E10
E11
D11
D10
B8
V9
A4
P2
W11
W10
V11
C6
R2
R1
B7
A3
Document #: 001-15143 Rev. *D
Page 18 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........–0.3V to +3.6V
Supply Voltage on VDDQ Relative to GND.......–0.3V to +VDD
Ambient
Range
VDD
VDDQ
Temperature
0°C to +70°C
–40°C to +85°C
DC Voltage Applied to Outputs
in Tri-State ...........................................–0.5V to VDDQ + 0.5V
Commercial
Industrial
2.5V –5%/+5% 2.5V–5%to
VDD
Electrical Characteristics
Over the Operating Range[12, 13]
Parameter
VDD
Description
Test Conditions
Min
2.375
2.375
2.0
Max
2.625
VDD
Unit
V
Power Supply Voltage
IO Supply Voltage
VDDQ
VOH
For 2.5V IO
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[12]
Input LOW Voltage[12]
For 2.5V IO, IOH = –1.0 mA
For 2.5V IO, IOL = 1.0 mA
For 2.5V IO
V
VOL
0.4
V
VIH
1.7
–0.3
–5
VDD + 0.3V
V
VIL
For 2.5V IO
0.7
5
V
IX
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
μA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
μA
μA
5
Input Current of ZZ
Input = VSS
Input = VDD
μA
30
5
μA
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
μA
[14]
IDD
VDD Operating Supply
Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speeds
450
450
400
200
200
200
120
mA
mA
mA
mA
mA
mA
mA
ISB1
Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
ISB2
Automatic CE
Power Down
Current—CMOS Inputs f = 0
VDD = Max, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
ISB3
Automatic CE
Power Down
Current—CMOS Inputs f = fMAX = 1/tCYC
VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz
200
200
200
135
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speeds
ISB4
Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
Notes
12. Overshoot: V (AC) < V +1.5V (pulse width less than t
/2).Undershoot: V (AC) > –2V (pulse width less than t
/2).
IH
DD
CYC
IL
CYC
.
13. Power up: assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
DD
IH
DD
DDQ
DD
14. The operation current is calculated with 50% read cycle and 50% write cycle.
Document #: 001-15143 Rev. *D
Page 19 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Capacitance
Tested initially and after any design or process change that may affect these parameters.
100 TQFP
165 FBGA 209 FBGA
Parameter
CADDRESS
Description
Test Conditions
Unit
Package
Package
Package
Address Input Capacitance
Data Input Capacitance
Control Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
TA = 25°C, f = 1 MHz,
6
5
8
6
5
6
5
8
6
5
6
5
8
6
5
pF
pF
pF
pF
pF
VDD = 2.5V
CDATA
CCTRL
CCLK
CIO
VDDQ = 2.5V
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
100 TQFP
165 FBGA
Max
209 FBGA
Max
Parameter
Description
Test Conditions
Unit
Max
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
24.63
16.3
15.2
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
2.28
2.1
1.7
°C/W
AC Test Loads and Waveforms
2.5V IO Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 1583Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document #: 001-15143 Rev. *D
Page 20 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Switching Characteristics
Over the Operating Range. Timing reference level is 1.25V when VDDQ = 2.5V. Test conditions shown in (a) of “AC Test Loads and
Waveforms” on page 20 unless otherwise noted.
250 MHz
200 MHz
167 MHz
Parameter
tPOWER
Description
Unit
Min
Max
Min
Max
Min
Max
VDD(Typical) to the first access[15]
1
1
1
ms
Clock
tCYC
Clock Cycle Time
Clock HIGH
4.0
2.0
2.0
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCO
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[16, 17, 18]
3.0
3.0
3.4
ns
ns
ns
ns
ns
ns
ns
tDOH
1.3
1.3
1.3
1.3
1.5
1.5
tCLZ
tCHZ
Clock to High-Z[16, 17, 18]
3.0
3.0
3.0
3.0
3.4
3.4
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to Output Low-Z[16, 17, 18]
OE HIGH to Output High-Z[16, 17, 18]
0
0
0
3.0
3.0
3.4
Address Setup Before CLK Rise
ADSC, ADSP Setup Before CLK Rise
ADV Setup Before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX Setup Before CLK Rise
Data Input Setup Before CLK Rise
Chip Enable Setup Before CLK Rise
tDS
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
tADVH
tWEH
GW, BWE, BWX Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tDH
tCEH
Notes
15. This part has an internal voltage regulator; t
is the time that the power is supplied above V (minimum) initially before a read or write operation can be initiated.
DD
POWER
16. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 20. Transition is measured ±200 mV
CHZ CLZ OELZ
OEHZ
from steady-state voltage.
17. At any possible voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
OEHZ
OELZ
CHZ
CLZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z before Low-Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document #: 001-15143 Rev. *D
Page 21 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Switching Waveforms
Timing for the read cycle is shown in Figure 6.[19]
Figure 6. Read Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BWx
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
OELZ
t
CHZ
DOH
t
CLZ
t
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A2
+
3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
19. On this diagram, when CE is LOW: CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH: CE is HIGH, CE is LOW, or CE is HIGH.
1
2
3
1
2
3
Document #: 001-15143 Rev. *D
Page 22 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Switching Waveforms (continued)
Timing for the write cycle is shown in Figure 7.[19, 20]
Figure 7. Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
ADDRESS
BWE,
t
t
AH
AS
A1
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note
20. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BW LOW.
X
Document #: 001-15143 Rev. *D
Page 23 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Switching Waveforms (continued)
Timing for the read-write cycle is shown in Figure 8.[19, 21, 22]
Figure 8. Read/Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE, BW
t
t
WEH
WES
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
CLZ
OEHZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes
21. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
22. GW is HIGH.
Document #: 001-15143 Rev. *D
Page 24 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Switching Waveforms (continued)
Timing for ZZ mode is shown in Figure 9.[23, 24]
Figure 9. ZZ Mode Timing
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
23. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.
24. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 001-15143 Rev. *D
Page 25 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
167 CY7C1480BV25-167AXC
CY7C1482BV25-167AXC
CY7C1480BV25-167BZC
CY7C1482BV25-167BZC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1480BV25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1482BV25-167BZXC
CY7C1486BV25-167BGC
CY7C1486BV25-167BGXC
CY7C1480BV25-167AXI
CY7C1482BV25-167AXI
CY7C1480BV25-167BZI
CY7C1482BV25-167BZI
CY7C1480BV25-167BZXI
CY7C1482BV25-167BZXI
CY7C1486BV25-167BGI
CY7C1486BV25-167BGXI
200 CY7C1480BV25-200AXC
CY7C1482BV25-200AXC
CY7C1480BV25-200BZC
CY7C1482BV25-200BZC
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1480BV25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1482BV25-200BZXC
CY7C1486BV25-200BGC
CY7C1486BV25-200BGXC
CY7C1480BV25-200AXI
CY7C1482BV25-200AXI
CY7C1480BV25-200BZI
CY7C1482BV25-200BZI
CY7C1480BV25-200BZXI
CY7C1482BV25-200BZXI
CY7C1486BV25-200BGI
CY7C1486BV25-200BGXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
Document #: 001-15143 Rev. *D
Page 26 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
250 CY7C1480BV25-250AXC
CY7C1482BV25-250AXC
CY7C1480BV25-250BZC
CY7C1482BV25-250BZC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1480BV25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1482BV25-250BZXC
CY7C1486BV25-250BGC
CY7C1486BV25-250BGXC
CY7C1480BV25-250AXI
CY7C1482BV25-250AXI
CY7C1480BV25-250BZI
CY7C1482BV25-250BZI
CY7C1480BV25-250BZXI
CY7C1482BV25-250BZXI
CY7C1486BV25-250BGI
CY7C1486BV25-250BGXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
Document #: 001-15143 Rev. *D
Page 27 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Package Diagrams
Figure 10. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
1.00 REF.
51-85050-*B
DETAIL
A
Document #: 001-15143 Rev. *D
Page 28 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Package Diagrams (continued)
Figure 11. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45 0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15(4X)
SEATING PLANE
C
51-85165-*A
Document #: 001-15143 Rev. *D
Page 29 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Package Diagrams (continued)
Figure 12. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167
51-85167-**
Document #: 001-15143 Rev. *D
Page 30 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Document History Page
Document Title: CY7C1480BV25/CY7C1482BV25/CY7C1486BV25, 72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined Sync SRAM
Document Number: 001-15143
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
1024385 See ECN VKN/KKVTMP New Data Sheet
*A
*B
*C
*D
1562944 See ECN
1897447 See ECN
2082487 See ECN
2159486 See ECN
VKN/AESA Removed 1.8V IO offering from the data sheet
VKN/AESA Added footnote 14 related to IDD
VKN
Converted from preliminary to final
VKN/PYRS Minor Change-Moved to the external web
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15143 Rev. *D
Revised February 29, 2008
Page 31 of 31
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this
document may be the trademarks of their respective holders.
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