CY7C149 [CYPRESS]
1K x 4 Static RAM; 1K ×4静态RAM
| 型号： | CY7C149 |
| 厂家： | 
CYPRESS |
| 描述： | 1K x 4 Static RAM |
| 文件： | 总8页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C148
CY7C149
Storage Temperature ......................................−65°C to+150°C
Latch-Up Current..................................................... >200 mA
Ambient Temperature with
Power Applied...................................................−55°C to+125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 18 to Pin 9)....................................................−0.5V to+7.0V
Ambient
Temperature
Range
V
CC
DC Voltage Applied to Outputs
in High Z State......................................................−0.5V to+7.0V
Commercial
0°C to +70°C
5V ± 10%
5V ± 10%
[1]
Military
−55°C to +125°C
DC Input Voltage .................................................−3.0V to +7.0V
Note:
1.
TA is the “instant on” case temperature.
Output Current into Outputs (LOW) .............................20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
[2]
Electrical Characteristics Over the Operating Range
7C148−25
7C149−25
7C148−35, 45
7C149−35, 45
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Test Conditions
= Min., I = −4.0 mA
OH
Min.
Max.
Min.
Max. Unit
V
V
V
2.4
2.4
V
V
OH
CC
CC
V
= Min., I = 8.0 mA
0.4
6.0
0.8
10
0.4
6.0
0.8
10
OL
OL
V
V
2.0
−3.0
−10
−50
2.0
−3.0
−10
−50
V
IH
IL
V
I
I
I
GND < V < V
CC
µA
µA
mA
IX
I
Output Leakage Current GND < V < V Output Disabled
50
50
OZ
CC
O
CC
V
Operating
Max. V , CS < V ,
Com’l
Mil
90
80
CC
CC
IL
Supply Current
Output Open
110
10
I
I
I
Automatic CS
Power-Down Current
Max. V , CS > V
7C148
Only
Com’l
Mil
15
15
mA
mA
mA
SB
PO
OS
CC
IH
IH
10
Peak Power-On
Max. V , CS > V
7C148
Only
Com’l
Mil
10
CC
[3]
Current
10
Output Short
Circuit Current
GND < V < V
Com’l
Mil
±275
±275
±350
O
CC
[4]
Capacitance[5]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
C
Input Capacitance
Output Capacitance
8
8
pF
pF
IN
A
V
= 5.0V
CC
OUT
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up. Otherwise current will exceed values given (CY7C148
only).
4. For test purposes, not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect these parameters.
2
CY7C148
CY7C149
AC Test Loads and Waveforms
R1481
R1481
Ω
Ω
5V
5V
ALL INPUT PULSES
OUTPUT
OUTPUT
3.0V
GND
90%
10%
90%
10%
R2
255
R2
255
30 pF
5 pF
Ω
Ω
< 10 ns
C148–5
< 10 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C148–4
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167
Ω
OUTPUT
1.73V
[2]
Switching Characteristics Over the Operating Range
7C148−25
7C149−25
7C148−35
7C149−35
7C148−45
7C149−45
Parameter
Description
Min.
Max.
Min. Max.
Min. Max.
Unit
READ CYCLE
t
t
Address Valid to Address Do Not Care Time
(Read Cycle Time)
25
35
45
ns
ns
RC
Address Valid to Data Out Valid Delay
(Address Access Time)
25
35
45
AA
[6]
t
t
Chip Select LOW to Data Out Valid (7C148 only)
25
30
35
35
15
45
45
20
ns
ns
ns
ns
ACS1
ACS2
[7]
t
t
Chip Select LOW to Data Out Valid (7C149 only)
15
ACS
[8]
Chip Select LOW to Data Out On
Chip Select HIGH to Data Out Off
7C148
7C149
8
5
0
0
10
5
10
5
LZ
[8]
t
t
t
t
15
20
0
20
30
0
20
30
ns
ns
ns
ns
HZ
Address Unknown to Data Out Unknown Time
Chip Select HIGH to Power-Down Delay 7C148
0
5
OH
PD
Chip Select LOW to Power-Up Delay
7C148
0
0
0
PU
WRITE CYCLE
t
Address Valid to Address Do Not Care
(Write Cycle Time)
25
35
45
ns
WC
[9]
t
t
t
t
t
t
t
t
t
Write Enable LOW to Write Enable HIGH
Address Hold from Write End
20
5
30
5
35
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
WP
WR
[8]
Write Enable to Output in High Z
Data in Valid to Write Enable HIGH
Data Hold Time
0
8
0
8
0
8
WZ
12
0
20
0
20
0
DW
DH
AS
Address Valid to Write Enable LOW
Chip Select LOW to Write Enable HIGH
Write Enable HIGH to Output in Low Z
Address Valid to End of Write
0
0
0
[9]
20
0
30
0
40
0
CW
[8]
OW
20
30
35
AW
Notes:
6. Chip deselected greater than 25 ns prior to selection.
7. Chip deselected less than 25 ns prior to selection.
8. At any given temperature and voltage condition, tHZ is less than tLZ for all devices. Transition is measured ±500 mV from steady-state voltage with specified
loading in part (b) of AC Test Loads.
9. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
CY7C148
CY7C149
Switching Waveforms
[10,11]
Read Cycle No.1
t
RC
ADDRESS
t
AA
t
OH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C148–6
[10,12]
Read Cycle No. 2
t
RC
CS
t
ACS
t
LZ
t
HZ
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
PU
t
PD
ICC
ISB
V
CC
SUPPLY
CURRENT
50%
50%
C148–7
Write Cycle No.1 (WE Controlled)
t
WC
ADDRESS
t
CW
CS
t
t
WA
AW
t
AS
t
WP
WE
t
t
DH
DW
DATA IN
DATA–IN VALID
t
t
OW
WZ
HIGH IMPEDANCE
DATA OUT
DATA UNDEFINED
C148–8
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CS = VIL
12. Address valid prior to or coincident with CS transition LOW.
.
4
CY7C148
CY7C149
Switching Waveforms (continued)
[13]
Write Cycle No. 2 (CSControlled)
t
WC
ADDRESS
t
CW
CS
t
t
WR
AW
t
WP
WE
t
t
DH
DW
DATA IN
DATA VALID
IN
t
WZ
HIGH IMPEDANCE
DATA OUT
DATA UNDEFINED
C148–9
Notes:
13. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs.AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs.OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs.SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.2
1.0
0.8
I
CC
I
CC
1.0
0.8
0.6
V
=5.0V
V
CC
=5.0V
IN
0.6
0.4
60
T =25°C
A
T =25°C
A
40
V
=5.0V
=5.0V
CC
0.4
V
IN
0.2
0.0
20
0
0.2
0.0
I
SB
I
SB
55
25
125
0.0
1.0
2.0
3.0
4.0
−
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE(°C)
OUTPUT VOLTAGE(V)
SUPPLY VOLTAGE(V)
NORMALIZED ACCESS TIME
vs.AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs.OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs.SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
1.2
1.0
1.1
1.0
60
T =25°C
A
V
CC
=5.0V
T =25°C
A
V
CC
=5.0V
40
0.8
0.6
20
0
0.9
0.8
0.0
1.0
2.0
3.0
4.0
55
25
125
−
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE(°C)
OUTPUT VOLTAGE(V)
SUPPLY VOLTAGE(V)
5
CY7C148
CY7C149
Typical DC and AC Characteristics
TYPICAL POWER–ON CURRENT
vs.SUPPLY VOLTAGE(7C148)
TYPICALACCESS TIME CHANGE
vs.OUTPUT LOADING
NORMALIZED I vs.ACCESS TIME
CC
3.0
2.5
2.0
1.5
30.0
1.4
1.3
1.2
25.0
20.0
15.0
T =25°C
A
1K CSPULL–UP
Ω
RESISTORTOV
CC
1.1
1.0
ISB
1.0
0.5
10.0
5.0
V
=4.5V
CC
T =25°C
A
0.9
0.8
0.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
50
60
SUPPLY VOLTAGE(V)
CAPACITANCE(pF)
CYCLE FREQUENCY(MHz)
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C148−25PC
CY7C148−35PC
CY7C148−35DMB
CY7C148−45PC
CY7C148−45DMB
Package Type
25
P3
P3
D4
P3
D4
18-Lead (300-Mil) Molded DIP
18-Lead (300-Mil) Molded DIP
18-Lead (300-Mil) CerDIP
Commercial
Commercial
Military
35
45
18-Lead (300-Mil) Molded DIP
18-Lead (300-Mil) CerDIP
Commercial
Military
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
CY7C149−25PC
CY7C149−35PC
CY7C149−35DMB
CY7C149−35LMB
CY7C149−45PC
CY7C149−45DMB
CY7C149−45LMB
Package Type
18-Lead (300-Mil) Molded DIP
18-Lead (300-Mil) Molded DIP
18-Lead (300-Mil) CerDIP
25
35
P3
P3
Commercial
Commercial
Military
D4
L50
P3
18-Pin Rectangular Leadless Chip Carrier
18-Lead (300-Mil) Molded DIP
45
Commercial
Military
D4
L50
18-Lead (300-Mil) CerDIP
18-Pin Rectangular Leadless Chip Carrier
6
CY7C148
CY7C149
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameters
Subgroups
READ CYCLE
DC Characteristics
t
t
t
t
t
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Parameters
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
RC
AA
I
I
OH
OL
[14]
ACS1
[14]
V
V
IH
IL
ACS2
[15]
Max.
ACS
I
I
I
I
IX
OH
OZ
WRITE CYCLE
CC
[14]
SB
t
t
t
t
t
t
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
WC
WP
WR
DW
DH
AS
AW
Notes:
14. 7C148 only.
15. 7C149 only.
Document #: 38−00031−D
7
CY7C148
CY7C149
18–Lead(300–Mil) CerDIP D4
MIL STD 1835 D 8Config.A
18–Pin RectangularLeadless ChipCarrier L50
MIL STD 1835 C 10A
−
−
−
−
−
−
18–Lead(300–Mil) Molded DIP P3
© Cypress Semiconductor Corporation, 1993. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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