CY7C162-35PC [CYPRESS]
Standard SRAM, 16KX4, 35ns, CMOS, PDIP28, DIP-28;
| 型号： | CY7C162-35PC |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 16KX4, 35ns, CMOS, PDIP28, DIP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C161
CY7C162
16K x 4 Static RAM
with Separate I/O
Easy memory expansion is provided by active LOW chip en-
Features
ables (CE , CE ) and three-state drivers. They have an auto-
1
2
• High speed
matic power-down feature, reducing the power consumption
by 65% when deselected.
— 15-ns
Writing to the device is accomplished when the chip enable
• Transparent write (7C161)
• CMOS for optimum speed/power
• Low active power
(CE , CE ) and write enable (WE) inputs are both LOW. Data
1
2
on the four input pins (I through I ) is written into the memory
0
3
location specified on the address pins (A through A ).
0
13
— 633 mW
Reading the device is accomplished by taking the chip enables
(CE , CE ) LOW while write enable (WE) remains HIGH. Un-
• Low standby power
— 220 mW
1
2
der these conditions the contents of the memory location
specified on the address pins will appear on the four data out-
put pins.
• TTL compatible inputs and outputs
• Automatic power-down when deselected
The output pins stay in a high-impedance state when write
enable (WE) is LOW (7C162 only), or one of the chip enables
Functional Description
(CE , CE ) are HIGH.
1
2
The CY7C161 and CY7C162 are high-performance CMOS
static RAMs organized as 16,384 by 4 bits with separate I/O.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
I
I
0
1
DIP
Top View
I
I
2
3
A
A
A
A
A
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
A
A
A
5
6
7
8
9
CC
4
2
3
3
INPUT BUFFER
4
2
5
A
A
1
0
A
A
A
A
I
6
10
11
12
13
A
A
A
A
A
A
0
1
O
O
0
7
I
7C161
7C162
3
8
I
2
2
3
1
256 x 256
ARRAY
O
9
3
2
1
0
4
5
10
11
12
13
14
O
O
O
0
O
O
2
I
A
A
1
6
7
CE
OE
GND
3
WE
CE
2
POWER
DOWN
COLUMN DECODER
CE
1
CE
2
C162-2
7C162 ONLY
7C161 ONLY
WE
OE
C162-1
Selection Guide[1]
7C161 12
7C161 15
7C161 20
7C161 25
7C161 35
−
−
−
−
−
7C162 12
7C162 15
7C162 20
7C162 25
7C162 35
−
−
−
−
−
Maximum Access Time (ns)
12
160
15
20
80
25
70
35
70
Maximum Operating Current (mA)
Maximum Standby Current (mA)
115
40/20
40/20
40/20
20/20
20/20
Shaded areas indicate preliminary information.
Note:
1. For military specifications, see the CY7C161A/CY7C162A datasheet.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
May 1986 – Revised March 1995
CY7C161
CY7C162
[2]
DC Input Voltage ..............................................−0.5V to +7.0V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .....................................−65°C to +150°C
Latch-Up Current..................................................... >200 mA
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Operating Range
Ambient
Temperature
Supply Voltage to Ground Potential
(Pin 24 to Pin 12)..................................................−0.5V to+7.0V
Range
V
CC
Commercial
0°C to +70°C
5V ± 10%
DC Voltage Applied to Outputs
in High Z State ..................................................−0.5V to+7.0V
[2]
Electrical Characteristics Over the Operating Range
7C161 12
7C161 15
−
7C162 15
−
−
7C162 12
−
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
= Min.,I = −4.0 mA
Min.
Max.
Min.
Max.
Unit
V
V
V
V
2.4
2.4
OH
CC
CC
OH
V
= Min.,I = 8.0 mA
0.4
0.4
V
OL
OL
V
V
2.2
−0.5
−5
V
2.2
−0.5
−5
V
V
IH
IL
CC
CC
[2]
Input LOW Voltage
0.8
+5
+5
0.8
V
I
I
Input Load Current
GND < V < V
CC
+5
+5
µA
µA
IX
I
Output Leakage
Current
GND < V < V ,
CC
−5
−5
OZ
I
Output Disabled
I
I
I
I
Output Short
Circuit Current
V
V
= Max.,
−350
160
40
−350
115
40
mA
mA
mA
mA
OS
CC
[3]
= GND
OUT
V
Operating
V
= Max.,
= 0 mA
CC
CC
CC
Supply Current
I
OUT
Automatic CE
Power-Down Current
Max. V , CE > V
IH
Min. Duty Cycle = 100%
SB1
SB2
1
CC
1
Automatic CE
Max. V , CE > V − 0.3V,
20
20
1
CC
1
CC
Power-Down Current
V > V − 0.3V or V < 0.3V
IN CC IN
Shaded areas indicate preliminary information.
Notes:
2. Minimum voltage is equal to -3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
CY7C161
CY7C162
Electrical Characteristics Over the Operating Range (continued)
7C161 20
7C161 25, 35
−
7C162 25, 35
−
−
7C162 20
−
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
= Min., I = −4.0 mA
Min.
Max.
Min.
Max.
Unit
V
V
V
V
2.4
2.4
OH
CC
CC
OH
V
= Min., I = 8.0 mA
0.4
0.4
V
OL
OL
V
V
2.2
−0.5
−5
V
2.2
−0.5
−5
V
CC
V
IH
IL
CC
[2]
Input LOW Voltage
0.8
+5
0.8
+5
V
I
I
I
Input Load Current
Output Leakage Current
Output Short
GND < V < V
CC
µA
µA
mA
IX
I
GND < V < V ,Output Disabled
−5
+5
−5
+5
OZ
OS
I
CC
V
V
= Max.,
−350
−350
CC
[3]
Circuit Current
= GND
OUT
I
I
I
V
Operating
V
CC
= Max.,
= 0 mA
80
40
20
70
20
20
mA
mA
mA
CC
CC
Supply Current
I
OUT
Automatic CE
Power-Down Current
Max. V , CE > V
IH
Min. Duty Cycle = 100%
SB1
SB2
1
CC
1
Automatic CE
Power-Down Current
Max. V , CE > V − 0.3V,
1
CC
1
CC
V
> V − 0.3V or V < 0.3V
IN
CC
IN
Capacitance[4]
Parameter
Description
Test Conditions
Max.
Unit
C
C
Input Capacitance
Output Capacitance
T = 25°C, f = 1 MHz,
10
10
pF
pF
IN
A
V
= 5.0V
CC
OUT
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481
R1 481
Ω
Ω
5V
5V
ALL INPUT PULSES
90%
OUTPUT
OUTPUT
3.0V
GND
90%
10%
30 pF
5 pF
R2
255
R2
10%
5 ns
255
Ω
Ω
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
5 ns
≤
≤
C162-3
C162-4
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167
Ω
OUTPUT
1.73V
3
CY7C161
CY7C162
[5, 6]
Switching Characteristics Over the Operating Range
7C161 12
7C161 15
7C161 20
7C161 25
7C161 35
−
7C162 35
−
−
−
−
−
7C162 12
7C162 15
7C162 20
7C162 25
−
−
−
−
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
12
3
15
3
20
5
25
5
35
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
Output Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
12
15
20
25
35
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
12
12
15
10
20
10
25
12
35
15
0
3
0
3
3
0
3
5
0
3
5
0
3
5
0
OE HIGH to High Z
7
7
8
8
8
8
10
10
20
12
15
20
[7]
CE LOW to Low Z
[7, 8]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
12
15
20
PD
[9]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
12
8
15
12
12
0
20
15
15
0
20
20
20
0
25
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
0
HA
0
0
0
0
0
SA
8
12
10
0
15
10
0
15
10
0
20
15
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
6
0
HD
[7]
WE HIGH to Low Z (7C162)
3
5
5
5
5
LZWE
HZWE
AWE
ADV
DCE
[7, 8]
WE LOW to High Z
(7C162)
6
7
7
7
10
30
30
35
WE LOW to Data Valid (7C161)
Data Valid to Output Valid (7C161)
CE LOW to Data Valid
12
12
12
15
15
15
20
20
20
25
20
25
Shaded areas indicate preliminary information.
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. Both CE1 and CE2 are represented by CE in the Switching Characteristics and Waveforms sections.
7. At any given temperature and voltage condition, tHZ is less than tLZ for any given device.
8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 LOW, and WE LOW. Both signals must be LOW to initiate a write and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
4
CY7C161
CY7C162
Switching Waveforms[8]
[10,11]
Read Cycle No.1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C162-5
[10,12]
Read Cycle No. 2
t
RC
CE
t
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
DATA VALID
t
LZCE
t
PD
t
PU
ICC
SUPPLY
CURRENT
50%
50%
ISB
C162-6
[9]
Write Cycle No.1 (WE Controlled)
t
WC
ADDRESS
t
SCE
CE
t
t
HA
AW
t
t
SA
PWE
WE
t
t
HD
SD
DATA VALID
DATA IN
IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
t
DATA OUT
(7C162)
DATA UNDEFINED
DATA UNDEFINED
DWE
t
ADV
DATA OUT
(7C161)
DATA VALID
C162-7
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE1, CE2 = VIL.
12. Address valid prior to or coincident with CE1, CE2 transition LOW.
5
CY7C161
CY7C162
Switching Waveforms[8] (Continued)
[9,13]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
t
t
SA
SCE
CE
t
t
HA
AW
t
PWE
t
HZLE
WE
t
t
HD
SD
DATA VALID
IN
DATA IN
t
HZLE
HIGH IMPEDANCE
DATA OUT
(7C162)
t
DCE
DATA OUT
(7C161)
DATA VALID
C162-8
Note:
13. If CEgoes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state (7C162 only).
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.2
1.0
0.8
I
I
CC
CC
1.0
0.8
0.6
V
CC
= 5.0V
0.6
0.4
T
A
= 25°C
60
40
V
V
= 5.0V
= 5.0V
CC
0.4
IN
I
SB
0.2
0.0
20
0
I
SB
0.2
0.0
55
25
125
0.0
1.0
2.0
3.0
4.0
−
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE ( C)
°
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
V
T
= 5.0V
= 25°C
CC
A
1.2
1.0
1.1
1.0
T
A
= 25°C
60
V
CC
= 5.0V
40
0.8
0.6
20
0
0.9
0.8
0.0
1.0
2.0
3.0
4.0
55
25
125
−
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE ( C)
°
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
6
CY7C161
CY7C162
Typical DC and AC Characteristics
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I vs.CYCLETIME
CC
3.0
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
T
V
CC
= 5.0V
= 25°C
= 0.5V
CC
A
2.5
2.0
1.5
1.0
0.5
0.0
10.0
5.0
V
T
= 4.5V
= 25°C
CC
A
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Address Designators
Address
Name
Address
Function
Pin
Number
A5
A6
X3
X4
X5
X6
X7
Y0
Y1
Y5
Y4
Y3
Y2
X0
X1
X2
1
2
A7
3
A8
4
A9
5
A10
A11
A12
A13
A0
6
7
8
9
23
24
25
26
27
A1
A2
A3
A4
7
CY7C161
CY7C162
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C161−12PC
CY7C161−12VC
CY7C161−15PC
CY7C161−15VC
CY7C161−20PC
CY7C161−20VC
CY7C161−25PC
CY7C161−25VC
CY7C161−35PC
CY7C161−35VC
Package Type
12
P21
V21
P21
V21
P21
V21
P21
V21
P21
V21
28-Lead (300-Mil) Molded DIP Commercial
28-Lead Molded SOJ
15
20
25
35
28-Lead (300-Mil) Molded DIP Commercial
28-Lead Molded SOJ
28-Lead (300-Mil) Molded DIP Commercial
28-Lead Molded SOJ
28-Lead (300-Mil) Molded DIP Commercial
28-Lead Molded SOJ
28-Lead (300-Mil) Molded DIP Commercial
28-Lead Molded SOJ
Speed
(ns)
Package
Name
Operating
Ordering Code
CY7C162−12PC
CY7C162−12VC
CY7C162−15PC
CY7C162−15VC
CY7C162−20PC
CY7C162−20VC
CY7C162−25PC
CY7C162−25VC
CY7C162−35PC
CY7C162−35VC
Package Type
Range
12
15
20
25
35
P21
V21
P21
V21
P21
V21
P21
V21
P21
V21
28-Lead (300-Mil) Molded DIP Commercial
28-Lead Molded SOJ
28-Lead (300-Mil) Molded DIP Commercial
28-Lead Molded SOJ
28-Lead (300-Mil) Molded DIP Commercial
28-Lead Molded SOJ
28-Lead (300-Mil) Molded DIP Commercial
28-Lead Molded SOJ
28-Lead (300-Mil) Molded DIP Commercial
28-Lead Molded SOJ
Shaded areas indicate preliminary information.
Document #: 38−00029−I
8
CY7C161
CY7C162
Package Diagrams
28-Lead (300-Mil) Molded DIP P21
28-Lead Molded SOJ V21
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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