CY7C1623KV18-250BZXC [CYPRESS]
144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture; 144兆位的DDR -II SRAM SIO双字突发架构
| 型号： | CY7C1623KV18-250BZXC |
| 厂家： | 
CYPRESS |
| 描述： | 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture |
| 文件： | 总28页 (文件大小：773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1623KV18
144-Mbit DDR-II SIO SRAM Two-Word
Burst Architecture
144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture
Features
Configuration
■ 144-Mbit density (8 M × 18)
CY7C1623KV18 – 8 M × 18
■ 333 MHz clock for high bandwidth
Functional Description
The CY7C1623KV18 is 1.8 V Synchronous Pipelined SRAM,
■ Two-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
equipped with DDR-II SIO (Double Data Rate Separate I/O)
architecture. The DDR-II SIO consists of two separate ports: the
read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. The DDR-II
SIO has separate data inputs and data outputs to completely
eliminate the need to ‘turnaround’ the data bus required with
common I/O devices. Access to each port is accomplished
through a common address bus. Addresses for read and write
are latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read data
is driven on the rising edges of C and C if provided, or on the
rising edge of K and K if C/C are not provided. Each address
location is associated with two 18-bit words that burst
sequentially into or out of the device.
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Synchronous internally self timed writes
■ DDR-II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR-I device with 1 cycle read latency
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from each individual DDR-II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
when DOFF is asserted LOW
■ 1.8 V core power supply with HSTL inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V–VDD
)
❐ Supports both 1.5 V and 1.8 V I/O supply
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
■ Available in 165-ball FBGA package (15 × 17 × 1.4 mm)
■ Offered in Pb-free package
■ JTAG 1149.1 compatible test access port
■ Phase Locked Loop (PLL) for accurate data placement
Selection Guide
Description
Maximum Operating Frequency
333 MHz
333
250 MHz Unit
250
560
MHz
mA
Maximum Operating Current
× 18
650
Cypress Semiconductor Corporation
Document Number: 001-44276 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 28, 2013
CY7C1623KV18
Logic Block Diagram – CY7C1623KV18
18
D[17:0]
Write
Data Reg
Write
Data Reg
22
Address
Register
A(21:0)
LD
R/W
C
K
Control
Logic
CLK
Gen.
K
DOFF
Read Data Reg.
C
CQ
36
18
R/W
CQ
Reg.
Reg.
Reg.
VREF
18
18
Control
Logic
18
LD
18
Q[17:0]
BWS[1:0]
Document Number: 001-44276 Rev. *G
Page 2 of 28
CY7C1623KV18
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................5
Functional Overview ........................................................6
Read Operations .........................................................6
Write Operations .........................................................6
Byte Write Operations .................................................6
Single Clock Mode ......................................................6
DDR Operation ............................................................7
Depth Expansion .........................................................7
Programmable Impedance ..........................................7
Echo Clocks ................................................................7
PLL ..............................................................................7
Application Example ........................................................7
Truth Table ........................................................................8
Write Cycle Descriptions .................................................8
IEEE 1149.1 Serial Boundary Scan (JTAG) ....................9
Disabling the JTAG Feature ........................................9
Test Access Port .........................................................9
Performing a TAP Reset .............................................9
TAP Registers .............................................................9
TAP Instruction Set .....................................................9
TAP Controller State Diagram .......................................11
TAP Controller Block Diagram ......................................12
TAP Electrical Characteristics ......................................12
TAP AC Switching Characteristics ...............................13
TAP Timing and Test Conditions ..................................14
Identification Register Definitions ................................15
Scan Register Sizes .......................................................15
Instruction Codes ...........................................................15
Boundary Scan Order ....................................................16
Power Up Sequence in DDR-II SRAM ...........................17
Power Up Sequence .................................................17
PLL Constraints .........................................................17
Maximum Ratings ...........................................................18
Operating Range .............................................................18
Electrical Characteristics ...............................................18
DC Electrical Characteristics .....................................18
AC Electrical Characteristics .....................................19
Capacitance ....................................................................19
Thermal Resistance ........................................................19
AC Test Loads and Waveforms .....................................19
Switching Characteristics ..............................................20
Switching Waveforms ....................................................22
Ordering Information ......................................................23
Ordering Code Definitions .........................................23
Package Diagram ............................................................24
Acronyms ........................................................................25
Document Conventions .................................................25
Units of Measure .......................................................25
Document History Page .................................................26
Sales, Solutions, and Legal Information ......................28
Worldwide Sales and Design Support .......................28
Products ....................................................................28
PSoC Solutions .........................................................28
Document Number: 001-44276 Rev. *G
Page 3 of 28
CY7C1623KV18
Pin Configurations
The pin configuration for CY7C1623KV18 follows: [1]
Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1623KV18 (8 M × 18)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
BWS1
NC
A
6
7
NC/288M
BWS0
A
8
9
A
10
A
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
A
A
R/W
A
K
LD
Q9
D9
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
Q7
NC
D6
NC
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
D11
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
Q12
D13
VREF
NC
NC
NC
VREF
Q4
D3
G
H
J
K
L
NC
Q15
NC
NC
Q1
NC
D0
M
N
P
R
D17
NC
A
C
A
TCK
A
A
C
A
A
TMS
Note
1. NC/288M is not connected to the die and can be tied to any voltage level.
Document Number: 001-44276 Rev. *G
Page 4 of 28
CY7C1623KV18
Pin Definitions
Pin Name
I/O
Pin Description
D[17:0]
Input-
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
Synchronous
LD
Input-
Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition
Synchronous includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period
of bus activity).
BWS0,
BWS1
Input-
Synchronous
Byte Write Select 0 and 1 Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the
write operations. Bytes not written remain unaltered.
BWS0 controls D[8:0], BWS1 controls D[17:9]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 8 M × 18 (2 arrays each of 4 M × 18). Therefore, only 22 address inputs are needed to
access the entire memory array. These inputs are ignored when the appropriate port is deselected.
Q[17:0]
R/W
C
Outputs-
Synchronous
Data Output Signals. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of both the C and C clocks during read operations, or K and K when in
single clock mode. When the read port is deselected, Q[17:0] are automatically tri-stated.
Input-
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read when
Synchronous R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times
around the edge of K.
Input Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See Application Example on page 7 for further details.
C
Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See Application Example on page 7 for further details.
K
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[17:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device
and to drive out data through Q[17:0] when in single clock mode.
CQ
Echo Clock CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks is shown in the Switching Characteristics on page 20.
CQ
ZQ
Echo Clock CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks is shown in the Switching Characteristics on page 20.
Input
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[17:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DOFF
PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The
timing in the PLL turned off operation differs from those listed in this data sheet. For normal operation,
this pin can be connected to a pull up through a 10-Kohm or less pull up resistor. The device behaves
in DDR-I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of
up to 167 MHz with DDR-I timing.
Document Number: 001-44276 Rev. *G
Page 5 of 28
CY7C1623KV18
Pin Definitions (continued)
Pin Name
TDO
I/O
Output
Input
Input
Input
N/A
Pin Description
TDO Pin for JTAG.
TCK Pin for JTAG.
TDI Pin for JTAG.
TMS Pin for JTAG.
TCK
TDI
TMS
NC
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
VREF
N/A
Input-
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, Outputs, and AC
measurement points.
Reference
VDD
VSS
Power Supply Power Supply Inputs to the Core of the Device.
Ground Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
VDDQ
The CY7C1623KV18 first completes the pending read
transactions, when read access is deselected. Synchronous
internal circuitry automatically tri-states the output following the
next rising edge of the positive output clock (C).
Functional Overview
The CY7C1623KV18 is synchronous pipelined Burst SRAM
equipped with a DDR-II Separate I/O interface, which operates
with a read latency of one and half cycles when DOFF pin is tied
HIGH. When DOFF pin is set LOW or connected to VSS the
device behaves in DDR-I mode with a read latency of one clock
cycle.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register. On the following K clock rise the data presented
to D[17:0] is latched and stored into the 18-bit write data register,
provided BWS[1:0] are both asserted active. On the subsequent
rising edge of the negative input clock (K) the information
presented to D[17:0] is also stored into the write data register,
provided BWS[1:0] are both asserted active. The 36 bits of data
are then written into the memory array at the specified location.
Write accesses can be initiated on every rising edge of the
positive input clock (K). The data flow is pipelined such that
18 bits of data can be transferred into the device on every rising
edge of the input clocks (K and K).
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing is
referenced to the rising edge of the output clocks (C/C, or K/K
when in single clock mode).
All synchronous data inputs (D[17:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[17:0]) pass through output registers
controlled by the rising edge of the output clocks (C/C, or K/K
when in single-clock mode).
All synchronous control (R/W, LD, BWS[0:1]) inputs pass through
input registers controlled by the rising edge of the input clock (K).
When Write access is deselected, the device ignores all inputs
after the pending write operations are completed.
Read Operations
Byte Write Operations
The CY7C1623KV18 is organized internally as two arrays of
4 M × 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to address inputs is stored in
the read address register. Following the next K clock rise the
corresponding lowest order 18-bit word data is driven onto the
Q[17:0] using C as the output timing reference. On the
subsequent rising edge of C, the next 18-bit data word is driven
onto the Q[17:0]. The requested data is valid 0.45 ns from the
rising edge of the output clock (C or C, or K and K when in single
clock mode). Read accesses can be initiated on every rising
edge of the positive input clock (K). The data flow is pipelined
such that data is transferred out of the device on every rising
edge of the output clocks, C/C (or K/K when in single clock
mode).
Byte write operations are supported by the CY7C1623KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify, read, modify, and write operations to a byte write
operation.
Single Clock Mode
The CY7C1623KV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device recognizes only a single pair of input clocks (K and K) that
Document Number: 001-44276 Rev. *G
Page 6 of 28
CY7C1623KV18
control both the input and output registers. This operation is
identical to the operation if the device had zero skew between
the K/K and C/C clocks. All timing parameters remain the same
in this mode. To use this mode of operation, tie C and C HIGH at
power on. This function is a strap option and not alterable during
device operation.
range of RQ to guarantee impedance matching with a tolerance
of ±15 percent is between 175 and 350 , with VDDQ = 1.5 V.
The output impedance is adjusted every 1024 cycles at power
up to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free-running clocks and are
synchronized to the output clock of the DDR-II. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in
Switching Characteristics on page 20.
DDR Operation
The CY7C1623KV18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
double data rate mode of operation.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information must be stored
because the SRAM cannot perform the last word write to the
array without conflicting with the read. The data stays in this
register until the next write cycle occurs. On the first write cycle
after the read(s), the stored data from the earlier write is written
into the SRAM array. This is called a posted write.
PLL
These chips use a Phase Locked Loop (PLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
PLL is locked after 20 s of stable clock. The PLL is also reset
by slowing or stopping the input clocks K and K for a minimum
of 30 ns. However, it is not necessary to reset the PLL to lock it
to the desired frequency. The PLL automatically locks 20 s after
a stable clock is presented. The PLL may be disabled by
applying ground to the DOFF pin. When the PLL is turned off, the
device behaves in DDR-I mode (with one cycle latency and a
longer access time).
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5 times the value of
the intended line impedance driven by the SRAM. The allowable
Application Example
Figure 2 shows four DDR-II SIO used in an application.
Figure 2. Application Example
SRAM 1
ZQ
SRAM 4
ZQ
Q
CQ
CQ#
K#
Q
R = 250Ohms
R = 250Ohms
B
B
Vt
CQ
CQ#
K#
W
W
S
#
D
A
D
S
LD R/W
LD R/W
#
#
A
R
#
#
#
C
C#
K
C C# K
DATA IN
DATA OUT
Address
LD#
Vt
Vt
R
R/W#
BWS#
BUS
MASTER
(CPU
or
ASIC)
SRAM
SRAM
SRAM
1
Input CQ
1 Input CQ#
Input CQ
Input CQ#
4
SRAM
4
Source
K
Source K#
Delayed
K
Delayed K#
R
R
= 50Ohms
Vt
= VREF
Document Number: 001-44276 Rev. *G
Page 7 of 28
CY7C1623KV18
Truth Table
The truth table for CY7C1623KV18 is as follows: [2, 3, 4, 5, 6, 7]
Operation
K
LD R/W
DQ
DQ
Write Cycle:
Load address; wait one cycle;
L–H
L
L
D(A + 0) at K(t + 1) D(A + 1) at K(t + 1)
input write data on consecutive K and K rising edges.
Read Cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
L–H
L
H
Q(A + 0) at C(t + 1) Q(A + 1) at C(t + 2)
NOP: No Operation
L–H
H
X
X
X
High Z
High Z
Standby: Clock Stopped
Stopped
Previous State
Previous State
Write Cycle Descriptions
The write cycle description table for CY7C1623KV18 is as follows: [2, 8]
BWS0 BWS1
K
L–H
–
Comments
During the data portion of a write sequenceboth bytes (D[17:0]) are written into the device.
K
L
L
L
L
L
–
L–H During the data portion of a write sequenceboth bytes (D[17:0]) are written into the device.
H
L–H
–
During the data portion of a write sequenceonly the lower byte (D[8:0]) is written into the device, D[17:9]
remains unaltered.
L
H
H
H
L
L
–
L–H
–
L–H During the data portion of a write sequenceonly the lower byte (D[8:0]) is written into the device, D[17:9]
remains unaltered.
–
During the data portion of a write sequenceonly the upper byte (D[17:9]) is written into the device, D[8:0]
remains unaltered.
L–H During the data portion of a write sequence only the upper byte (D[17:9]) is written into the device,
[8:0] remains unaltered.
D
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS and BWS can be altered on different portions of a write cycle,
0
1
as long as the setup and hold requirements are achieved.
Document Number: 001-44276 Rev. *G
Page 8 of 28
CY7C1623KV18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 12. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard 1149.1-2001. The TAP operates using JEDEC
standard 1.8 V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull up resistor. TDO
must be left unconnected. Upon power up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 11. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order on page 16 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 15.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 15).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 15. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-44276 Rev. *G
Page 9 of 28
CY7C1623KV18
IDCODE
BYPASS
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
SAMPLE/PRELOAD
The boundary scan register has a special bit located at bit 108.
When this scan cell, called the ‘extest output bus tri-state’, is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is pre-set LOW to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
Document Number: 001-44276 Rev. *G
Page 10 of 28
CY7C1623KV18
TAP Controller State Diagram
The state diagram for the TAP controller follows: [9]
TEST-LOGIC
1
RESET
0
1
1
1
SELECT
TEST-LOGIC/
SELECT
0
IR-SCAN
IDLE
DR-SCAN
0
0
1
1
CAPTURE-DR
0
CAPTURE-IR
0
0
0
1
SHIFT-DR
1
SHIFT-IR
1
1
0
EXIT1-DR
0
EXIT1-IR
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
0
UPDATE-DR
1
1
0
Note
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-44276 Rev. *G
Page 11 of 28
CY7C1623KV18
TAP Controller Block Diagram
0
Bypass Register
2
1
1
1
0
0
0
Selection
TDI
Selection
TDO
Instruction Register
Circuitry
Circuitry
31 30
29
.
.
2
Identification Register
.
108
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range
Parameter [10, 11, 12]
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
IOH =2.0 mA
Min
1.4
1.6
–
Max
–
Unit
V
VOH1
VOH2
VOL1
VOL2
VIH
IOH =100 A
IOL = 2.0 mA
IOL = 100 A
–
V
0.4
0.2
V
–
V
0.65 × VDD VDD + 0.3
V
VIL
–0.3
–5
0.35 × VDD
5
V
IX
Input and Output Load Current GND VI VDD
A
Notes
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 18.
11. Overshoot: V < V + 0.85 V (Pulse width less than t /2), Undershoot: V /2).
> 1.5 V (Pulse width less than t
IH(AC)
DDQ
CYC
IL(AC)
CYC
12. All Voltage referenced to Ground.
Document Number: 001-44276 Rev. *G
Page 12 of 28
CY7C1623KV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter [13, 14]
Description
Min
50
–
Max
–
Unit
ns
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
tTF
20
–
MHz
ns
tTH
20
20
tTL
TCK Clock LOW
–
ns
Setup Times
tTMSS
tTDIS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
Notes
13. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
14. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-44276 Rev. *G
Page 13 of 28
CY7C1623KV18
TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions. [15]
Figure 3. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
0.9V
1.8V
50
TDO
0V
Z = 50
0
C = 20 pF
L
t
t
TL
TH
GND
(a)
Test Clock
TCK
t
TCYC
t
TMSH
t
TMSS
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data In
TDI
Test Data Out
TDO
t
TDOV
t
TDOX
Note
15. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-44276 Rev. *G
Page 14 of 28
CY7C1623KV18
Identification Register Definitions
Value
CY7C1623KV18
000
Instruction Field
Description
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Version number.
11010100010010011
00000110100
1
Defines the type of SRAM.
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
109
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-44276 Rev. *G
Page 15 of 28
CY7C1623KV18
Boundary Scan Order
Bit No.
0
Bump ID
6R
Bit No.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
10G
9G
Bit No.
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
Bit No.
84
Bump ID
1J
1
6P
5B
5A
85
2J
2
6N
11F
11G
9F
86
3K
3
7P
4A
87
3J
4
7N
5C
4B
88
2K
5
7R
10F
11E
10E
10D
9E
89
1K
6
8R
3A
90
2L
7
8P
2A
91
3L
8
9R
1A
92
1M
1L
9
11P
10P
10N
9P
2B
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
3B
94
3N
1C
1B
95
3M
1N
96
10M
11N
9M
9D
3D
3C
1D
2C
3E
97
2M
3P
11B
11C
9B
98
99
2N
9N
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
10B
11A
10A
9A
1P
2D
2E
3R
4R
10L
11K
10K
9J
1E
4P
8B
2F
5P
7C
3F
5N
6C
1G
1F
5R
9K
8A
Internal
10J
11J
11H
7A
3G
2G
1H
7B
6B
Document Number: 001-44276 Rev. *G
Page 16 of 28
CY7C1623KV18
PLL Constraints
Power Up Sequence in DDR-II SRAM
■ PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var
DDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
.
■ The PLL functions at frequencies down to 120 MHz.
Power Up Sequence
■ If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 s of stable clock to
relock to the desired clock frequency.
■ Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ
.
❐ Apply VDDQ before VREF or at the same time as VREF
.
❐ Drive DOFF HIGH.
■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 s
to lock the PLL.
Figure 4. Power Up Waveforms
K
K
Unstable Clock
> 20μs Stable clock
Stable)
DDQ
Start Normal
Operation
/
V
Clock Start (Clock Starts after V
DD
Stable (< +/- 0.1V DC per 50ns )
/
/
V
VDDQ
V
VDD
DD
DDQ
Fix HIGH (or tie to V
)
DDQ
DOFF
Document Number: 001-44276 Rev. *G
Page 17 of 28
CY7C1623KV18
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage
(MIL-STD-883, M. 3015) ........................................ > 2001 V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch-up Current ................................................... > 200 mA
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Operating Range
Ambient
Temperature (TA)
[17]
[17]
Supply Voltage on VDD Relative to GND .....–0.5 V to +2.9 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC Applied to Outputs in High Z ......–0.5 V to VDDQ + 0.3 V
DC Input Voltage [16] ...........................–0.5 V to VDD + 0.3 V
Range
VDD
1.8 ± 0.1 V
VDDQ
Commercial
0 °C to +70 °C
1.4 V to
VDD
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [18]
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
1.7
Typ
1.8
1.5
–
Max
Unit
1.9
V
V
VDDQ
VOH
1.4
VDD
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Note 19
Note 20
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VDDQ/2 + 0.12
V
VOL
–
VDDQ/2 + 0.12
V
VOH(LOW)
VOL(LOW)
VIH
IOH =0.1 mA, Nominal Impedance
–
VDDQ
V
IOL = 0.1 mA, Nominal Impedance
–
0.2
VDDQ + 0.3
VREF – 0.1
5
V
VREF + 0.1
–0.3
–
V
VIL
–
V
IX
Input Leakage Current
GND VI VDDQ
5
–
A
A
V
IOZ
Output Leakage Current
Input Reference Voltage [21] Typical Value = 0.75 V
GND VI VDDQ, Output Disabled
5
–
5
VREF
0.68
0.75
–
0.95
[22]
IDD
VDD Operating Supply
VDD = Max, IOUT = 0 mA, 333 MHz (× 18)
–
–
–
–
650
mA
mA
mA
mA
f = fMAX = 1/tCYC
250 MHz (× 18)
333 MHz (× 18)
250 MHz (× 18)
–
560
ISB1
Automatic Power Down
Current
Max VDD
,
–
410
Both Ports Deselected,
–
370
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
Inputs Static
,
Notes
16. Overshoot: V
17. Power up: assumes a linear ramp from 0 V to V
< V
+ 0.85 V (Pulse width less than t
/2), Undershoot: V
> 1.5 V (Pulse width less than t
/2).
IH(AC)
DDQ
CYC
IL(AC)
CYC
within 200 ms. During this time V < V and V
< V
.
DD
DD(min)
IH
DD
DDQ
18. All Voltage referenced to Ground.
19. Outputs are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175 < RQ < 350 .
DDQ
OH
20. Outputs are impedance controlled. I = (V
/2)/(RQ/5) for values of 175 < RQ < 350 .
OL
DDQ
21. V
= 0.68 V or 0.46 V
, whichever is larger, V
= 0.95 V or 0.54 V
, whichever is smaller.
REF(min)
DDQ
REF(max)
DDQ
22. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-44276 Rev. *G
Page 18 of 28
CY7C1623KV18
AC Electrical Characteristics
Over the Operating Range
Parameter [23]
Description
Input HIGH voltage
Input LOW voltage
Test Conditions
Min
VREF + 0.2
–
Typ
–
Max
–
Unit
V
VIH
VIL
–
VREF – 0.2
V
Capacitance
Parameter [24]
Description
Input capacitance
Test Conditions
Max
2
Unit
pF
CIN
CO
TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
Output capacitance
3
pF
Thermal Resistance
165-ballFBGA
Package
Parameter [24]
Description
Test Conditions
Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
12.55
°C/W
JC
Thermal resistance
(junction to case)
2.49
°C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
VREF = 0.75 V
0.75 V
VREF
VREF
0.75 V
R = 50
OUTPUT
[25]
ALL INPUT PULSES
1.25 V
Z = 50
0
OUTPUT
Device
R = 50
L
0.75 V
Under
Device
Under
0.25 V
Test
5 pF
VREF = 0.75 V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250
(b)
250
INCLUDING
JIG AND
SCOPE
(a)
Notes
23. Overshoot: V
< V
+ 0.85 V (Pulse width less than t
/2), Undershoot: V
> 1.5 V (Pulse width less than t
/2).
IH(AC)
DDQ
CYC
IL(AC)
CYC
24. Tested initially and after any design or process change that may affect these parameters.
25. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , V
= 1.5 V, input
DDQ
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5.
OL OH
Document Number: 001-44276 Rev. *G
Page 19 of 28
CY7C1623KV18
Switching Characteristics
Over the Operating Range
Parameters [26, 27]
333 MHz
Max
250 MHz
Unit
Description
Cypress
Consortium
Parameter
Min
Min
Max
Parameter
tPOWER
tCYC
tKH
VDD(typical) to the first access [28]
K clock and C clock cycle time
Input clock (K/K; C/C) HIGH
Input clock (K/K; C/C) LOW
1
–
8.4
–
1
–
8.4
–
ms
ns
ns
ns
ns
tKHKH
tKHKL
tKLKH
tKHKH
3.0
4.0
1.6
1.6
1.8
1.20
1.20
1.35
tKL
–
–
tKHKH
–
–
K clock rise to K clock rise and C to C rise (rising
edge to rising edge)
tKHCH
tKHCH
0
1.30
0
1.8
ns
K/K clock rise to C/C clock rise (rising edge to
rising edge)
Setup Times
tSA
tAVKH
tIVKH
tIVKH
Address setup to K clock rise
0.4
0.4
0.3
–
–
–
0.5
0.5
–
–
–
ns
ns
ns
tSC
Control setup to K clock rise (LD, R/W)
tSCDDR
Double datarate control setup to clock (K/K) rise
(BWS0, BWS1)
0.35
tSD
tDVKH
0.3
–
0.35
–
ns
D[X:0] setup to clock (K/K) rise
Hold Times
tHA
tKHAX
tKHIX
tKHIX
0.4
0.4
0.3
–
–
–
0.5
0.5
–
–
–
ns
ns
ns
Address hold after K clock rise
tHC
Control hold after K clock rise
(LD, R/W)
tHCDDR
Double data rate control hold after clock (K/K)
rise (BWS0, BWS1)
0.35
tHD
tKHDX
0.3
–
0.35
–
ns
D[X:0] hold after clock (K/K) rise
Notes
26. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , V
= 1.5 V, input
DDQ
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5 on page 19.
OL OH
27. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
28. This part has a voltage regulator internally; t
is the time that the power must be supplied above V
initially before a read or write operation can be initiated.
POWER
DD(minimum)
Document Number: 001-44276 Rev. *G
Page 20 of 28
CY7C1623KV18
Switching Characteristics (continued)
Over the Operating Range
Parameters [26, 27]
333 MHz
Max
250 MHz
Unit
Description
Cypress
Consortium
Parameter
Min
Min
Max
Parameter
Output Times
tCO
tCHQV
–
0.45
–
–
0.45
–
ns
ns
C/C clock rise (or K/K in single clock mode) to
data valid
tDOH
tCHQX
–0.45
–0.45
Data output hold after output C/C clock rise
(active to active)
tCCQO
tCQOH
tCQD
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCQHCQL
tCQHCQH
–
0.45
–
–
0.45
–
ns
ns
ns
ns
ns
ns
C/C clock rise to echo clock valid
Echo clock hold after C/C clock rise
Echo clock high to data valid
–0.45
–
–0.45
–
0.25
–
0.30
–
tCQDOH
tCQH
Echo clock high to data invalid
Output clock (CQ/CQ) HIGH [29]
–0.25
1.25
1.25
–0.30
1.75
1.75
–
–
tCQHCQH
CQ clock rise to CQ clock rise
rising edge) [29]
–
–
(rising edge to
Clock (C/C) rise to high Z (active to high Z) [30,
tCHZ
tCHQZ
–
0.45
–
–
0.45
–
ns
ns
31]
Clock (C/C) rise to low Z [30, 31]
tCLZ
tCHQX1
–0.45
–0.45
PLL Timing
tKC Var
tKC Var
Clock phase jitter
–
0.20
–
–
0.20
–
ns
s
ns
tKC lock
tKC lock
tKC Reset
PLL lock time (K, C)
K static to PLL reset
20
30
20
30
tKC Reset
–
–
Notes
29. These parameters are extrapolated from the input timing parameters (t
/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
CYC
design and are not tested in production.
30. t
, t
, are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 19. Transition is measured ±100 mV from steady-state voltage.
CHZ CLZ
31. At any voltage and temperature t
is less than t
and t
less than t
.
CHZ
CLZ
CHZ
CO
Document Number: 001-44276 Rev. *G
Page 21 of 28
CY7C1623KV18
Switching Waveforms
Figure 6. Read/Write/Deselect Sequence [32, 33, 34]
NOP
1
READ
(burst of 2)
2
WRITE
READ
READ
(burst of 2)
3
WRITE
(burst of 2)
4
NOP
7
(burst of 2) (burst of 2)
5
6
8
K
t
t
t
t
KH
KL
CYC
KHKH
K
LD
t
t
SC
HC
R/W
A
A0
A1
A2
A3
A4
t
t
HD
HD
t
t
SA
HA
t
t
SD
SD
D
Q
D20
D21
D30
D31
Q00
Q10
Q11
Q01
Q40
Q41
t
CQD
t
t
CLZ
t
DOH
KHCH
t
KHCH
t
CHZ
t
t
CQDOH
CO
C
t
t
t
KHKH
t
KH
CYC
KL
C#
t
CCQO
t
CQOH
CQ
t
t
t
CQHCQH
CCQO
CQH
t
CQOH
CQ#
DON’T CARE
UNDEFINED
Notes
32. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
33. Outputs are disabled (High Z) one clock cycle after a NOP.
34. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-44276 Rev. *G
Page 22 of 28
CY7C1623KV18
Ordering Information
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
333 CY7C1623KV18-333BZXC
250 CY7C1623KV18-250BZXC
51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
Commercial
Commercial
Ordering Code Definitions
CY
7
C 1623
-
V18
XXX
C
K
X
BZ
Temperature Grade: C = Commercial
Pb-free
Package Type: BZ = 165-ball FBGA
Frequency Range: XXX = 333 MHz or 250 MHz
V18 = 1.8 V
Die Revision
Part Identifier
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-44276 Rev. *G
Page 23 of 28
CY7C1623KV18
Package Diagram
Figure 7. 165-ball FBGA (15 × 17 × 1.40 mm) (0.50 Ball Diameter) Package Outline, 51-85195
51-85195 *C
Document Number: 001-44276 Rev. *G
Page 24 of 28
CY7C1623KV18
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BWS
DDR
DLL
Byte Write Select
Symbol
°C
Unit of Measure
Double Data Rate
Delay Lock Loop
degree Celsius
FIT/Dev
FIT/Mb
MHz
µA
failure in time per device
FBGA
HSTL
I/O
Fine-Pitch Ball Grid Array
High-Speed Transceiver Logic
input/output
failure in time per mega bit
megahertz
microampere
microsecond
milliampere
millimeter
millisecond
nanosecond
ohm
JTAG
LSB
Joint Test Action Group
Least Significant Bit
Logical Single-Bit Upsets
Logical Multi-Bit Upsets
Most Significant Bit
Phase Locked Loop
Quad Data Rate
µs
mA
mm
ms
LSBU
LMBU
MSB
PLL
ns
QDR
SEL
%
percent
Single Event Latch Up
Static Random Access Memory
Test Access Port
pF
picofarad
SRAM
TAP
V
volt
W
watt
TCK
TDI
Test Clock
Test Data-In
TDO
TMS
Test Data-Out
Test Mode Select
Document Number: 001-44276 Rev. *G
Page 25 of 28
CY7C1623KV18
Document History Page
Document Title: CY7C1623KV18, 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture
Document Number: 001-44276
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
1961327
See ECN
VKN /
PYRS
New data sheet.
*A
2555945
08/22/08
VKN /
PYRS
Updated IdentificationRegisterDefinitions (Changed RevisionNumber (31:29)
from 001 to 000).
Updated Power Up Sequence in DDR-II SRAM (Updated description and
Figure 4).
Updated Maximum Ratings (Changed Ambient Temperature with Power
Applied from “–10 °C to +85 °C” to “–55 °C to +125 °C”).
Updated Electrical Characteristics (Changed the maximum values of IDD and
ISB1 parameters).
Updated Thermal Resistance (Included values for 165-ball FBGA package).
*B
3228953
04/15/2011
NJY
Changed status from Preliminary to Final.
Updated Ordering Information (updated part numbers) and added Ordering
Code Definitions.
Updated Package Diagram.
Added Acronyms and Units of Measure.
Updated in new template.
*C
*D
*E
3243572
3275033
3428174
04/28/2011
06/06/2011
11/04/2011
NJY
NJY
NJY
Minor text edits across the document.
No technical updates.
Updated Package Diagram.
Document Number: 001-44276 Rev. *G
Page 26 of 28
CY7C1623KV18
Document History Page (continued)
Document Title: CY7C1623KV18, 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture
Document Number: 001-44276
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
*F
3577172
04/10/2012 AVIA / PRIT Updated Features (Removed CY7C1622KV18, CY7C1629KV18, and
CY7C1624KV18 related information, removed non Pb-free packages).
Updated Configuration (Removed CY7C1622KV18, CY7C1629KV18, and
CY7C1624KV18 related information).
Updated Functional Description (Removed CY7C1622KV18,
CY7C1629KV18, and CY7C1624KV18 related information).
Updated Selection Guide (Removed CY7C1622KV18, CY7C1629KV18, and
CY7C1624KV18 related information, removed 300 MHz, 200 MHz and
167 MHz frequencies related information).
Removed Logic Block Diagram – CY7C1622KV18.
Removed Logic Block Diagram – CY7C1629KV18.
Removed Logic Block Diagram – CY7C1624KV18.
Updated Pin Configurations (Removed CY7C1622KV18, CY7C1629KV18,
and CY7C1624KV18 related information).
Updated Pin Definitions (Removed CY7C1622KV18, CY7C1629KV18, and
CY7C1624KV18 related information).
Updated Functional Overview (Removed CY7C1622KV18, CY7C1629KV18,
and CY7C1624KV18 related information).
Updated Truth Table (Removed CY7C1622KV18, CY7C1629KV18, and
CY7C1624KV18 related information).
Updated Write Cycle Descriptions (Removed CY7C1622KV18 related
information).
Removed Write Cycle Descriptions (Corresponding to CY7C1629KV18 and
CY7C1624KV18).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed
CY7C1622KV18, CY7C1629KV18, and CY7C1624KV18 related information).
Updated Identification Register Definitions (Removed CY7C1622KV18,
CY7C1629KV18, and CY7C1624KV18 related information).
Updated Operating Range (Removed Indsutrial Temperature Range).
Updated Electrical Characteristics (Updated DC Electrical Characteristics
(Removed CY7C1622KV18, CY7C1629KV18, and CY7C1624KV18 related
information, removed 300 MHz, 200 MHz and 167 MHz frequencies related
information)).
Updated Switching Characteristics (Removed 300 MHz, 200 MHz and
167 MHz frequencies related information).
Replaced all instances of IO with I/O across the document.
*G
3947120
03/28/2013
PRIT
No technical updates. Completing sunset review.
Document Number: 001-44276 Rev. *G
Page 27 of 28
CY7C1623KV18
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2008-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-44276 Rev. *G
Revised March 28, 2013
Page 28 of 28
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document
may be the trademarks of their respective holders.
相关型号：
CY7C1625KV18-200BZXC
QDR SRAM, 16MX9, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CYPRESS
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