CY7C1668KV18-450BZXC [CYPRESS]
144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency);
| 型号： | CY7C1668KV18-450BZXC |
| 厂家： | 
CYPRESS |
| 描述： | 144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 双倍数据速率 静态存储器 内存集成电路 |
| 文件： | 总30页 (文件大小：771K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1668KV18
CY7C1670KV18
144-Mbit DDR II+ SRAM Two-Word
Burst Architecture (2.5 Cycle Read Latency)
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
Features
Configurations
■ 144-Mbit density (8 M × 18, 4 M × 36)
■ 550-MHz clock for high bandwidth
With Read Cycle Latency of 2.5 cycles:
CY7C1668KV18 – 8 M × 18
CY7C1670KV18 – 4 M × 36
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at
1100 MHz) at 550 MHz
Functional Description
The CY7C1668KV18, and CY7C1670KV18 are 1.8-V
synchronous pipelined SRAMs equipped with DDR II+
architecture. The DDR II+ consists of an SRAM core with
advanced synchronous peripheral circuitry. Addresses for read
and write are latched on alternate rising edges of the input (K)
clock. Write data is registered on the rising edges of both K and
K. Read data is driven on the rising edges of K and K. Each
address location is associated with two 18-bit words
(CY7C1668KV18), or 36-bit words (CY7C1670KV18) that burst
sequentially into or out of the device.
■ Available in 2.5-clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
■ DDR II+ operates with 2.5-cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR I device with one cycle read latency
when DOFF is asserted LOW
[1]
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
❐ Supports both 1.5-V and 1.8-V I/O supply
■ High-speed transceiver logic (HSTL) inputs and variable drive
HSTL output buffers
For a complete list of related documentation, click here.
■ Available in 165-ball fine pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
■ Offered in Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
Selection Guide
Description
Maximum operating frequency
550 MHz
550
450 MHz Unit
450
790
980
MHz
mA
Maximum operating current
× 18
× 36
910
1140
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
= 1.4 V to V
.
DDQ
DD
Cypress Semiconductor Corporation
Document Number: 001-44062 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 1, 2017
CY7C1668KV18
CY7C1670KV18
Logic Block Diagram – CY7C1668KV18
Write
Reg
Write
Reg
22
A
(21:0)
Address
Register
18
LD
K
K
Output
Logic
Control
CLK
R/W
Gen.
DOFF
Read Data Reg.
36
18
CQ
CQ
V
REF
18
18
Reg.
Reg.
Reg.
Control
Logic
R/W
18
18
BWS
[1:0]
DQ
[17:0]
QVLD
Logic Block Diagram – CY7C1670KV18
Write
Reg
Write
Reg
21
A
(20:0)
Address
Register
36
LD
K
K
Output
Logic
Control
CLK
R/W
Gen.
DOFF
Read Data Reg.
72
36
CQ
CQ
V
REF
36
36
Reg.
Reg.
Reg.
Control
Logic
R/W
36
36
BWS
[3:0]
DQ
[35:0]
QVLD
Document Number: 001-44062 Rev. *K
Page 2 of 30
CY7C1668KV18
CY7C1670KV18
Contents
Pin Configuration .............................................................4
Pin Definitions ..................................................................5
Functional Overview ........................................................6
Read Operations .........................................................6
Write Operations .........................................................6
Byte Write Operations .................................................6
DDR Operation ............................................................6
Depth Expansion .........................................................7
Programmable Impedance ..........................................7
Echo Clocks ................................................................7
Valid Data Indicator (QVLD) ........................................7
PLL ..............................................................................7
Application Example ........................................................7
Truth Table ........................................................................8
Write Cycle Descriptions .................................................8
Write Cycle Descriptions .................................................9
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................10
Disabling the JTAG Feature ......................................10
Test Access Port .......................................................10
Performing a TAP Reset ...........................................10
TAP Registers ...........................................................10
TAP Instruction Set ...................................................10
TAP Controller State Diagram .......................................12
TAP Controller Block Diagram ......................................13
TAP Electrical Characteristics ......................................13
TAP AC Switching Characteristics ...............................14
TAP Timing and Test Conditions ..................................15
Identification Register Definitions ................................16
Scan Register Sizes .......................................................16
Instruction Codes ...........................................................16
Boundary Scan Order ....................................................17
Power Up Sequence in DDR II+ SRAM .........................18
Power Up Sequence .................................................18
PLL Constraints .........................................................18
Maximum Ratings ...........................................................19
Operating Range .............................................................19
Neutron Soft Error Immunity .........................................19
Electrical Characteristics ...............................................19
DC Electrical Characteristics .....................................19
AC Electrical Characteristics .....................................21
Capacitance ....................................................................21
Thermal Resistance ........................................................21
AC Test Loads and Waveforms .....................................21
Switching Characteristics ..............................................22
Switching Waveforms ....................................................24
Read/Write/Deselect Sequence ................................24
Ordering Information ......................................................25
Ordering Code Definitions .........................................25
Package Diagram ............................................................26
Acronyms ........................................................................27
Document Conventions .................................................27
Units of Measure .......................................................27
Document History Page .................................................28
Sales, Solutions, and Legal Information ......................30
Worldwide Sales and Design Support .......................30
Products ....................................................................30
PSoC® Solutions ......................................................30
Cypress Developer Community .................................30
Technical Support .....................................................30
Document Number: 001-44062 Rev. *K
Page 3 of 30
CY7C1668KV18
CY7C1670KV18
Pin Configuration
The pin configuration for CY7C1668KV18, and CY7C1670KV18 follow. [2]
Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1668KV18 (8 M × 18)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
3
4
5
BWS1
NC/288M
A
6
K
7
A
8
9
A
10
A
11
CQ
A
B
C
D
E
F
A
R/W
A
LD
DQ9
NC
NC
K
BWS0
A
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
DQ8
NC
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
DQ7
NC
NC
DQ10
DQ11
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
NC
NC
DQ6
DQ5
NC
DQ12
NC
NC
G
H
J
DQ13
VDDQ
NC
NC
VREF
NC
VREF
DQ4
NC
ZQ
NC
K
L
NC
DQ14
NC
DQ3
DQ2
NC
DQ15
NC
NC
M
N
P
R
NC
DQ1
NC
NC
DQ16
DQ17
A
NC
NC
A
QVLD
NC
A
NC
DQ0
TDI
TCK
A
A
A
A
TMS
CY7C1670KV18 (4 M × 36)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
BWS2
BWS3
A
6
K
7
BWS1
BWS0
A
8
9
A
10
A
11
A
B
C
D
E
F
A
A
R/W
A
LD
CQ
DQ27
NC
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
DQ17
NC
DQ29
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
DQ15
NC
DQ30
DQ31
VREF
NC
G
H
J
NC
VREF
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
NC
DQ33
NC
M
N
P
R
DQ11
NC
DQ35
NC
A
QVLD
NC
A
DQ9
TMS
TCK
A
A
A
A
Note
2. NC/288M is not connected to the die and can be tied to any voltage level.
Document Number: 001-44062 Rev. *K
Page 4 of 30
CY7C1668KV18
CY7C1670KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input Output- Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write
Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the K and K clocks during read operations. When read access is deselected,
Q[x:0] are automatically tri-stated.
CY7C1668KV18 DQ[17:0]
CY7C1670KV18 DQ[35:0]
LD
Input-
Synchronous load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus
Synchronous cycle sequence is defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Byte write select 0, 1, 2, and 3 Active Low. Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1668KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1670KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls
D[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Address inputs. Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
8 M × 18 (2 arrays each of 4 M × 18) for CY7C1668KV18, and 4 M × 36 (2 arrays each of 2 M × 36) for
CY7C1670KV18.
R/W
Input-
Synchronous read or write input. When LD is LOW, this input designates the access type (read when
Synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
QVLD
K
Valid output Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and
to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
Input Clock Negative input clock input. K is used to capture synchronous data being presented to the device and to
K
drive out data through Q[x:0]
.
CQ
Echo Clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock (K)
of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.
Echo Clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock (K)
of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.
CQ
ZQ
Input
Input
Output impedance matching input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
PLL turn off Active Low. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 K or less pull up resistor. The device behaves in DDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR I timing.
Document Number: 001-44062 Rev. *K
Page 5 of 30
CY7C1668KV18
CY7C1670KV18
Pin Definitions (continued)
Pin Name
TDO
I/O
Output
Input
Input
Input
N/A
Pin Description
Test data-out (TDO) pin for JTAG.
Test clock (TCK) pin for JTAG.
Test data-in (TDI) pin for JTAG.
Test mode select (TMS) pin for JTAG.
TCK
TDI
TMS
NC
Not connected to the die: Can be tied to any voltage level.
Not connected to the die: Can be tied to any voltage level.
NC/288M
VREF
Input
Input-
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
Reference measurement points.
VDD
VSS
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
transition between devices without the insertion of wait states in
a depth expanded memory.
Functional Overview
The CY7C1668KV18, and CY7C1670KV18 are synchronous
pipelined Burst SRAMs equipped with a DDR interface, which
operates with a read latency of two and half cycles when DOFF
pin is tied HIGH. When DOFF pin is set LOW or connected to
VSS the device behaves in DDR I mode with a read latency of
one clock cycle.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register. On the following K clock rise, the data
presented to D[17:0] is latched and stored into the 18-bit write
data register, provided BWS[1:0] are both asserted active. On the
subsequent rising edge of the negative input clock (K) the
information presented to D[17:0] is also stored into the write data
register, provided BWS[1:0] are both asserted active. The 36 bits
of data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of
the positive input clock (K). The data flow is pipelined such that
18 bits of data can be transferred into the device on every rising
edge of the input clocks (K and K).
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input and output timing is referenced
from the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the input clocks (K and K).
All synchronous control (R/W, LD, BWS[X:0]) inputs pass through
input registers controlled by the rising edge of the input clock (K).
CY7C1668KV18 is described in the following sections. The
same basic descriptions apply to CY7C1670KV18.
When the write access is deselected, the device ignores all
inputs after the pending write operations have been completed.
Read Operations
Byte Write Operations
The CY7C1668KV18 is organized internally as two arrays of
4 M × 18. Accesses are completed in a burst of 2 sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to the address inputs is stored
in the read address register. Following the next two K clock rise,
the corresponding 18-bit word of data from this address location
is driven onto the Q[17:0] using K as the output timing reference.
On the subsequent rising edge of K, the next 18-bit data word is
driven onto the Q[17:0]. The requested data is valid 0.45 ns from
the rising edge of the input clock (K and K). To maintain the
internal logic, each read access must be allowed to complete.
Read accesses can be initiated on every rising edge of the
positive input clock (K).
Byte write operations are supported by the CY7C1668KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
DDR Operation
The CY7C1668KV18 enables high performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1668KV18 requires two No
Operation (NOP) cycle during transition from a read to a write
When read access is deselected, the CY7C1668KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the output following the next
rising edge of the negative input clock (K). This enables for a
Document Number: 001-44062 Rev. *K
Page 6 of 30
CY7C1668KV18
CY7C1670KV18
cycle. At higher frequencies, some applications require third
NOP cycle to avoid contention.
Echo Clocks
Echo clocks are provided on the DDR II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR II+. CQ is referenced with respect to K and CQ is
referenced with respect to K. These are free-running clocks and
are synchronized to the input clock of the DDR II+. The timing for
the echo clocks is shown in the Switching Characteristics on
page 22.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information is stored because
the SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the read(s),
the stored data from the earlier write is written into the SRAM
array. This is called a Posted write.
Valid Data Indicator (QVLD)
If a read is performed on the same address as the write, in the
previous cycle, the SRAM reads out the most current data. The
SRAM does this by bypassing the memory array and reading the
data from the registers.
QVLD is provided on the DDR II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clock K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in DDR I mode (with one cycle latency and a longer
access time).
Programmable Impedance
Connect an external resistor, RQ, between the ZQ pin on the
SRAM and VSS to enable the SRAM to adjust its output driver
impedance. The value of RQ must be 5 times the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15 percent is between 175 and 350 , with VDDQ = 1.5 V.
The output impedance is adjusted every 1024 cycles upon power
up to account for drifts in supply voltage and temperature.
Application Example
Figure 2 shows two DDR II+ used in an application.
Figure 2. Application Example (Width Expansion)
ZQ
ZQ
SRAM#1
SRAM#2
CQ/CQ
CQ/CQ
RQ
RQ
DQ[x:0]
LD
DQ[x:0]
LD
A
R/W BWS
K
K
A
R/W BWS
K
K
DQ[2x:0]
ADDRESS
LD
R/W
BWS
CLKIN1/CLKIN1
CLKIN2/CLKIN2
SOURCE K
SOURCE K
FPGA / ASIC
Document Number: 001-44062 Rev. *K
Page 7 of 30
CY7C1668KV18
CY7C1670KV18
Truth Table
The truth table for the CY7C1668KV18, and CY7C1670KV18 follow. [3, 4, 5, 6, 7, 8]
Operation
K
LD
R/W
DQ
DQ
Write cycle:
Load address; wait one cycle;
L–H
L
L
D(A) at K(t + 1) D(A+1) at K(t + 1)
input write data on consecutive K and K rising edges.
Read cycle: (2.5 cycle Latency)
Load address; wait two and half cycles;
read data on consecutive K and K rising edges.
L–H
L
H
Q(A) at K(t + 2)
Q(A+1) at K(t + 3)
NOP: No operation
L–H
H
X
X
X
High Z
High Z
Standby: Clock stopped
Stopped
Previous State
Previous State
Write Cycle Descriptions
The write cycle description table for CY7C1668KV18 follows. [3, 9]
BWS0 BWS1
K
Comments
K
L
L
L–H
–
During the data portion of a write sequence
CY7C1668KV18 both bytes (D[17:0]) are written into the device.
L
L
–
L–H
–
L–H During the data portion of a write sequence
CY7C1668KV18 both bytes (D[17:0]) are written into the device.
L
H
H
L
–
During the data portion of a write sequence
CY7C1668KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
L–H During the data portion of a write sequence
CY7C1668KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence
CY7C1668KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L
L–H During the data portion of a write sequence
CY7C1668KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
4. Device powers up deselected with the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. Is based on a write cycle that was initiated in accordance with the Truth Table. BWS , BWS , BWS , and BWS can be altered on different portions of a write cycle, as
0
1
2
3
long as the setup and hold requirements are achieved.
Document Number: 001-44062 Rev. *K
Page 8 of 30
CY7C1668KV18
CY7C1670KV18
Write Cycle Descriptions
The write cycle description table for CY7C1670KV18 follows. [10, 11]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Notes
10. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
11. Is based on a write cycle that was initiated in accordance with the Truth Table on page 8. BWS , BWS , BWS , and BWS can be altered on different portions of a write
0
1
2
3
cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-44062 Rev. *K
Page 9 of 30
CY7C1668KV18
CY7C1670KV18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 13. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard 1149.1-2001. The TAP operates using JEDEC
standard 1.8 V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull up resistor. TDO
must be left unconnected. Upon power up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 12. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order on page 17 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 16.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 16).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 16. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a High Z state.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-44062 Rev. *K
Page 10 of 30
CY7C1668KV18
CY7C1670KV18
IDCODE
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
The boundary scan register has a special bit located at bit 108.
When this scan cell, called the ‘extest output bus tri-state’, is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-44062 Rev. *K
Page 11 of 30
CY7C1668KV18
CY7C1670KV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [12]
TEST-LOGIC
1
RESET
0
1
1
1
SELECT
TEST-LOGIC/
SELECT
0
IR-SCAN
IDLE
DR-SCAN
0
0
1
1
CAPTURE-DR
0
CAPTURE-IR
0
0
0
1
SHIFT-DR
1
SHIFT-IR
1
1
0
EXIT1-DR
0
EXIT1-IR
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
0
UPDATE-DR
1
1
0
Note
12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-44062 Rev. *K
Page 12 of 30
CY7C1668KV18
CY7C1670KV18
TAP Controller Block Diagram
0
Bypass Register
2
1
1
1
0
0
0
Selection
TDI
Selection
TDO
Instruction Register
Circuitry
Circuitry
31 30
29
.
.
2
Identification Register
.
108
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range
Parameter [13, 14, 15]
Description
Output high voltage
Test Conditions
IOH =2.0 mA
Min
1.4
1.6
–
Max
–
Unit
V
VOH1
VOH2
VOL1
VOL2
VIH
Output high voltage
Output low voltage
Output low voltage
Input high voltage
Input low voltage
IOH =100 A
IOL = 2.0 mA
IOL = 100 A
–
V
0.4
0.2
V
–
V
0.65 × VDD VDD + 0.3
V
VIL
–0.3
–5
0.35 × VDD
5
V
IX
Input and output load current
GND VI VDD
A
Notes
13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 19.
14. Overshoot: V (AC) < V + 0.3 V (Pulse width less than t /2).
/2), Undershoot: V (AC) > 0.3 V (Pulse width less than t
IH
DDQ
CYC
IL
CYC
15. All voltage referenced to ground.
Document Number: 001-44062 Rev. *K
Page 13 of 30
CY7C1668KV18
CY7C1670KV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter [16, 17]
Description
Min
50
–
Max
–
Unit
ns
tTCYC
TCK clock cycle time
TCK clock frequency
TCK clock high
tTF
20
–
MHz
ns
tTH
20
20
tTL
TCK clock low
–
ns
Setup Times
tTMSS
tTDIS
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
Output Times
tTDOV
tTDOX
TCK clock low to TDO valid
TCK clock low to TDO invalid
–
0
10
–
ns
ns
Notes
16. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
17. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-44062 Rev. *K
Page 14 of 30
CY7C1668KV18
CY7C1670KV18
TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions. [18]
Figure 3. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
0.9V
1.8V
50
TDO
0V
Z = 50
0
C = 20 pF
L
tTL
tTH
GND
(a)
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Note
18. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-44062 Rev. *K
Page 15 of 30
CY7C1668KV18
CY7C1670KV18
Identification Register Definitions
Value
Instruction Field
Description
CY7C1668KV18
CY7C1670KV18
000
Revision number (31:29)
Cypress device ID (28:12)
Cypress JEDEC ID (11:1)
000
Version number.
11010111000010011
00000110100
11010111000100011
00000110100
Defines the type of SRAM.
Allows unique identification of
SRAM vendor.
ID register presence (0)
1
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
109
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-44062 Rev. *K
Page 16 of 30
CY7C1668KV18
CY7C1670KV18
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
10G
9G
Bit #
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit #
84
Bump ID
1J
1
6P
85
2J
2
6N
11F
11G
9F
86
3K
3
7P
87
3J
4
7N
88
2K
5
7R
10F
11E
10E
10D
9E
89
1K
6
8R
90
2L
7
8P
91
3L
8
9R
92
1M
1L
9
11P
10P
10N
9P
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
94
3N
95
3M
1N
96
10M
11N
9M
9D
97
2M
3P
11B
11C
9B
98
99
2N
9N
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
10B
11A
10A
9A
1P
3R
4R
10L
11K
10K
9J
4P
8B
5P
7C
3F
5N
6C
1G
1F
5R
9K
8A
Internal
10J
11J
11H
7A
3G
2G
1H
7B
6B
Document Number: 001-44062 Rev. *K
Page 17 of 30
CY7C1668KV18
CY7C1670KV18
PLL Constraints
Power Up Sequence in DDR II+ SRAM
■ PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var
DDR II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
.
■ The PLL functions at frequencies down to 120 MHz.
Power Up Sequence
■ If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 s of stable clock to
relock to the desired clock frequency.
■ Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ
.
❐ Apply VDDQ before VREF or at the same time as VREF
.
❐ Drive DOFF HIGH.
■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 s
to lock the PLL
Figure 4. Power Up Waveforms
K
K
Unstable Clock
> 20μs Stable clock
Stable)
DDQ
Start Normal
Operation
/
V
Clock Start (Clock Starts after V
DD
Stable (< +/- 0.1V DC per 50ns )
/
/
V
VDDQ
V
VDD
DD
DDQ
Fix HIGH (or tie to V
)
DDQ
DOFF
Document Number: 001-44062 Rev. *K
Page 18 of 30
CY7C1668KV18
CY7C1670KV18
Maximum Ratings
Operating Range
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Ambient
Temperature (TA)
[20]
[20]
Range
VDD
VDDQ
Storage temperature ................................ –65 °C to +150 °C
Commercial
0 °C to +70 °C
1.8 ± 0.1 V 1.4 V to
VDD
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +2.9 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC applied to outputs in High Z ........–0.5 V to VDDQ + 0.3 V
DC input voltage [19] ...........................–0.5 V to VDD + 0.3 V
Current into outputs (Low) .......................................... 20 mA
Neutron Soft Error Immunity
Test
Parameter Description
Conditions
Typ Max* Unit
LSBU
LMBU
SEL
Logical
single-bit
upsets
25 °C
25 °C
85 °C
197 216 FIT/
Mb
Static discharge voltage
(MIL-STD-883, M 3015) ..........................................> 2001 V
Logical
multi-bit
upsets
0
0
0.01 FIT/
Mb
Latch up current .................................................... > 200 mA
Single event
latch up
0.1 FIT/D
ev
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [21]
VDD
Description
Power supply voltage
I/O supply voltage
Output high voltage
Output low voltage
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Test Conditions
Min
1.7
Typ
1.8
1.5
–
Max
Unit
V
1.9
VDD
VDDQ
VOH
1.4
V
Note 22
Note 23
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
V
VOL
–
V
VOH(LOW)
VOL(LOW)
VIH
IOH =0.1 mA, Nominal impedance
–
V
IOL = 0.1 mA, Nominal impedance
–
0.2
V
VREF + 0.1
–0.15
–
VDDQ + 0.15
VREF – 0.1
2
V
VIL
–
V
IX
Input leakage current
GND VI VDDQ
2
–
A
A
V
IOZ
Output leakage current
Input reference voltage [24] Typical Value = 0.75 V
GND VI VDDQ, Output disabled
2
–
2
VREF
0.68
0.75
0.95
Notes
19. Overshoot: V (AC) < V
20. Power up: assumes a linear ramp from 0 V to V (min) within 200 ms. During this time V < V and V
+ 0.3 V (Pulse width less than t
/2), Undershoot: V (AC) > 0.3 V (Pulse width less than t
/2).
CYC
IH
DDQ
CYC
IL
< V
.
DD
IH
DD
DDQ
DD
21. All voltage referenced to ground.
22. Outputs are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175 < RQ < 350 .
OH
DDQ
23. Outputs are impedance controlled. I = (V
/2)/(RQ/5) for values of 175 < RQ < 350 .
OL
DDQ
24. V
(min) = 0.68 V or 0.46 V
, whichever is larger, V
(max) = 0.95 V or 0.54 V
, whichever is smaller.
DDQ
REF
DDQ
REF
Document Number: 001-44062 Rev. *K
Page 19 of 30
CY7C1668KV18
CY7C1670KV18
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter [21]
Description
Test Conditions
Min
–
Typ
–
Max
910
1140
790
980
500
500
460
460
Unit
[25]
IDD
VDD operating supply
VDD = Max,
550 MHz (× 18)
(× 36)
mA
IOUT = 0 mA,
f = fMAX = 1/tCYC
–
–
450 MHz (× 18)
(× 36)
–
–
mA
mA
mA
–
–
ISB1
Automatic power down
current
Max VDD
,
550 MHz (× 18)
(× 36)
–
–
BothPortsDeselected,
–
–
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
Inputs Static
,
450 MHz (× 18)
(× 36)
–
–
–
–
Note
25. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-44062 Rev. *K
Page 20 of 30
CY7C1668KV18
CY7C1670KV18
AC Electrical Characteristics
Over the Operating Range
Parameter [26]
Description
Test Conditions
Min
VREF + 0.2
–0.24
Typ
–
Max
Unit
V
VIH
VIL
Input high voltage
Input low voltage
VDDQ + 0.24
VREF – 0.2
–
V
Capacitance
Parameter [27]
Description
Test Conditions
Max
4
Unit
pF
CIN
CO
Input capacitance
Output capacitance
TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
4
pF
Thermal Resistance
165-ballFBGA
Package
Parameter [27]
Description
Test Conditions
Unit
JA (0 m/s)
JA (1 m/s)
JA (3 m/s)
Thermal resistance
(junction to ambient)
Socketed on a 170 × 220 × 2.35 mm, eight-layer printed
circuit board
12.23
11.17
10.42
9.34
°C/W
°C/W
°C/W
°C/W
JB
Thermal resistance
(junction to board)
JC
Thermal resistance
(junction to case)
2.10
°C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
VREF = 0.75 V
0.75 V
VREF
VREF
0.75 V
R = 50
OUTPUT
[28]
ALL INPUT PULSES
1.25 V
Z = 50
0
OUTPUT
Device
R = 50
L
0.75V
Under
Device
Under
0.25 V
Test
5 pF
VREF = 0.75 V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250
(b)
250
INCLUDING
JIG AND
SCOPE
(a)
Notes
26. Overshoot: V (AC) < V
27. Tested initially and after any design or process change that may affect these parameters.
+ 0.3 V (Pulse width less than t
/2), Undershoot: V (AC) > 0.3 V (Pulse width less than t
/2).
CYC
IH
DDQ
CYC
IL
28. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V
= 0.75 V, RQ = 250 , V
= 1.5 V, input
DDQ
REF
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5.
OL OH
Document Number: 001-44062 Rev. *K
Page 21 of 30
CY7C1668KV18
CY7C1670KV18
Switching Characteristics
Over the Operating Range [29, 30]
550 MHz
Max
450 MHz
Unit
Cypress Consortium
Parameter Parameter
Description
Min
1
Min
Max
–
tPOWER
tCYC
tKH
VDD(Typical) to the First Access [31]
K Clock Cycle Time
–
8.4
–
1
ms
ns
tKHKH
tKHKL
tKLKH
tKHKH
1.81
0.4
0.4
0.77
2.2
0.4
0.4
0.94
8.4
–
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
tCYC
tCYC
ns
tKL
–
–
tKHKH
K Clock Rise to K Clock Rise
(rising edge to rising edge)
–
–
Setup Times
tSA
tAVKH
tIVKH
tIVKH
Address Setup to K Clock Rise
0.23
0.23
0.18
–
–
–
0.275
0.275
0.22
–
–
–
ns
ns
ns
tSC
Control Setup to K Clock Rise (LD, R/W)
tSCDDR
Double Data Rate Control Setup to Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.18
–
0.22
–
ns
Hold Times
tHA
tKHAX
tKHIX
tKHIX
Address Hold after K Clock Rise
0.23
0.23
0.18
–
–
–
0.275
0.275
0.22
–
–
–
ns
ns
ns
tHC
Control Hold after K Clock Rise (LD, R/W)
tHCDDR
DoubleDataRateControlHoldafterClock(K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.18
–
0.22
–
ns
Notes
29. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V
= 0.75 V, RQ = 250 , V
= 1.5 V, input pulse
REF
DDQ
levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5 on page 21.
OL OH
30. When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
31. This part has an internal voltage regulator; t
is the time that the power is supplied above V min initially before a read or write operation can be initiated.
DD
POWER
Document Number: 001-44062 Rev. *K
Page 22 of 30
CY7C1668KV18
CY7C1670KV18
Switching Characteristics (continued)
Over the Operating Range [29, 30]
Cypress Consortium
550 MHz
Max
450 MHz
Unit
Description
Parameter Parameter
Min
Min
Max
Output Times
tCO
tCHQV
tCHQX
K/K Clock Rise to Data Valid
–
0.45
–
–
0.45
–
ns
ns
tDOH
Data Output Hold after Output K/K Clock Rise
(Active to Active)
–0.45
–0.45
tCCQO
tCQOH
tCQD
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCQHCQL
tCQHCQH
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold after K/K Clock Rise
Echo Clock High to Data Valid
–
0.45
–
–
0.45
–
ns
ns
ns
ns
ns
ns
–0.45
–
–0.45
–
0.15
–
0.15
–
tCQDOH
tCQH
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH [32]
–0.15
0.655
0.655
–0.15
0.85
0.85
–
–
tCQHCQH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge) [32]
–
–
tCHZ
tCHQZ
Clock (K/K) Rise to High Z
(Active to High Z) [33, 34]
–
0.45
–
0.45
ns
tCLZ
tCHQX1
Clock (K/K) Rise to Low Z [33, 34]
Echo Clock High to QVLD Valid [35]
–0.45
–0.15
–
–0.45
–0.15
–
ns
ns
tQVLD
tCQHQVLD
0.15
0.15
PLL Timing
tKC Var
tKC Var
Clock Phase Jitter
–
0.15
–
–
0.15
–
ns
s
ns
tKC lock
tKC Reset
tKC lock
tKC Reset
PLL Lock Time (K)
K Static to PLL Reset [36]
20
30
20
30
–
–
Notes
32. These parameters are extrapolated from the input timing parameters (t
/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
CYC
design and are not tested in production.
33. t
, t
are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 21. Transition is measured 100 mV from steady-state voltage.
CHZ CLZ
34. At any voltage and temperature t
is less than t
and t
less than t
.
CHZ
CLZ
CHZ
CO
35. t
specification is applicable for both rising and falling edges of QVLD signal.
QVLD
36. Hold to >V or <V .
IH
IL
Document Number: 001-44062 Rev. *K
Page 23 of 30
CY7C1668KV18
CY7C1670KV18
Switching Waveforms
Read/Write/Deselect Sequence
Figure 6. Waveform for 2.5 Cycle Read Latency [37, 38, 39]
NOP
1
READ
2
READ
3
NOP
5
NOP
6
WRITE
7
WRITE
8
NOP
11
NOP
4
READ
9
NOP
10
12
K
t
t
t
t
KH
KL
KHKH
CYC
K
LD
t
t
HC
SC
R/W
A
A2
A3
A0
A4
A1
t
QVLD
t
t
t
t
SA HA
QVLD
QVLD
QVLD
t
t
HD
HD
SD
t
t
SD
D21 D30 D31
Q00 Q01 Q10 Q11
D20
Q40
DQ
t
t
DOH
t
CHZ
CLZ
t
t
t
CO
CQD
(Read Latency = 2.5 Cycles)
t
CQDOH
CCQO
CQOH
t
CQ
CQ
t
CQH
t
CQHCQH
t
CCQO
t
CQOH
DON’T CARE
UNDEFINED
Notes
37. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
38. Outputs are disabled (High Z) one clock cycle after a NOP.
39. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-44062 Rev. *K
Page 24 of 30
CY7C1668KV18
CY7C1670KV18
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
450 CY7C1668KV18-450BZXC
CY7C1670KV18-450BZXC
51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
Commercial
550 CY7C1668KV18-550BZXC
CY7C1670KV18-550BZXC
51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY 7 C 16XX
XXX
C
K V18 -
X
BZ
Temperature Grade:
C = Commercial
Pb-free
Package Type: BZ = 165-ball FBGA
Frequency Range: XXX = 450 MHz or 550 MHz
V18 = 1.8 V
Die Revision
Part Identifier: 16XX = 1668 or 1670
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-44062 Rev. *K
Page 25 of 30
CY7C1668KV18
CY7C1670KV18
Package Diagram
Figure 7. 165-ball FBGA (15 × 17 × 1.4 mm (0.50 Ball Diameter)) Package Outline, 51-85195
51-85195 *D
Document Number: 001-44062 Rev. *K
Page 26 of 30
CY7C1668KV18
CY7C1670KV18
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BWS
DDR
DLL
Byte Write Select
Symbol
°C
Unit of Measure
Double Data Rate
Delay Lock Loop
degree Celsius
FIT/Dev
FIT/Mb
MHz
µA
failure in time per device
failure in time per mega bit
megahertz
microampere
microsecond
milliampere
millimeter
FBGA
HSTL
I/O
Fine-Pitch Ball Grid Array
High-Speed Transceiver Logic
Input/Output
µs
JTAG
LSB
Joint Test Action Group
Least Significant Bit
Logical Single-Bit Upsets
Logical Multi-Bit Upsets
Most Significant Bit
Phase Locked Loop
Quad Data Rate
mA
mm
ms
LSBU
LMBU
MSB
PLL
millisecond
nanosecond
ohm
ns
pF
picofarad
QDR
SEL
V
volt
Single Event Latch Up
Static Random Access Memory
Test Access Port
W
watt
SRAM
TAP
TCK
TDI
Test Clock
Test Data-In
TDO
TMS
Test Data-Out
Test Mode Select
Document Number: 001-44062 Rev. *K
Page 27 of 30
CY7C1668KV18
CY7C1670KV18
Document History Page
Document Title: CY7C1668KV18/CY7C1670KV18, 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read
Latency)
Document Number: 001-44062
Submission
Date
Orig. of
Change
Revision
ECN
Description of Change
**
1910807
2556980
See ECN VKN / AESA New data sheet.
*A
08/25/08
VKN /
PYRS
Updated Identification Register Definitions:
Changed Revision Number [31:29] from 001 to 000.
Updated Power Up Sequence in DDR II+ SRAM:
Updated description.
Updated Figure 4.
Updated Electrical Characteristics:
Updated values of IDD and ISB1 parameters.
Updated Thermal Resistance:
Included values.
Updated Switching Characteristics:
Changed maximum value of tKC Var parameter from 0.2 ns to 0.15 ns for
500 MHz speed bin.
*B
2806011
11/12/09
VKN /
PYRS
Added Neutron Soft Error Immunity.
Updated Capacitance:
Changed Input Capacitance (CIN) from 2 pF to 4 pF.
Changed Output Capacitance (CO) from 3 pF to 4 pF.
Updated Switching Characteristics:
Updated maximum value of tCO, tCCQO, tCHZ parameters to 450 ps for 550
MHz, 500 MHz and 450 MHz bins.
Updated minimum value of tDOH, tCQOH, tCLZ parameters to -450 ps for
550 MHz, 500 MHz and 450 MHz bins.
Updated Ordering Information:
Added disclaimer at the top of Ordering Information table.
Updated part numbers.
Updated Package Diagram.
*C
*D
3022441
3242073
09/03/2010
04/27/2011
NJY
NJY
Changed status from Preliminary to Final.
Updated Ordering Information:
Updated part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated Sales, Solutions, and Legal Information.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*E
*F
3275033
3437771
06/06/2011
11/14/2011
NJY
No technical updates.
PRIT
Updated Pin Configuration:
Changed part number densities from CY7C1668KV18 (4 M × 18) and
CY7C1670KV18 (2 M × 36) to CY7C1668KV18 (8 M × 18) and
CY7C1670KV18 (4 M × 36).
Updated Ordering Information:
Removed the following parts namely CY7C1668KV18-450BZXC,
CY7C1668KV18-550BZXC, CY7C1670KV18-450BZXC,
CY7C1670KV18-550BZXC.
*G
4234939
01/02/2014
PRIT
Removed CY7C1666KV18, CY7C1677KV18 parts related information across
the document.
Removed 500 MHz and 400 MHz frequency related information across the
document.
Updated to new template.
Completing Sunset Review.
Document Number: 001-44062 Rev. *K
Page 28 of 30
CY7C1668KV18
CY7C1670KV18
Document History Page (continued)
Document Title: CY7C1668KV18/CY7C1670KV18, 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read
Latency)
Document Number: 001-44062
Submission
Date
Orig. of
Change
Revision
ECN
Description of Change
Updated Application Example:
*H
4372754
05/07/2014
PRIT
Updated Figure 2.
Updated Thermal Resistance:
Updated values of JA parameter.
Included JB parameter and its details.
*I
4573182
5056316
11/18/2014
12/18/2015
PRIT
PRIT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*J
Updated Package Diagram:
spec 51-85195 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*K
5981430
12/01/2017 AESATMP9 Updated logo and copyright.
Document Number: 001-44062 Rev. *K
Page 29 of 30
CY7C1668KV18
CY7C1670KV18
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
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cypress.com/arm
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Automotive
Cypress Developer Community
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Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
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Technical Support
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© Cypress Semiconductor Corporation, 2008-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-44062 Rev. *K
Revised December 1, 2017
Page 30 of 30
相关型号：
CY7C1668KV18-550BZXC
144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CYPRESS
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