CY7C167A-15VCT [CYPRESS]
Standard SRAM, 16KX1, 15ns, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOJ-20;
| 型号： | CY7C167A-15VCT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 16KX1, 15ns, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOJ-20 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
67A
CY7C167A
16K x 1 Static RAM
Functional Description
Features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
The CY7C167A is a high-performance CMOS static RAM or-
ganized as 16,384 words by 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and three-state
drivers. The CY7C167A has an automatic power-down fea-
ture, reducing the power consumption by 67% when
deselected.
— 15 ns
• Low active power
— 495 mW
Writing to the device is accomplished when the Chip Select
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (DI) is written into the memory location specified on
the address pins (A0 through A13).
• Low standby power
— 220 mW
• TTL-compatible inputs and outputs
• Capable of withstanding greater than 2001V electro-
static discharge
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while (WE) remains HIGH. Under these conditions,
the contents of the location specified on the address pins will
appear on the data output (DO) pin.
• VIH of 2.2V
The output pin remains in a high-impedance state when Chip
Enable is HIGH, or Write Enable (WE) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configuration
DIP
Top View
DI
A
A
V
0
1
1
2
3
4
5
6
CC
20
A
A
13
19
18
17
16
15
INPUT BUFFER
A
A
2
3
12
11
10
9
A
A
A
A
A
A
0
A
1
A
A
A
4
5
6
7C167A
A
2
14
13
12
11
8
DO
7
128 x 128
ARRAY
A
3
DO
7
8
A
4
WE
DI
9
A
A
6
5
GND
CE
10
C167A-2
CE
POWER
DOWN
COLUMN
DECODER
WE
C167A-1
Selection Guide
7C167A-15
7C167A-20
7C167A-25
7C167A-35
7C167A-45
Maximum Access Time (ns)
15
90
20
90
25
90
35
90
45
90
Maximum Operating Current (mA)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05027 Rev. **
Revised August 24, 2001
CY7C167A
DC Input Voltage.................................................−3.0V to +7.0V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .....................................−65°C to +150°C
Latch-Up Current..................................................... >200 mA
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
Ambient
(Pin 20 to Pin 10)................................................ −0.5V to +7.0V
Range
Temperature[1]
VCC
DC Voltage Applied to Outputs
in High Z State.................................................... −0.5V to +7.0V
Commercial
0°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
7C167A-15
7C167A-20
7C167A-25
Parameter
VOH
Description
Output High Voltage
Output Low Voltage
Test Conditions
VCC = Min., IOH = −4.0 mA
VCC = Min.,
Min. Max. Min. Max. Min. Max. Unit
2.4
2.4
2.4
V
V
VOL
0.4
0.4
0.4
I
OL = 12.0 mA, 8.0 mA Mil
VIH
VIL
IIX
Input High Voltage
Input Low Voltage[2]
Input Load Current
2.2
−0.5
−10
−10
VCC
0.8
2.2
−0.5
−10
−10
VCC
0.8
2.2
−0.5
−10
−10
VCC
0.8
V
V
GND < VI < VCC
+10
+10
+10
+10
+10
+10
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC
Output Disabled
IOS
ICC
ISB
Output Short
VCC = Max., VOUT = GND
VCC = Max., IOUT = 0 mA
Max. VCC, CE > VIH
−350
90
−350
90
−350
90
mA
mA
mA
Circuit Current[3]
VCC Operating
Supply Current
Automatic CE
40
40
20
Power-Down Current[4]
7C167A-35
7C167A-45
Parameter
VOH
Description
Output High Voltage
Output Low Voltage
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
VCC = Min., IOH = −4.0 mA
2.4
2.4
VOL
VCC = Min.,
0.4
0.4
V
IOL = 12.0 mA, 8.0 mA Mil
VIH
VIL
IIX
Input High Voltage
Input Low Voltage[2]
Input Load Current
2.2
−0.5
−10
−10
VCC
0.8
2.2
−0.5
−10
−10
VCC
0.8
V
V
GND < VI < VCC
+10
+10
+10
+10
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC
Output Disabled
IOS
ICC
Output Short
VCC = Max., VOUT = GND
VCC = Max., IOUT = 0 mA
Max. VCC, CE > VIH
−350
90
−350
90
mA
mA
mA
Circuit Current[3]
VCC Operating
Supply Current
ISB
Automatic CE
20
20
Power-Down Current[4]
Notes:
1. TA is the case temperature.
2. IL min. = −3.0V for pulse durations less than 30 ns.
3. Duration of the short circuit should not exceed 30 seconds.
4. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
V
Document #: 38-05027 Rev. **
Page 2 of 9
CY7C167A
Capacitance[5]
Parameter
Description
Input Capacitance
Test Conditions
Max.
10
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
VCC = 5.0V
COUT
CCE
Output Capacitance
Chip Enable Capacitance
10
pF
6
pF
AC Test Loads and Waveforms
R1 329Ω
R1 329Ω
ALL INPUT PULSES
90%
10%
5V
5V
OUTPUT
3.0V
GND
OUTPUT
90%
10%
< 5 ns
R2
202Ω
R2
202Ω
30 pF
5 pF
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C167A-4
C167A-3
(a)
(b)
Equivalent to:
THÉVENINEQUIVALENT
125Ω
OUTPUT
1.9V
Switching Characteristics Over the Operating Range[6]
7C167A-15 7C167A-20 7C167A-25 7C167A-35 7C167A-45
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
15
5
20
5
25
5
30
5
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
15
15
8
20
20
8
25
25
10
20
30
35
15
20
tOHA
tACE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE LOW to Data Valid
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
5
5
0
45
15
25
5
5
5
5
0
0
0
0
tPD
15
20
WRITE CYCLE[9]
tWC Write Cycle Time
tSCE
tAW
15
12
12
0
20
15
15
0
20
20
20
0
25
25
25
0
40
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
0
0
0
0
tPWE
tSD
12
10
0
15
10
0
15
10
0
20
15
0
20
15
0
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[7, 8]
WE HIGH to Low Z[7]
tHD
tHZWE
7
7
7
10
15
tLZWE
5
5
5
5
5
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.
6. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZ is less than tLZ for any given device.
8.
tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signal must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05027 Rev. **
Page 3 of 9
CY7C167A
Switching Waveforms
Read Cycle No. 1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C167A-5
Read Cycle No. 2[10, 12]
t
RC
CE
t
ACE
t
LZCE
t
HZCE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
PD
t
PU
V
CC
I
CC
SUPPLY
CURRENT
50%
50%
I
SB
C167A-6
Write Cycle No. 1 (WE Controlled)[9]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA VALID
DATA IN
IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
C167A-7
Notes:
10. WE is high for read cycle.
11. Device is continuously selected, CE = VIL
.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05027 Rev. **
Page 4 of 9
CY7C167A
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[9, 13]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA VALID
DATA IN
IN
t
HZWE
HIGH IMPEDANCE
DATA UNDEFINED
DATA I/O
C167A-8
Note:
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05027 Rev. **
Page 5 of 9
CY7C167A
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
60
50
40
30
20
1.4
1.2
1.2
I
CC
1.0
0.8
I
CC
1.0
0.8
0.6
V
CC
= 5.0V
0.6
0.4
T = 25°C
A
V
V
IN
= 5.0V
= 5.0V
CC
0.4
0.2
0.0
10
0
0.2
0.0
I
SB
I
SB
−55
25
125
0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.6
1.4
150
125
100
1.4
1.3
1.2
1.2
1.0
75
50
1.1
T = 25°C
A
V
= 5.0V
CC
T = 25°C
A
V
CC
= 5.0V
1.0
0.9
0.8
0.8
25
0
0.6
-55
0.0 1.0
2.0
3.0
4.0
5.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I
vs. CYCLE TIME
CC
3.0
2.5
2.0
1.5
30.0
1.1
V
= 5.0V
CC
T = 25°C
A
V
IH
= 0.5V
1.0
0.9
0.8
20.0
1.0
0.5
10.0
0.0
V
= 4.5V
CC
T = 25°C
A
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-05027 Rev. **
Page 6 of 9
CY7C167A
Ordering Information
Speed (ns) ICC (mA)
Ordering Code
CY7C167A-15PC
CY7C167A-15VC
CY7C167A-20PC
CY7C167A-20VC
CY7C167A-25PC
CY7C167A-25VC
CY7C167A-35PC
CY7C167A-35VC
CY7C167A-45PC
CY7C167A-45VC
Package Name
Package Type
20-Lead (300-Mil) Molded DIP
20-Lead Molded SOJ
Operating Range
15
20
25
35
45
80
80
60
60
50
P5
V5
P5
V5
P5
V5
P5
V5
P5
V5
Commercial
20-Lead (300-Mil) Molded DIP
20-Lead Molded SOJ
Commercial
Commercial
Commercial
Commercial
20-Lead (300-Mil) Molded DIP
20-Lead Molded SOJ
20-Lead (300-Mil) Molded DIP
20-Lead Molded SOJ
20-Lead (300-Mil) Molded DIP
20-Lead Molded SOJ
Document #: 38-05027 Rev. **
Page 7 of 9
CY7C167A
Package Diagrams
20-Lead (300-Mil) Molded DIP P5
51-85011-A
20-Lead (300-Mil) Molded SOJ V5
51-85029-A
Document #: 38-05027 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C167A
Document Title: CY7C167A 16K x 1 Static RAM
Document Number: 38-05027
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
106813
09/10/01
SZV
Change from Spec number: 38-00093 to 38-05027
Document #: 38-05027 Rev. **
Page 9 of 9
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